sc7280-chrome-common.dtsi 2.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * sc7280 fragment for devices with Chrome bootloader
  4. *
  5. * This file mainly tries to abstract out the memory protections put into
  6. * place by the Chrome bootloader which are different than what's put into
  7. * place by Qualcomm's typical bootloader. It also has a smattering of other
  8. * things that will hold true for any conceivable Chrome design
  9. *
  10. * Copyright 2022 Google LLC.
  11. */
  12. /*
  13. * Reserved memory changes
  14. *
  15. * Delete all unused memory nodes and define the peripheral memory regions
  16. * required by the setup for Chrome boards.
  17. */
  18. /delete-node/ &hyp_mem;
  19. /delete-node/ &xbl_mem;
  20. /delete-node/ &reserved_xbl_uefi_log;
  21. /delete-node/ &sec_apps_mem;
  22. / {
  23. reserved-memory {
  24. adsp_mem: memory@86700000 {
  25. reg = <0x0 0x86700000 0x0 0x2800000>;
  26. no-map;
  27. };
  28. camera_mem: memory@8ad00000 {
  29. reg = <0x0 0x8ad00000 0x0 0x500000>;
  30. no-map;
  31. };
  32. venus_mem: memory@8b200000 {
  33. reg = <0x0 0x8b200000 0x0 0x500000>;
  34. no-map;
  35. };
  36. mpss_mem: memory@8b800000 {
  37. reg = <0x0 0x8b800000 0x0 0xf600000>;
  38. no-map;
  39. };
  40. wpss_mem: memory@9ae00000 {
  41. reg = <0x0 0x9ae00000 0x0 0x1900000>;
  42. no-map;
  43. };
  44. mba_mem: memory@9c700000 {
  45. reg = <0x0 0x9c700000 0x0 0x200000>;
  46. no-map;
  47. };
  48. };
  49. };
  50. /* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
  51. &pmk8350_pon {
  52. status = "disabled";
  53. };
  54. /*
  55. * Chrome designs always boot from SPI flash hooked up to the qspi.
  56. *
  57. * It's expected that all boards will support "dual SPI" at 37.5 MHz.
  58. * If some boards need a different speed or have a package that allows
  59. * Quad SPI together with WP then those boards can easily override.
  60. */
  61. &qspi {
  62. status = "okay";
  63. pinctrl-names = "default";
  64. pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
  65. spi_flash: flash@0 {
  66. compatible = "jedec,spi-nor";
  67. reg = <0>;
  68. spi-max-frequency = <37500000>;
  69. spi-tx-bus-width = <2>;
  70. spi-rx-bus-width = <2>;
  71. };
  72. };
  73. &remoteproc_wpss {
  74. status = "okay";
  75. firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
  76. };
  77. /* Increase the size from 2.5MB to 8MB */
  78. &rmtfs_mem {
  79. reg = <0x0 0x9c900000 0x0 0x800000>;
  80. };
  81. &wifi {
  82. status = "okay";
  83. wifi-firmware {
  84. iommus = <&apps_smmu 0x1c02 0x1>;
  85. };
  86. };