tegra210-p3450-0000.dts 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/gpio-keys.h>
  4. #include <dt-bindings/input/linux-event-codes.h>
  5. #include <dt-bindings/mfd/max77620.h>
  6. #include "tegra210.dtsi"
  7. / {
  8. model = "NVIDIA Jetson Nano Developer Kit";
  9. compatible = "nvidia,p3450-0000", "nvidia,tegra210";
  10. aliases {
  11. ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
  12. rtc0 = "/i2c@7000d000/pmic@3c";
  13. rtc1 = "/rtc@7000e000";
  14. serial0 = &uarta;
  15. };
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. memory@80000000 {
  20. device_type = "memory";
  21. reg = <0x0 0x80000000 0x1 0x0>;
  22. };
  23. pcie@1003000 {
  24. status = "okay";
  25. hvddio-pex-supply = <&vdd_1v8>;
  26. dvddio-pex-supply = <&vdd_pex_1v05>;
  27. vddio-pex-ctl-supply = <&vdd_1v8>;
  28. pci@1,0 {
  29. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
  30. <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
  31. <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
  32. <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
  33. phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
  34. nvidia,num-lanes = <4>;
  35. status = "okay";
  36. };
  37. pci@2,0 {
  38. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
  39. phy-names = "pcie-0";
  40. status = "okay";
  41. ethernet@0,0 {
  42. reg = <0x000000 0 0 0 0>;
  43. local-mac-address = [ 00 00 00 00 00 00 ];
  44. };
  45. };
  46. };
  47. host1x@50000000 {
  48. dpaux@54040000 {
  49. status = "okay";
  50. };
  51. vi@54080000 {
  52. status = "okay";
  53. avdd-dsi-csi-supply = <&vdd_sys_1v2>;
  54. csi@838 {
  55. status = "okay";
  56. };
  57. };
  58. sor@54540000 {
  59. status = "okay";
  60. avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>;
  61. vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
  62. nvidia,xbar-cfg = <2 1 0 3 4>;
  63. nvidia,dpaux = <&dpaux>;
  64. };
  65. sor@54580000 {
  66. status = "okay";
  67. avdd-io-hdmi-dp-supply = <&avdd_1v05>;
  68. vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
  69. hdmi-supply = <&vdd_hdmi>;
  70. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  71. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
  72. GPIO_ACTIVE_LOW>;
  73. nvidia,xbar-cfg = <0 1 2 3 4>;
  74. };
  75. dpaux@545c0000 {
  76. status = "okay";
  77. };
  78. i2c@546c0000 {
  79. status = "okay";
  80. };
  81. };
  82. gpu@57000000 {
  83. vdd-supply = <&vdd_gpu>;
  84. status = "okay";
  85. };
  86. pinmux@700008d4 {
  87. dvfs_pwm_active_state: dvfs_pwm_active {
  88. dvfs_pwm_pbb1 {
  89. nvidia,pins = "dvfs_pwm_pbb1";
  90. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  91. };
  92. };
  93. dvfs_pwm_inactive_state: dvfs_pwm_inactive {
  94. dvfs_pwm_pbb1 {
  95. nvidia,pins = "dvfs_pwm_pbb1";
  96. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  97. };
  98. };
  99. };
  100. /* debug port */
  101. serial@70006000 {
  102. status = "okay";
  103. };
  104. pwm@7000a000 {
  105. status = "okay";
  106. };
  107. i2c@7000c500 {
  108. status = "okay";
  109. clock-frequency = <100000>;
  110. eeprom@50 {
  111. compatible = "atmel,24c02";
  112. reg = <0x50>;
  113. label = "module";
  114. vcc-supply = <&vdd_1v8>;
  115. address-width = <8>;
  116. pagesize = <8>;
  117. size = <256>;
  118. read-only;
  119. };
  120. eeprom@57 {
  121. compatible = "atmel,24c02";
  122. reg = <0x57>;
  123. label = "system";
  124. vcc-supply = <&vdd_1v8>;
  125. address-width = <8>;
  126. pagesize = <8>;
  127. size = <256>;
  128. read-only;
  129. };
  130. };
  131. hdmi_ddc: i2c@7000c700 {
  132. status = "okay";
  133. clock-frequency = <100000>;
  134. };
  135. i2c@7000d000 {
  136. status = "okay";
  137. clock-frequency = <400000>;
  138. pmic: pmic@3c {
  139. compatible = "maxim,max77620";
  140. reg = <0x3c>;
  141. interrupt-parent = <&tegra_pmc>;
  142. interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
  143. #interrupt-cells = <2>;
  144. interrupt-controller;
  145. #gpio-cells = <2>;
  146. gpio-controller;
  147. pinctrl-names = "default";
  148. pinctrl-0 = <&max77620_default>;
  149. max77620_default: pinmux {
  150. gpio0 {
  151. pins = "gpio0";
  152. function = "gpio";
  153. };
  154. gpio1 {
  155. pins = "gpio1";
  156. function = "fps-out";
  157. drive-push-pull = <1>;
  158. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  159. maxim,active-fps-power-up-slot = <0>;
  160. maxim,active-fps-power-down-slot = <7>;
  161. };
  162. gpio2 {
  163. pins = "gpio2";
  164. function = "fps-out";
  165. drive-open-drain = <1>;
  166. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  167. maxim,active-fps-power-up-slot = <0>;
  168. maxim,active-fps-power-down-slot = <7>;
  169. };
  170. gpio3 {
  171. pins = "gpio3";
  172. function = "fps-out";
  173. drive-open-drain = <1>;
  174. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  175. maxim,active-fps-power-up-slot = <4>;
  176. maxim,active-fps-power-down-slot = <3>;
  177. };
  178. gpio4 {
  179. pins = "gpio4";
  180. function = "32k-out1";
  181. };
  182. gpio5_6_7 {
  183. pins = "gpio5", "gpio6", "gpio7";
  184. function = "gpio";
  185. drive-push-pull = <1>;
  186. };
  187. };
  188. fps {
  189. fps0 {
  190. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
  191. maxim,suspend-fps-time-period-us = <5120>;
  192. };
  193. fps1 {
  194. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
  195. maxim,suspend-fps-time-period-us = <5120>;
  196. };
  197. fps2 {
  198. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
  199. };
  200. };
  201. regulators {
  202. in-ldo0-1-supply = <&vdd_pre>;
  203. in-ldo2-supply = <&vdd_3v3_sys>;
  204. in-ldo3-5-supply = <&vdd_1v8>;
  205. in-ldo4-6-supply = <&vdd_5v0_sys>;
  206. in-ldo7-8-supply = <&vdd_pre>;
  207. in-sd0-supply = <&vdd_5v0_sys>;
  208. in-sd1-supply = <&vdd_5v0_sys>;
  209. in-sd2-supply = <&vdd_5v0_sys>;
  210. in-sd3-supply = <&vdd_5v0_sys>;
  211. vdd_soc: sd0 {
  212. regulator-name = "VDD_SOC";
  213. regulator-min-microvolt = <1000000>;
  214. regulator-max-microvolt = <1170000>;
  215. regulator-enable-ramp-delay = <146>;
  216. regulator-ramp-delay = <27500>;
  217. regulator-ramp-delay-scale = <300>;
  218. regulator-always-on;
  219. regulator-boot-on;
  220. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  221. maxim,active-fps-power-up-slot = <1>;
  222. maxim,active-fps-power-down-slot = <6>;
  223. };
  224. vdd_ddr: sd1 {
  225. regulator-name = "VDD_DDR_1V1_PMIC";
  226. regulator-min-microvolt = <1150000>;
  227. regulator-max-microvolt = <1150000>;
  228. regulator-enable-ramp-delay = <176>;
  229. regulator-ramp-delay = <27500>;
  230. regulator-ramp-delay-scale = <300>;
  231. regulator-always-on;
  232. regulator-boot-on;
  233. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  234. maxim,active-fps-power-up-slot = <5>;
  235. maxim,active-fps-power-down-slot = <2>;
  236. };
  237. vdd_pre: sd2 {
  238. regulator-name = "VDD_PRE_REG_1V35";
  239. regulator-min-microvolt = <1350000>;
  240. regulator-max-microvolt = <1350000>;
  241. regulator-enable-ramp-delay = <176>;
  242. regulator-ramp-delay = <27500>;
  243. regulator-ramp-delay-scale = <350>;
  244. regulator-always-on;
  245. regulator-boot-on;
  246. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  247. maxim,active-fps-power-up-slot = <2>;
  248. maxim,active-fps-power-down-slot = <5>;
  249. };
  250. vdd_1v8: sd3 {
  251. regulator-name = "VDD_1V8";
  252. regulator-min-microvolt = <1800000>;
  253. regulator-max-microvolt = <1800000>;
  254. regulator-enable-ramp-delay = <242>;
  255. regulator-ramp-delay = <27500>;
  256. regulator-ramp-delay-scale = <360>;
  257. regulator-always-on;
  258. regulator-boot-on;
  259. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  260. maxim,active-fps-power-up-slot = <3>;
  261. maxim,active-fps-power-down-slot = <4>;
  262. };
  263. vdd_sys_1v2: ldo0 {
  264. regulator-name = "AVDD_SYS_1V2";
  265. regulator-min-microvolt = <1200000>;
  266. regulator-max-microvolt = <1200000>;
  267. regulator-enable-ramp-delay = <26>;
  268. regulator-ramp-delay = <100000>;
  269. regulator-ramp-delay-scale = <200>;
  270. regulator-always-on;
  271. regulator-boot-on;
  272. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  273. maxim,active-fps-power-up-slot = <0>;
  274. maxim,active-fps-power-down-slot = <7>;
  275. };
  276. vdd_pex_1v05: ldo1 {
  277. regulator-name = "VDD_PEX_1V05";
  278. regulator-min-microvolt = <1050000>;
  279. regulator-max-microvolt = <1050000>;
  280. regulator-enable-ramp-delay = <22>;
  281. regulator-ramp-delay = <100000>;
  282. regulator-ramp-delay-scale = <200>;
  283. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  284. maxim,active-fps-power-up-slot = <0>;
  285. maxim,active-fps-power-down-slot = <7>;
  286. };
  287. vddio_sdmmc: ldo2 {
  288. regulator-name = "VDDIO_SDMMC";
  289. regulator-min-microvolt = <1800000>;
  290. regulator-max-microvolt = <3300000>;
  291. regulator-enable-ramp-delay = <62>;
  292. regulator-ramp-delay = <100000>;
  293. regulator-ramp-delay-scale = <200>;
  294. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  295. maxim,active-fps-power-up-slot = <0>;
  296. maxim,active-fps-power-down-slot = <7>;
  297. };
  298. ldo3 {
  299. status = "disabled";
  300. };
  301. vdd_rtc: ldo4 {
  302. regulator-name = "VDD_RTC";
  303. regulator-min-microvolt = <850000>;
  304. regulator-max-microvolt = <1100000>;
  305. regulator-enable-ramp-delay = <22>;
  306. regulator-ramp-delay = <100000>;
  307. regulator-ramp-delay-scale = <200>;
  308. regulator-disable-active-discharge;
  309. regulator-always-on;
  310. regulator-boot-on;
  311. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  312. maxim,active-fps-power-up-slot = <1>;
  313. maxim,active-fps-power-down-slot = <6>;
  314. };
  315. ldo5 {
  316. status = "disabled";
  317. };
  318. ldo6 {
  319. status = "disabled";
  320. };
  321. avdd_1v05_pll: ldo7 {
  322. regulator-name = "AVDD_1V05_PLL";
  323. regulator-min-microvolt = <1050000>;
  324. regulator-max-microvolt = <1050000>;
  325. regulator-enable-ramp-delay = <24>;
  326. regulator-ramp-delay = <100000>;
  327. regulator-ramp-delay-scale = <200>;
  328. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  329. maxim,active-fps-power-up-slot = <3>;
  330. maxim,active-fps-power-down-slot = <4>;
  331. };
  332. avdd_1v05: ldo8 {
  333. regulator-name = "AVDD_SATA_HDMI_DP_1V05";
  334. regulator-min-microvolt = <1050000>;
  335. regulator-max-microvolt = <1050000>;
  336. regulator-enable-ramp-delay = <22>;
  337. regulator-ramp-delay = <100000>;
  338. regulator-ramp-delay-scale = <200>;
  339. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  340. maxim,active-fps-power-up-slot = <6>;
  341. maxim,active-fps-power-down-slot = <1>;
  342. };
  343. };
  344. };
  345. };
  346. pmc@7000e400 {
  347. nvidia,invert-interrupt;
  348. nvidia,suspend-mode = <0>;
  349. nvidia,cpu-pwr-good-time = <0>;
  350. nvidia,cpu-pwr-off-time = <0>;
  351. nvidia,core-pwr-good-time = <4587 3876>;
  352. nvidia,core-pwr-off-time = <39065>;
  353. nvidia,core-power-req-active-high;
  354. nvidia,sys-clock-req-active-high;
  355. };
  356. hda@70030000 {
  357. nvidia,model = "NVIDIA Jetson Nano HDA";
  358. status = "okay";
  359. };
  360. usb@70090000 {
  361. phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
  362. <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
  363. <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
  364. <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
  365. phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
  366. avdd-usb-supply = <&vdd_3v3_sys>;
  367. dvddio-pex-supply = <&vdd_pex_1v05>;
  368. hvddio-pex-supply = <&vdd_1v8>;
  369. status = "okay";
  370. };
  371. padctl@7009f000 {
  372. status = "okay";
  373. avdd-pll-utmip-supply = <&vdd_1v8>;
  374. avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
  375. dvdd-pex-pll-supply = <&vdd_pex_1v05>;
  376. hvdd-pex-pll-e-supply = <&vdd_1v8>;
  377. pads {
  378. usb2 {
  379. status = "okay";
  380. lanes {
  381. micro_b: usb2-0 {
  382. nvidia,function = "xusb";
  383. status = "okay";
  384. };
  385. usb2-1 {
  386. nvidia,function = "xusb";
  387. status = "okay";
  388. };
  389. usb2-2 {
  390. nvidia,function = "xusb";
  391. status = "okay";
  392. };
  393. };
  394. };
  395. pcie {
  396. status = "okay";
  397. lanes {
  398. pcie-0 {
  399. nvidia,function = "pcie-x1";
  400. status = "okay";
  401. };
  402. pcie-1 {
  403. nvidia,function = "pcie-x4";
  404. status = "okay";
  405. };
  406. pcie-2 {
  407. nvidia,function = "pcie-x4";
  408. status = "okay";
  409. };
  410. pcie-3 {
  411. nvidia,function = "pcie-x4";
  412. status = "okay";
  413. };
  414. pcie-4 {
  415. nvidia,function = "pcie-x4";
  416. status = "okay";
  417. };
  418. pcie-5 {
  419. nvidia,function = "usb3-ss";
  420. status = "okay";
  421. };
  422. pcie-6 {
  423. nvidia,function = "usb3-ss";
  424. status = "okay";
  425. };
  426. };
  427. };
  428. };
  429. ports {
  430. usb2-0 {
  431. status = "okay";
  432. mode = "peripheral";
  433. usb-role-switch;
  434. vbus-supply = <&vdd_5v0_usb>;
  435. connector {
  436. compatible = "gpio-usb-b-connector",
  437. "usb-b-connector";
  438. label = "micro-USB";
  439. type = "micro";
  440. vbus-gpios = <&gpio TEGRA_GPIO(CC, 4)
  441. GPIO_ACTIVE_LOW>;
  442. };
  443. };
  444. usb2-1 {
  445. status = "okay";
  446. mode = "host";
  447. };
  448. usb2-2 {
  449. status = "okay";
  450. mode = "host";
  451. };
  452. usb3-0 {
  453. status = "okay";
  454. nvidia,usb2-companion = <1>;
  455. vbus-supply = <&vdd_hub_3v3>;
  456. };
  457. };
  458. };
  459. mmc@700b0000 {
  460. status = "okay";
  461. bus-width = <4>;
  462. cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
  463. disable-wp;
  464. vqmmc-supply = <&vddio_sdmmc>;
  465. vmmc-supply = <&vdd_3v3_sd>;
  466. };
  467. mmc@700b0400 {
  468. status = "okay";
  469. bus-width = <4>;
  470. vqmmc-supply = <&vdd_1v8>;
  471. vmmc-supply = <&vdd_3v3_sys>;
  472. non-removable;
  473. cap-sdio-irq;
  474. keep-power-in-suspend;
  475. wakeup-source;
  476. };
  477. usb@700d0000 {
  478. status = "okay";
  479. phys = <&micro_b>;
  480. phy-names = "usb2-0";
  481. avddio-usb-supply = <&vdd_3v3_sys>;
  482. hvdd-usb-supply = <&vdd_1v8>;
  483. };
  484. clock@70110000 {
  485. status = "okay";
  486. nvidia,cf = <6>;
  487. nvidia,ci = <0>;
  488. nvidia,cg = <2>;
  489. nvidia,droop-ctrl = <0x00000f00>;
  490. nvidia,force-mode = <1>;
  491. nvidia,sample-rate = <25000>;
  492. nvidia,pwm-min-microvolts = <708000>;
  493. nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
  494. nvidia,pwm-to-pmic;
  495. nvidia,pwm-tristate-microvolts = <1000000>;
  496. nvidia,pwm-voltage-step-microvolts = <19200>;
  497. pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
  498. pinctrl-0 = <&dvfs_pwm_active_state>;
  499. pinctrl-1 = <&dvfs_pwm_inactive_state>;
  500. };
  501. aconnect@702c0000 {
  502. status = "okay";
  503. dma-controller@702e2000 {
  504. status = "okay";
  505. };
  506. interrupt-controller@702f9000 {
  507. status = "okay";
  508. };
  509. ahub@702d0800 {
  510. status = "okay";
  511. admaif@702d0000 {
  512. status = "okay";
  513. };
  514. i2s@702d1200 {
  515. status = "okay";
  516. ports {
  517. #address-cells = <1>;
  518. #size-cells = <0>;
  519. port@0 {
  520. reg = <0>;
  521. i2s3_cif_ep: endpoint {
  522. remote-endpoint = <&xbar_i2s3_ep>;
  523. };
  524. };
  525. i2s3_port: port@1 {
  526. reg = <1>;
  527. i2s3_dap_ep: endpoint {
  528. dai-format = "i2s";
  529. /* Placeholder for external Codec */
  530. };
  531. };
  532. };
  533. };
  534. i2s@702d1300 {
  535. status = "okay";
  536. ports {
  537. #address-cells = <1>;
  538. #size-cells = <0>;
  539. port@0 {
  540. reg = <0>;
  541. i2s4_cif_ep: endpoint {
  542. remote-endpoint = <&xbar_i2s4_ep>;
  543. };
  544. };
  545. i2s4_port: port@1 {
  546. reg = <1>;
  547. i2s4_dap_ep: endpoint {
  548. dai-format = "i2s";
  549. /* Placeholder for external Codec */
  550. };
  551. };
  552. };
  553. };
  554. dmic@702d4000 {
  555. status = "okay";
  556. ports {
  557. #address-cells = <1>;
  558. #size-cells = <0>;
  559. port@0 {
  560. reg = <0>;
  561. dmic1_cif_ep: endpoint {
  562. remote-endpoint = <&xbar_dmic1_ep>;
  563. };
  564. };
  565. dmic1_port: port@1 {
  566. reg = <1>;
  567. dmic1_dap_ep: endpoint {
  568. /* Placeholder for external Codec */
  569. };
  570. };
  571. };
  572. };
  573. dmic@702d4100 {
  574. status = "okay";
  575. ports {
  576. #address-cells = <1>;
  577. #size-cells = <0>;
  578. port@0 {
  579. reg = <0>;
  580. dmic2_cif_ep: endpoint {
  581. remote-endpoint = <&xbar_dmic2_ep>;
  582. };
  583. };
  584. dmic2_port: port@1 {
  585. reg = <1>;
  586. dmic2_dap_ep: endpoint {
  587. /* Placeholder for external Codec */
  588. };
  589. };
  590. };
  591. };
  592. sfc@702d2000 {
  593. status = "okay";
  594. ports {
  595. #address-cells = <1>;
  596. #size-cells = <0>;
  597. port@0 {
  598. reg = <0>;
  599. sfc1_cif_in_ep: endpoint {
  600. remote-endpoint = <&xbar_sfc1_in_ep>;
  601. };
  602. };
  603. sfc1_out_port: port@1 {
  604. reg = <1>;
  605. sfc1_cif_out_ep: endpoint {
  606. remote-endpoint = <&xbar_sfc1_out_ep>;
  607. };
  608. };
  609. };
  610. };
  611. sfc@702d2200 {
  612. status = "okay";
  613. ports {
  614. #address-cells = <1>;
  615. #size-cells = <0>;
  616. port@0 {
  617. reg = <0>;
  618. sfc2_cif_in_ep: endpoint {
  619. remote-endpoint = <&xbar_sfc2_in_ep>;
  620. };
  621. };
  622. sfc2_out_port: port@1 {
  623. reg = <1>;
  624. sfc2_cif_out_ep: endpoint {
  625. remote-endpoint = <&xbar_sfc2_out_ep>;
  626. };
  627. };
  628. };
  629. };
  630. sfc@702d2400 {
  631. status = "okay";
  632. ports {
  633. #address-cells = <1>;
  634. #size-cells = <0>;
  635. port@0 {
  636. reg = <0>;
  637. sfc3_cif_in_ep: endpoint {
  638. remote-endpoint = <&xbar_sfc3_in_ep>;
  639. };
  640. };
  641. sfc3_out_port: port@1 {
  642. reg = <1>;
  643. sfc3_cif_out_ep: endpoint {
  644. remote-endpoint = <&xbar_sfc3_out_ep>;
  645. };
  646. };
  647. };
  648. };
  649. sfc@702d2600 {
  650. status = "okay";
  651. ports {
  652. #address-cells = <1>;
  653. #size-cells = <0>;
  654. port@0 {
  655. reg = <0>;
  656. sfc4_cif_in_ep: endpoint {
  657. remote-endpoint = <&xbar_sfc4_in_ep>;
  658. };
  659. };
  660. sfc4_out_port: port@1 {
  661. reg = <1>;
  662. sfc4_cif_out_ep: endpoint {
  663. remote-endpoint = <&xbar_sfc4_out_ep>;
  664. };
  665. };
  666. };
  667. };
  668. mvc@702da000 {
  669. status = "okay";
  670. ports {
  671. #address-cells = <1>;
  672. #size-cells = <0>;
  673. port@0 {
  674. reg = <0>;
  675. mvc1_cif_in_ep: endpoint {
  676. remote-endpoint = <&xbar_mvc1_in_ep>;
  677. };
  678. };
  679. mvc1_out_port: port@1 {
  680. reg = <1>;
  681. mvc1_cif_out_ep: endpoint {
  682. remote-endpoint = <&xbar_mvc1_out_ep>;
  683. };
  684. };
  685. };
  686. };
  687. mvc@702da200 {
  688. status = "okay";
  689. ports {
  690. #address-cells = <1>;
  691. #size-cells = <0>;
  692. port@0 {
  693. reg = <0>;
  694. mvc2_cif_in_ep: endpoint {
  695. remote-endpoint = <&xbar_mvc2_in_ep>;
  696. };
  697. };
  698. mvc2_out_port: port@1 {
  699. reg = <1>;
  700. mvc2_cif_out_ep: endpoint {
  701. remote-endpoint = <&xbar_mvc2_out_ep>;
  702. };
  703. };
  704. };
  705. };
  706. amx@702d3000 {
  707. status = "okay";
  708. ports {
  709. #address-cells = <1>;
  710. #size-cells = <0>;
  711. port@0 {
  712. reg = <0>;
  713. amx1_in1_ep: endpoint {
  714. remote-endpoint = <&xbar_amx1_in1_ep>;
  715. };
  716. };
  717. port@1 {
  718. reg = <1>;
  719. amx1_in2_ep: endpoint {
  720. remote-endpoint = <&xbar_amx1_in2_ep>;
  721. };
  722. };
  723. port@2 {
  724. reg = <2>;
  725. amx1_in3_ep: endpoint {
  726. remote-endpoint = <&xbar_amx1_in3_ep>;
  727. };
  728. };
  729. port@3 {
  730. reg = <3>;
  731. amx1_in4_ep: endpoint {
  732. remote-endpoint = <&xbar_amx1_in4_ep>;
  733. };
  734. };
  735. amx1_out_port: port@4 {
  736. reg = <4>;
  737. amx1_out_ep: endpoint {
  738. remote-endpoint = <&xbar_amx1_out_ep>;
  739. };
  740. };
  741. };
  742. };
  743. amx@702d3100 {
  744. status = "okay";
  745. ports {
  746. #address-cells = <1>;
  747. #size-cells = <0>;
  748. port@0 {
  749. reg = <0>;
  750. amx2_in1_ep: endpoint {
  751. remote-endpoint = <&xbar_amx2_in1_ep>;
  752. };
  753. };
  754. port@1 {
  755. reg = <1>;
  756. amx2_in2_ep: endpoint {
  757. remote-endpoint = <&xbar_amx2_in2_ep>;
  758. };
  759. };
  760. amx2_in3_port: port@2 {
  761. reg = <2>;
  762. amx2_in3_ep: endpoint {
  763. remote-endpoint = <&xbar_amx2_in3_ep>;
  764. };
  765. };
  766. amx2_in4_port: port@3 {
  767. reg = <3>;
  768. amx2_in4_ep: endpoint {
  769. remote-endpoint = <&xbar_amx2_in4_ep>;
  770. };
  771. };
  772. amx2_out_port: port@4 {
  773. reg = <4>;
  774. amx2_out_ep: endpoint {
  775. remote-endpoint = <&xbar_amx2_out_ep>;
  776. };
  777. };
  778. };
  779. };
  780. adx@702d3800 {
  781. status = "okay";
  782. ports {
  783. #address-cells = <1>;
  784. #size-cells = <0>;
  785. port@0 {
  786. reg = <0>;
  787. adx1_in_ep: endpoint {
  788. remote-endpoint = <&xbar_adx1_in_ep>;
  789. };
  790. };
  791. adx1_out1_port: port@1 {
  792. reg = <1>;
  793. adx1_out1_ep: endpoint {
  794. remote-endpoint = <&xbar_adx1_out1_ep>;
  795. };
  796. };
  797. adx1_out2_port: port@2 {
  798. reg = <2>;
  799. adx1_out2_ep: endpoint {
  800. remote-endpoint = <&xbar_adx1_out2_ep>;
  801. };
  802. };
  803. adx1_out3_port: port@3 {
  804. reg = <3>;
  805. adx1_out3_ep: endpoint {
  806. remote-endpoint = <&xbar_adx1_out3_ep>;
  807. };
  808. };
  809. adx1_out4_port: port@4 {
  810. reg = <4>;
  811. adx1_out4_ep: endpoint {
  812. remote-endpoint = <&xbar_adx1_out4_ep>;
  813. };
  814. };
  815. };
  816. };
  817. adx@702d3900 {
  818. status = "okay";
  819. ports {
  820. #address-cells = <1>;
  821. #size-cells = <0>;
  822. port@0 {
  823. reg = <0>;
  824. adx2_in_ep: endpoint {
  825. remote-endpoint = <&xbar_adx2_in_ep>;
  826. };
  827. };
  828. adx2_out1_port: port@1 {
  829. reg = <1>;
  830. adx2_out1_ep: endpoint {
  831. remote-endpoint = <&xbar_adx2_out1_ep>;
  832. };
  833. };
  834. adx2_out2_port: port@2 {
  835. reg = <2>;
  836. adx2_out2_ep: endpoint {
  837. remote-endpoint = <&xbar_adx2_out2_ep>;
  838. };
  839. };
  840. adx2_out3_port: port@3 {
  841. reg = <3>;
  842. adx2_out3_ep: endpoint {
  843. remote-endpoint = <&xbar_adx2_out3_ep>;
  844. };
  845. };
  846. adx2_out4_port: port@4 {
  847. reg = <4>;
  848. adx2_out4_ep: endpoint {
  849. remote-endpoint = <&xbar_adx2_out4_ep>;
  850. };
  851. };
  852. };
  853. };
  854. processing-engine@702d8000 {
  855. status = "okay";
  856. ports {
  857. #address-cells = <1>;
  858. #size-cells = <0>;
  859. port@0 {
  860. reg = <0x0>;
  861. ope1_cif_in_ep: endpoint {
  862. remote-endpoint = <&xbar_ope1_in_ep>;
  863. };
  864. };
  865. ope1_out_port: port@1 {
  866. reg = <0x1>;
  867. ope1_cif_out_ep: endpoint {
  868. remote-endpoint = <&xbar_ope1_out_ep>;
  869. };
  870. };
  871. };
  872. };
  873. processing-engine@702d8400 {
  874. status = "okay";
  875. ports {
  876. #address-cells = <1>;
  877. #size-cells = <0>;
  878. port@0 {
  879. reg = <0x0>;
  880. ope2_cif_in_ep: endpoint {
  881. remote-endpoint = <&xbar_ope2_in_ep>;
  882. };
  883. };
  884. ope2_out_port: port@1 {
  885. reg = <0x1>;
  886. ope2_cif_out_ep: endpoint {
  887. remote-endpoint = <&xbar_ope2_out_ep>;
  888. };
  889. };
  890. };
  891. };
  892. amixer@702dbb00 {
  893. status = "okay";
  894. ports {
  895. #address-cells = <1>;
  896. #size-cells = <0>;
  897. port@0 {
  898. reg = <0x0>;
  899. mixer_in1_ep: endpoint {
  900. remote-endpoint = <&xbar_mixer_in1_ep>;
  901. };
  902. };
  903. port@1 {
  904. reg = <0x1>;
  905. mixer_in2_ep: endpoint {
  906. remote-endpoint = <&xbar_mixer_in2_ep>;
  907. };
  908. };
  909. port@2 {
  910. reg = <0x2>;
  911. mixer_in3_ep: endpoint {
  912. remote-endpoint = <&xbar_mixer_in3_ep>;
  913. };
  914. };
  915. port@3 {
  916. reg = <0x3>;
  917. mixer_in4_ep: endpoint {
  918. remote-endpoint = <&xbar_mixer_in4_ep>;
  919. };
  920. };
  921. port@4 {
  922. reg = <0x4>;
  923. mixer_in5_ep: endpoint {
  924. remote-endpoint = <&xbar_mixer_in5_ep>;
  925. };
  926. };
  927. port@5 {
  928. reg = <0x5>;
  929. mixer_in6_ep: endpoint {
  930. remote-endpoint = <&xbar_mixer_in6_ep>;
  931. };
  932. };
  933. port@6 {
  934. reg = <0x6>;
  935. mixer_in7_ep: endpoint {
  936. remote-endpoint = <&xbar_mixer_in7_ep>;
  937. };
  938. };
  939. port@7 {
  940. reg = <0x7>;
  941. mixer_in8_ep: endpoint {
  942. remote-endpoint = <&xbar_mixer_in8_ep>;
  943. };
  944. };
  945. port@8 {
  946. reg = <0x8>;
  947. mixer_in9_ep: endpoint {
  948. remote-endpoint = <&xbar_mixer_in9_ep>;
  949. };
  950. };
  951. port@9 {
  952. reg = <0x9>;
  953. mixer_in10_ep: endpoint {
  954. remote-endpoint = <&xbar_mixer_in10_ep>;
  955. };
  956. };
  957. mixer_out1_port: port@a {
  958. reg = <0xa>;
  959. mixer_out1_ep: endpoint {
  960. remote-endpoint = <&xbar_mixer_out1_ep>;
  961. };
  962. };
  963. mixer_out2_port: port@b {
  964. reg = <0xb>;
  965. mixer_out2_ep: endpoint {
  966. remote-endpoint = <&xbar_mixer_out2_ep>;
  967. };
  968. };
  969. mixer_out3_port: port@c {
  970. reg = <0xc>;
  971. mixer_out3_ep: endpoint {
  972. remote-endpoint = <&xbar_mixer_out3_ep>;
  973. };
  974. };
  975. mixer_out4_port: port@d {
  976. reg = <0xd>;
  977. mixer_out4_ep: endpoint {
  978. remote-endpoint = <&xbar_mixer_out4_ep>;
  979. };
  980. };
  981. mixer_out5_port: port@e {
  982. reg = <0xe>;
  983. mixer_out5_ep: endpoint {
  984. remote-endpoint = <&xbar_mixer_out5_ep>;
  985. };
  986. };
  987. };
  988. };
  989. ports {
  990. xbar_i2s3_port: port@c {
  991. reg = <0xc>;
  992. xbar_i2s3_ep: endpoint {
  993. remote-endpoint = <&i2s3_cif_ep>;
  994. };
  995. };
  996. xbar_i2s4_port: port@d {
  997. reg = <0xd>;
  998. xbar_i2s4_ep: endpoint {
  999. remote-endpoint = <&i2s4_cif_ep>;
  1000. };
  1001. };
  1002. xbar_dmic1_port: port@f {
  1003. reg = <0xf>;
  1004. xbar_dmic1_ep: endpoint {
  1005. remote-endpoint = <&dmic1_cif_ep>;
  1006. };
  1007. };
  1008. xbar_dmic2_port: port@10 {
  1009. reg = <0x10>;
  1010. xbar_dmic2_ep: endpoint {
  1011. remote-endpoint = <&dmic2_cif_ep>;
  1012. };
  1013. };
  1014. xbar_sfc1_in_port: port@12 {
  1015. reg = <0x12>;
  1016. xbar_sfc1_in_ep: endpoint {
  1017. remote-endpoint = <&sfc1_cif_in_ep>;
  1018. };
  1019. };
  1020. port@13 {
  1021. reg = <0x13>;
  1022. xbar_sfc1_out_ep: endpoint {
  1023. remote-endpoint = <&sfc1_cif_out_ep>;
  1024. };
  1025. };
  1026. xbar_sfc2_in_port: port@14 {
  1027. reg = <0x14>;
  1028. xbar_sfc2_in_ep: endpoint {
  1029. remote-endpoint = <&sfc2_cif_in_ep>;
  1030. };
  1031. };
  1032. port@15 {
  1033. reg = <0x15>;
  1034. xbar_sfc2_out_ep: endpoint {
  1035. remote-endpoint = <&sfc2_cif_out_ep>;
  1036. };
  1037. };
  1038. xbar_sfc3_in_port: port@16 {
  1039. reg = <0x16>;
  1040. xbar_sfc3_in_ep: endpoint {
  1041. remote-endpoint = <&sfc3_cif_in_ep>;
  1042. };
  1043. };
  1044. port@17 {
  1045. reg = <0x17>;
  1046. xbar_sfc3_out_ep: endpoint {
  1047. remote-endpoint = <&sfc3_cif_out_ep>;
  1048. };
  1049. };
  1050. xbar_sfc4_in_port: port@18 {
  1051. reg = <0x18>;
  1052. xbar_sfc4_in_ep: endpoint {
  1053. remote-endpoint = <&sfc4_cif_in_ep>;
  1054. };
  1055. };
  1056. port@19 {
  1057. reg = <0x19>;
  1058. xbar_sfc4_out_ep: endpoint {
  1059. remote-endpoint = <&sfc4_cif_out_ep>;
  1060. };
  1061. };
  1062. xbar_mvc1_in_port: port@1a {
  1063. reg = <0x1a>;
  1064. xbar_mvc1_in_ep: endpoint {
  1065. remote-endpoint = <&mvc1_cif_in_ep>;
  1066. };
  1067. };
  1068. port@1b {
  1069. reg = <0x1b>;
  1070. xbar_mvc1_out_ep: endpoint {
  1071. remote-endpoint = <&mvc1_cif_out_ep>;
  1072. };
  1073. };
  1074. xbar_mvc2_in_port: port@1c {
  1075. reg = <0x1c>;
  1076. xbar_mvc2_in_ep: endpoint {
  1077. remote-endpoint = <&mvc2_cif_in_ep>;
  1078. };
  1079. };
  1080. port@1d {
  1081. reg = <0x1d>;
  1082. xbar_mvc2_out_ep: endpoint {
  1083. remote-endpoint = <&mvc2_cif_out_ep>;
  1084. };
  1085. };
  1086. xbar_amx1_in1_port: port@1e {
  1087. reg = <0x1e>;
  1088. xbar_amx1_in1_ep: endpoint {
  1089. remote-endpoint = <&amx1_in1_ep>;
  1090. };
  1091. };
  1092. xbar_amx1_in2_port: port@1f {
  1093. reg = <0x1f>;
  1094. xbar_amx1_in2_ep: endpoint {
  1095. remote-endpoint = <&amx1_in2_ep>;
  1096. };
  1097. };
  1098. xbar_amx1_in3_port: port@20 {
  1099. reg = <0x20>;
  1100. xbar_amx1_in3_ep: endpoint {
  1101. remote-endpoint = <&amx1_in3_ep>;
  1102. };
  1103. };
  1104. xbar_amx1_in4_port: port@21 {
  1105. reg = <0x21>;
  1106. xbar_amx1_in4_ep: endpoint {
  1107. remote-endpoint = <&amx1_in4_ep>;
  1108. };
  1109. };
  1110. port@22 {
  1111. reg = <0x22>;
  1112. xbar_amx1_out_ep: endpoint {
  1113. remote-endpoint = <&amx1_out_ep>;
  1114. };
  1115. };
  1116. xbar_amx2_in1_port: port@23 {
  1117. reg = <0x23>;
  1118. xbar_amx2_in1_ep: endpoint {
  1119. remote-endpoint = <&amx2_in1_ep>;
  1120. };
  1121. };
  1122. xbar_amx2_in2_port: port@24 {
  1123. reg = <0x24>;
  1124. xbar_amx2_in2_ep: endpoint {
  1125. remote-endpoint = <&amx2_in2_ep>;
  1126. };
  1127. };
  1128. xbar_amx2_in3_port: port@25 {
  1129. reg = <0x25>;
  1130. xbar_amx2_in3_ep: endpoint {
  1131. remote-endpoint = <&amx2_in3_ep>;
  1132. };
  1133. };
  1134. xbar_amx2_in4_port: port@26 {
  1135. reg = <0x26>;
  1136. xbar_amx2_in4_ep: endpoint {
  1137. remote-endpoint = <&amx2_in4_ep>;
  1138. };
  1139. };
  1140. port@27 {
  1141. reg = <0x27>;
  1142. xbar_amx2_out_ep: endpoint {
  1143. remote-endpoint = <&amx2_out_ep>;
  1144. };
  1145. };
  1146. xbar_adx1_in_port: port@28 {
  1147. reg = <0x28>;
  1148. xbar_adx1_in_ep: endpoint {
  1149. remote-endpoint = <&adx1_in_ep>;
  1150. };
  1151. };
  1152. port@29 {
  1153. reg = <0x29>;
  1154. xbar_adx1_out1_ep: endpoint {
  1155. remote-endpoint = <&adx1_out1_ep>;
  1156. };
  1157. };
  1158. port@2a {
  1159. reg = <0x2a>;
  1160. xbar_adx1_out2_ep: endpoint {
  1161. remote-endpoint = <&adx1_out2_ep>;
  1162. };
  1163. };
  1164. port@2b {
  1165. reg = <0x2b>;
  1166. xbar_adx1_out3_ep: endpoint {
  1167. remote-endpoint = <&adx1_out3_ep>;
  1168. };
  1169. };
  1170. port@2c {
  1171. reg = <0x2c>;
  1172. xbar_adx1_out4_ep: endpoint {
  1173. remote-endpoint = <&adx1_out4_ep>;
  1174. };
  1175. };
  1176. xbar_adx2_in_port: port@2d {
  1177. reg = <0x2d>;
  1178. xbar_adx2_in_ep: endpoint {
  1179. remote-endpoint = <&adx2_in_ep>;
  1180. };
  1181. };
  1182. port@2e {
  1183. reg = <0x2e>;
  1184. xbar_adx2_out1_ep: endpoint {
  1185. remote-endpoint = <&adx2_out1_ep>;
  1186. };
  1187. };
  1188. port@2f {
  1189. reg = <0x2f>;
  1190. xbar_adx2_out2_ep: endpoint {
  1191. remote-endpoint = <&adx2_out2_ep>;
  1192. };
  1193. };
  1194. port@30 {
  1195. reg = <0x30>;
  1196. xbar_adx2_out3_ep: endpoint {
  1197. remote-endpoint = <&adx2_out3_ep>;
  1198. };
  1199. };
  1200. port@31 {
  1201. reg = <0x31>;
  1202. xbar_adx2_out4_ep: endpoint {
  1203. remote-endpoint = <&adx2_out4_ep>;
  1204. };
  1205. };
  1206. xbar_mixer_in1_port: port@32 {
  1207. reg = <0x32>;
  1208. xbar_mixer_in1_ep: endpoint {
  1209. remote-endpoint = <&mixer_in1_ep>;
  1210. };
  1211. };
  1212. xbar_mixer_in2_port: port@33 {
  1213. reg = <0x33>;
  1214. xbar_mixer_in2_ep: endpoint {
  1215. remote-endpoint = <&mixer_in2_ep>;
  1216. };
  1217. };
  1218. xbar_mixer_in3_port: port@34 {
  1219. reg = <0x34>;
  1220. xbar_mixer_in3_ep: endpoint {
  1221. remote-endpoint = <&mixer_in3_ep>;
  1222. };
  1223. };
  1224. xbar_mixer_in4_port: port@35 {
  1225. reg = <0x35>;
  1226. xbar_mixer_in4_ep: endpoint {
  1227. remote-endpoint = <&mixer_in4_ep>;
  1228. };
  1229. };
  1230. xbar_mixer_in5_port: port@36 {
  1231. reg = <0x36>;
  1232. xbar_mixer_in5_ep: endpoint {
  1233. remote-endpoint = <&mixer_in5_ep>;
  1234. };
  1235. };
  1236. xbar_mixer_in6_port: port@37 {
  1237. reg = <0x37>;
  1238. xbar_mixer_in6_ep: endpoint {
  1239. remote-endpoint = <&mixer_in6_ep>;
  1240. };
  1241. };
  1242. xbar_mixer_in7_port: port@38 {
  1243. reg = <0x38>;
  1244. xbar_mixer_in7_ep: endpoint {
  1245. remote-endpoint = <&mixer_in7_ep>;
  1246. };
  1247. };
  1248. xbar_mixer_in8_port: port@39 {
  1249. reg = <0x39>;
  1250. xbar_mixer_in8_ep: endpoint {
  1251. remote-endpoint = <&mixer_in8_ep>;
  1252. };
  1253. };
  1254. xbar_mixer_in9_port: port@3a {
  1255. reg = <0x3a>;
  1256. xbar_mixer_in9_ep: endpoint {
  1257. remote-endpoint = <&mixer_in9_ep>;
  1258. };
  1259. };
  1260. xbar_mixer_in10_port: port@3b {
  1261. reg = <0x3b>;
  1262. xbar_mixer_in10_ep: endpoint {
  1263. remote-endpoint = <&mixer_in10_ep>;
  1264. };
  1265. };
  1266. port@3c {
  1267. reg = <0x3c>;
  1268. xbar_mixer_out1_ep: endpoint {
  1269. remote-endpoint = <&mixer_out1_ep>;
  1270. };
  1271. };
  1272. port@3d {
  1273. reg = <0x3d>;
  1274. xbar_mixer_out2_ep: endpoint {
  1275. remote-endpoint = <&mixer_out2_ep>;
  1276. };
  1277. };
  1278. port@3e {
  1279. reg = <0x3e>;
  1280. xbar_mixer_out3_ep: endpoint {
  1281. remote-endpoint = <&mixer_out3_ep>;
  1282. };
  1283. };
  1284. port@3f {
  1285. reg = <0x3f>;
  1286. xbar_mixer_out4_ep: endpoint {
  1287. remote-endpoint = <&mixer_out4_ep>;
  1288. };
  1289. };
  1290. port@40 {
  1291. reg = <0x40>;
  1292. xbar_mixer_out5_ep: endpoint {
  1293. remote-endpoint = <&mixer_out5_ep>;
  1294. };
  1295. };
  1296. xbar_ope1_in_port: port@41 {
  1297. reg = <0x41>;
  1298. xbar_ope1_in_ep: endpoint {
  1299. remote-endpoint = <&ope1_cif_in_ep>;
  1300. };
  1301. };
  1302. port@42 {
  1303. reg = <0x42>;
  1304. xbar_ope1_out_ep: endpoint {
  1305. remote-endpoint = <&ope1_cif_out_ep>;
  1306. };
  1307. };
  1308. xbar_ope2_in_port: port@43 {
  1309. reg = <0x43>;
  1310. xbar_ope2_in_ep: endpoint {
  1311. remote-endpoint = <&ope2_cif_in_ep>;
  1312. };
  1313. };
  1314. port@44 {
  1315. reg = <0x44>;
  1316. xbar_ope2_out_ep: endpoint {
  1317. remote-endpoint = <&ope2_cif_out_ep>;
  1318. };
  1319. };
  1320. };
  1321. };
  1322. };
  1323. spi@70410000 {
  1324. status = "okay";
  1325. flash@0 {
  1326. compatible = "jedec,spi-nor";
  1327. reg = <0>;
  1328. spi-max-frequency = <104000000>;
  1329. spi-tx-bus-width = <2>;
  1330. spi-rx-bus-width = <2>;
  1331. };
  1332. };
  1333. clk32k_in: clock-32k {
  1334. compatible = "fixed-clock";
  1335. clock-frequency = <32768>;
  1336. #clock-cells = <0>;
  1337. };
  1338. cpus {
  1339. cpu@0 {
  1340. enable-method = "psci";
  1341. };
  1342. cpu@1 {
  1343. enable-method = "psci";
  1344. };
  1345. cpu@2 {
  1346. enable-method = "psci";
  1347. };
  1348. cpu@3 {
  1349. enable-method = "psci";
  1350. };
  1351. idle-states {
  1352. cpu-sleep {
  1353. status = "okay";
  1354. };
  1355. };
  1356. };
  1357. fan: pwm-fan {
  1358. compatible = "pwm-fan";
  1359. pwms = <&pwm 3 45334>;
  1360. cooling-levels = <0 64 128 255>;
  1361. #cooling-cells = <2>;
  1362. };
  1363. thermal-zones {
  1364. cpu-thermal {
  1365. trips {
  1366. cpu_trip_critical: critical {
  1367. temperature = <96500>;
  1368. hysteresis = <0>;
  1369. type = "critical";
  1370. };
  1371. cpu_trip_hot: hot {
  1372. temperature = <70000>;
  1373. hysteresis = <2000>;
  1374. type = "hot";
  1375. };
  1376. cpu_trip_active: active {
  1377. temperature = <50000>;
  1378. hysteresis = <2000>;
  1379. type = "active";
  1380. };
  1381. cpu_trip_passive: passive {
  1382. temperature = <30000>;
  1383. hysteresis = <2000>;
  1384. type = "passive";
  1385. };
  1386. };
  1387. cooling-maps {
  1388. cpu-critical {
  1389. cooling-device = <&fan 3 3>;
  1390. trip = <&cpu_trip_critical>;
  1391. };
  1392. cpu-hot {
  1393. cooling-device = <&fan 2 2>;
  1394. trip = <&cpu_trip_hot>;
  1395. };
  1396. cpu-active {
  1397. cooling-device = <&fan 1 1>;
  1398. trip = <&cpu_trip_active>;
  1399. };
  1400. cpu-passive {
  1401. cooling-device = <&fan 0 0>;
  1402. trip = <&cpu_trip_passive>;
  1403. };
  1404. };
  1405. };
  1406. };
  1407. gpio-keys {
  1408. compatible = "gpio-keys";
  1409. key-power {
  1410. label = "Power";
  1411. gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
  1412. linux,input-type = <EV_KEY>;
  1413. linux,code = <KEY_POWER>;
  1414. debounce-interval = <30>;
  1415. wakeup-event-action = <EV_ACT_ASSERTED>;
  1416. wakeup-source;
  1417. };
  1418. key-force-recovery {
  1419. label = "Force Recovery";
  1420. gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
  1421. linux,input-type = <EV_KEY>;
  1422. linux,code = <BTN_1>;
  1423. debounce-interval = <30>;
  1424. };
  1425. };
  1426. psci {
  1427. compatible = "arm,psci-1.0";
  1428. method = "smc";
  1429. };
  1430. vdd_5v0_sys: regulator-vdd-5v0-sys {
  1431. compatible = "regulator-fixed";
  1432. regulator-name = "VDD_5V0_SYS";
  1433. regulator-min-microvolt = <5000000>;
  1434. regulator-max-microvolt = <5000000>;
  1435. regulator-always-on;
  1436. regulator-boot-on;
  1437. };
  1438. vdd_3v3_sys: regulator-vdd-3v3-sys {
  1439. compatible = "regulator-fixed";
  1440. regulator-name = "VDD_3V3_SYS";
  1441. regulator-min-microvolt = <3300000>;
  1442. regulator-max-microvolt = <3300000>;
  1443. regulator-enable-ramp-delay = <240>;
  1444. regulator-always-on;
  1445. regulator-boot-on;
  1446. gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
  1447. enable-active-high;
  1448. vin-supply = <&vdd_5v0_sys>;
  1449. };
  1450. vdd_3v3_sd: regulator-vdd-3v3-sd {
  1451. compatible = "regulator-fixed";
  1452. regulator-name = "VDD_3V3_SD";
  1453. regulator-min-microvolt = <3300000>;
  1454. regulator-max-microvolt = <3300000>;
  1455. gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
  1456. enable-active-high;
  1457. vin-supply = <&vdd_3v3_sys>;
  1458. };
  1459. vdd_hdmi: regulator-vdd-hdmi-5v0 {
  1460. compatible = "regulator-fixed";
  1461. regulator-name = "VDD_HDMI_5V0";
  1462. regulator-min-microvolt = <5000000>;
  1463. regulator-max-microvolt = <5000000>;
  1464. vin-supply = <&vdd_5v0_sys>;
  1465. };
  1466. vdd_hub_3v3: regulator-vdd-hub-3v3 {
  1467. compatible = "regulator-fixed";
  1468. regulator-name = "VDD_HUB_3V3";
  1469. regulator-min-microvolt = <3300000>;
  1470. regulator-max-microvolt = <3300000>;
  1471. gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
  1472. enable-active-high;
  1473. vin-supply = <&vdd_5v0_sys>;
  1474. };
  1475. vdd_cpu: regulator-vdd-cpu {
  1476. compatible = "regulator-fixed";
  1477. regulator-name = "VDD_CPU";
  1478. regulator-min-microvolt = <5000000>;
  1479. regulator-max-microvolt = <5000000>;
  1480. regulator-always-on;
  1481. regulator-boot-on;
  1482. gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
  1483. enable-active-high;
  1484. vin-supply = <&vdd_5v0_sys>;
  1485. };
  1486. vdd_gpu: regulator-vdd-gpu {
  1487. compatible = "pwm-regulator";
  1488. pwms = <&pwm 1 8000>;
  1489. regulator-name = "VDD_GPU";
  1490. regulator-min-microvolt = <710000>;
  1491. regulator-max-microvolt = <1320000>;
  1492. regulator-ramp-delay = <80>;
  1493. regulator-enable-ramp-delay = <2000>;
  1494. regulator-settling-time-us = <160>;
  1495. enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
  1496. vin-supply = <&vdd_5v0_sys>;
  1497. };
  1498. avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 {
  1499. compatible = "regulator-fixed";
  1500. regulator-name = "AVDD_IO_EDP_1V05";
  1501. regulator-min-microvolt = <1050000>;
  1502. regulator-max-microvolt = <1050000>;
  1503. gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
  1504. enable-active-high;
  1505. vin-supply = <&avdd_1v05_pll>;
  1506. };
  1507. vdd_5v0_usb: regulator-vdd-5v-usb {
  1508. compatible = "regulator-fixed";
  1509. regulator-name = "VDD_5V_USB";
  1510. regulator-min-microvolt = <50000000>;
  1511. regulator-max-microvolt = <50000000>;
  1512. vin-supply = <&vdd_5v0_sys>;
  1513. };
  1514. sound {
  1515. compatible = "nvidia,tegra210-audio-graph-card";
  1516. status = "okay";
  1517. dais = /* FE */
  1518. <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
  1519. <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
  1520. <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
  1521. <&admaif10_port>,
  1522. /* Router */
  1523. <&xbar_i2s3_port>, <&xbar_i2s4_port>,
  1524. <&xbar_dmic1_port>, <&xbar_dmic2_port>,
  1525. <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
  1526. <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
  1527. <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
  1528. <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
  1529. <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
  1530. <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
  1531. <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
  1532. <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
  1533. <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
  1534. <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
  1535. <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
  1536. <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
  1537. <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
  1538. <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
  1539. /* HW accelerators */
  1540. <&sfc1_out_port>, <&sfc2_out_port>,
  1541. <&sfc3_out_port>, <&sfc4_out_port>,
  1542. <&mvc1_out_port>, <&mvc2_out_port>,
  1543. <&amx1_out_port>, <&amx2_out_port>,
  1544. <&adx1_out1_port>, <&adx1_out2_port>,
  1545. <&adx1_out3_port>, <&adx1_out4_port>,
  1546. <&adx2_out1_port>, <&adx2_out2_port>,
  1547. <&adx2_out3_port>, <&adx2_out4_port>,
  1548. <&mixer_out1_port>, <&mixer_out2_port>,
  1549. <&mixer_out3_port>, <&mixer_out4_port>,
  1550. <&mixer_out5_port>,
  1551. <&ope1_out_port>, <&ope2_out_port>,
  1552. /* I/O DAP Ports */
  1553. <&i2s3_port>, <&i2s4_port>,
  1554. <&dmic1_port>, <&dmic2_port>;
  1555. label = "NVIDIA Jetson Nano APE";
  1556. };
  1557. };