tegra210-p2894.dtsi 54 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/input/gpio-keys.h>
  4. #include <dt-bindings/mfd/max77620.h>
  5. #include <dt-bindings/pinctrl/pinctrl-tegra.h>
  6. #include "tegra210.dtsi"
  7. / {
  8. aliases {
  9. serial0 = &uarta;
  10. };
  11. chosen {
  12. bootargs = "earlycon";
  13. stdout-path = "serial0:115200n8";
  14. };
  15. memory@80000000 {
  16. device_type = "memory";
  17. reg = <0x0 0x80000000 0x0 0xc0000000>;
  18. };
  19. pinmux: pinmux@700008d4 {
  20. status = "okay";
  21. pinctrl-names = "boot";
  22. pinctrl-0 = <&state_boot>;
  23. state_boot: pinmux {
  24. pex_l0_rst_n_pa0 {
  25. nvidia,pins = "pex_l0_rst_n_pa0";
  26. nvidia,function = "rsvd1";
  27. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  28. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  29. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  30. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  31. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  32. };
  33. pex_l0_clkreq_n_pa1 {
  34. nvidia,pins = "pex_l0_clkreq_n_pa1";
  35. nvidia,function = "pe0";
  36. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  37. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  38. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  39. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  40. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  41. };
  42. pex_wake_n_pa2 {
  43. nvidia,pins = "pex_wake_n_pa2";
  44. nvidia,function = "pe";
  45. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  46. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  47. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  48. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  49. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  50. };
  51. pex_l1_rst_n_pa3 {
  52. nvidia,pins = "pex_l1_rst_n_pa3";
  53. nvidia,function = "pe1";
  54. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  55. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  56. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  57. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  58. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  59. };
  60. pex_l1_clkreq_n_pa4 {
  61. nvidia,pins = "pex_l1_clkreq_n_pa4";
  62. nvidia,function = "pe1";
  63. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  64. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  65. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  66. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  67. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  68. };
  69. sata_led_active_pa5 {
  70. nvidia,pins = "sata_led_active_pa5";
  71. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  72. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  73. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  74. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  75. };
  76. pa6 {
  77. nvidia,pins = "pa6";
  78. nvidia,function = "rsvd1";
  79. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  80. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  81. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  82. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  83. };
  84. dap1_fs_pb0 {
  85. nvidia,pins = "dap1_fs_pb0";
  86. nvidia,function = "rsvd1";
  87. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  88. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  89. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  90. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  91. };
  92. dap1_din_pb1 {
  93. nvidia,pins = "dap1_din_pb1";
  94. nvidia,function = "rsvd1";
  95. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  96. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  97. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  98. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  99. };
  100. dap1_dout_pb2 {
  101. nvidia,pins = "dap1_dout_pb2";
  102. nvidia,function = "rsvd1";
  103. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  104. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  105. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  106. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  107. };
  108. dap1_sclk_pb3 {
  109. nvidia,pins = "dap1_sclk_pb3";
  110. nvidia,function = "rsvd1";
  111. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  112. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  113. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  114. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  115. };
  116. spi2_mosi_pb4 {
  117. nvidia,pins = "spi2_mosi_pb4";
  118. nvidia,function = "rsvd2";
  119. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  120. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  121. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  122. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  123. };
  124. spi2_miso_pb5 {
  125. nvidia,pins = "spi2_miso_pb5";
  126. nvidia,function = "rsvd2";
  127. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  128. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  129. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  130. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  131. };
  132. spi2_sck_pb6 {
  133. nvidia,pins = "spi2_sck_pb6";
  134. nvidia,function = "rsvd2";
  135. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  136. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  137. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  138. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  139. };
  140. spi2_cs0_pb7 {
  141. nvidia,pins = "spi2_cs0_pb7";
  142. nvidia,function = "rsvd2";
  143. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  144. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  145. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  146. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  147. };
  148. spi1_mosi_pc0 {
  149. nvidia,pins = "spi1_mosi_pc0";
  150. nvidia,function = "rsvd1";
  151. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  152. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  153. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  154. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  155. };
  156. spi1_miso_pc1 {
  157. nvidia,pins = "spi1_miso_pc1";
  158. nvidia,function = "rsvd1";
  159. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  160. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  161. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  162. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  163. };
  164. spi1_sck_pc2 {
  165. nvidia,pins = "spi1_sck_pc2";
  166. nvidia,function = "rsvd1";
  167. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  168. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  169. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  170. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  171. };
  172. spi1_cs0_pc3 {
  173. nvidia,pins = "spi1_cs0_pc3";
  174. nvidia,function = "rsvd1";
  175. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  176. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  177. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  178. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  179. };
  180. spi1_cs1_pc4 {
  181. nvidia,pins = "spi1_cs1_pc4";
  182. nvidia,function = "rsvd1";
  183. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  184. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  185. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  186. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  187. };
  188. spi4_sck_pc5 {
  189. nvidia,pins = "spi4_sck_pc5";
  190. nvidia,function = "rsvd1";
  191. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  192. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  193. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  194. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  195. };
  196. spi4_cs0_pc6 {
  197. nvidia,pins = "spi4_cs0_pc6";
  198. nvidia,function = "rsvd1";
  199. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  200. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  201. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  202. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  203. };
  204. spi4_mosi_pc7 {
  205. nvidia,pins = "spi4_mosi_pc7";
  206. nvidia,function = "rsvd1";
  207. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  208. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  209. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  210. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  211. };
  212. spi4_miso_pd0 {
  213. nvidia,pins = "spi4_miso_pd0";
  214. nvidia,function = "rsvd1";
  215. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  216. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  217. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  218. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  219. };
  220. uart3_tx_pd1 {
  221. nvidia,pins = "uart3_tx_pd1";
  222. nvidia,function = "rsvd2";
  223. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  224. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  225. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  226. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  227. };
  228. uart3_rx_pd2 {
  229. nvidia,pins = "uart3_rx_pd2";
  230. nvidia,function = "rsvd2";
  231. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  232. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  233. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  234. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  235. };
  236. uart3_rts_pd3 {
  237. nvidia,pins = "uart3_rts_pd3";
  238. nvidia,function = "rsvd2";
  239. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  240. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  241. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  242. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  243. };
  244. uart3_cts_pd4 {
  245. nvidia,pins = "uart3_cts_pd4";
  246. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  247. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  248. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  249. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  250. };
  251. dmic1_clk_pe0 {
  252. nvidia,pins = "dmic1_clk_pe0";
  253. nvidia,function = "rsvd2";
  254. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  255. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  256. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  257. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  258. };
  259. dmic1_dat_pe1 {
  260. nvidia,pins = "dmic1_dat_pe1";
  261. nvidia,function = "rsvd2";
  262. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  263. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  264. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  265. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  266. };
  267. dmic2_clk_pe2 {
  268. nvidia,pins = "dmic2_clk_pe2";
  269. nvidia,function = "rsvd2";
  270. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  271. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  272. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  273. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  274. };
  275. dmic2_dat_pe3 {
  276. nvidia,pins = "dmic2_dat_pe3";
  277. nvidia,function = "rsvd2";
  278. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  279. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  280. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  281. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  282. };
  283. dmic3_clk_pe4 {
  284. nvidia,pins = "dmic3_clk_pe4";
  285. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  286. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  287. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  288. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  289. };
  290. dmic3_dat_pe5 {
  291. nvidia,pins = "dmic3_dat_pe5";
  292. nvidia,function = "rsvd2";
  293. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  294. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  295. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  296. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  297. };
  298. pe6 {
  299. nvidia,pins = "pe6";
  300. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  301. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  302. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  303. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  304. };
  305. pe7 {
  306. nvidia,pins = "pe7";
  307. nvidia,function = "pwm3";
  308. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  309. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  310. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  311. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  312. };
  313. gen3_i2c_scl_pf0 {
  314. nvidia,pins = "gen3_i2c_scl_pf0";
  315. nvidia,function = "i2c3";
  316. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  317. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  318. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  319. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  320. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  321. };
  322. gen3_i2c_sda_pf1 {
  323. nvidia,pins = "gen3_i2c_sda_pf1";
  324. nvidia,function = "i2c3";
  325. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  326. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  327. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  328. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  329. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  330. };
  331. uart2_tx_pg0 {
  332. nvidia,pins = "uart2_tx_pg0";
  333. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  334. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  335. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  336. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  337. };
  338. uart2_rx_pg1 {
  339. nvidia,pins = "uart2_rx_pg1";
  340. nvidia,function = "uartb";
  341. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  342. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  343. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  344. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  345. };
  346. uart2_rts_pg2 {
  347. nvidia,pins = "uart2_rts_pg2";
  348. nvidia,function = "rsvd2";
  349. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  350. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  351. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  352. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  353. };
  354. uart2_cts_pg3 {
  355. nvidia,pins = "uart2_cts_pg3";
  356. nvidia,function = "rsvd2";
  357. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  358. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  359. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  360. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  361. };
  362. wifi_en_ph0 {
  363. nvidia,pins = "wifi_en_ph0";
  364. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  365. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  366. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  367. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  368. };
  369. wifi_rst_ph1 {
  370. nvidia,pins = "wifi_rst_ph1";
  371. nvidia,function = "rsvd0";
  372. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  373. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  374. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  375. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  376. };
  377. wifi_wake_ap_ph2 {
  378. nvidia,pins = "wifi_wake_ap_ph2";
  379. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  380. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  381. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  382. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  383. };
  384. ap_wake_bt_ph3 {
  385. nvidia,pins = "ap_wake_bt_ph3";
  386. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  387. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  388. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  389. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  390. };
  391. bt_rst_ph4 {
  392. nvidia,pins = "bt_rst_ph4";
  393. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  394. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  395. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  396. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  397. };
  398. bt_wake_ap_ph5 {
  399. nvidia,pins = "bt_wake_ap_ph5";
  400. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  401. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  402. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  403. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  404. };
  405. ph6 {
  406. nvidia,pins = "ph6";
  407. nvidia,function = "rsvd0";
  408. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  409. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  410. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  411. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  412. };
  413. ap_wake_nfc_ph7 {
  414. nvidia,pins = "ap_wake_nfc_ph7";
  415. nvidia,function = "rsvd0";
  416. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  417. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  418. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  419. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  420. };
  421. nfc_en_pi0 {
  422. nvidia,pins = "nfc_en_pi0";
  423. nvidia,function = "rsvd0";
  424. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  425. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  426. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  427. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  428. };
  429. nfc_int_pi1 {
  430. nvidia,pins = "nfc_int_pi1";
  431. nvidia,function = "rsvd0";
  432. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  433. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  434. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  435. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  436. };
  437. gps_en_pi2 {
  438. nvidia,pins = "gps_en_pi2";
  439. nvidia,function = "rsvd0";
  440. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  441. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  442. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  443. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  444. };
  445. gps_rst_pi3 {
  446. nvidia,pins = "gps_rst_pi3";
  447. nvidia,function = "rsvd0";
  448. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  449. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  450. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  451. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  452. };
  453. uart4_tx_pi4 {
  454. nvidia,pins = "uart4_tx_pi4";
  455. nvidia,function = "uartd";
  456. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  457. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  458. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  459. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  460. };
  461. uart4_rx_pi5 {
  462. nvidia,pins = "uart4_rx_pi5";
  463. nvidia,function = "uartd";
  464. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  465. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  466. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  467. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  468. };
  469. uart4_rts_pi6 {
  470. nvidia,pins = "uart4_rts_pi6";
  471. nvidia,function = "uartd";
  472. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  473. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  474. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  475. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  476. };
  477. uart4_cts_pi7 {
  478. nvidia,pins = "uart4_cts_pi7";
  479. nvidia,function = "uartd";
  480. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  481. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  482. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  483. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  484. };
  485. gen1_i2c_sda_pj0 {
  486. nvidia,pins = "gen1_i2c_sda_pj0";
  487. nvidia,function = "i2c1";
  488. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  489. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  490. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  491. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  492. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  493. };
  494. gen1_i2c_scl_pj1 {
  495. nvidia,pins = "gen1_i2c_scl_pj1";
  496. nvidia,function = "i2c1";
  497. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  498. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  499. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  500. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  501. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  502. };
  503. gen2_i2c_scl_pj2 {
  504. nvidia,pins = "gen2_i2c_scl_pj2";
  505. nvidia,function = "i2c2";
  506. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  507. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  508. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  509. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  510. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  511. };
  512. gen2_i2c_sda_pj3 {
  513. nvidia,pins = "gen2_i2c_sda_pj3";
  514. nvidia,function = "i2c2";
  515. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  516. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  517. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  518. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  519. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  520. };
  521. dap4_fs_pj4 {
  522. nvidia,pins = "dap4_fs_pj4";
  523. nvidia,function = "rsvd1";
  524. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  525. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  526. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  527. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  528. };
  529. dap4_din_pj5 {
  530. nvidia,pins = "dap4_din_pj5";
  531. nvidia,function = "rsvd1";
  532. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  533. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  534. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  535. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  536. };
  537. dap4_dout_pj6 {
  538. nvidia,pins = "dap4_dout_pj6";
  539. nvidia,function = "rsvd1";
  540. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  541. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  542. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  543. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  544. };
  545. dap4_sclk_pj7 {
  546. nvidia,pins = "dap4_sclk_pj7";
  547. nvidia,function = "rsvd1";
  548. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  549. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  550. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  551. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  552. };
  553. pk0 {
  554. nvidia,pins = "pk0";
  555. nvidia,function = "rsvd2";
  556. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  557. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  558. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  559. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  560. };
  561. pk1 {
  562. nvidia,pins = "pk1";
  563. nvidia,function = "rsvd2";
  564. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  565. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  566. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  567. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  568. };
  569. pk2 {
  570. nvidia,pins = "pk2";
  571. nvidia,function = "rsvd2";
  572. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  573. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  574. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  575. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  576. };
  577. pk3 {
  578. nvidia,pins = "pk3";
  579. nvidia,function = "rsvd2";
  580. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  581. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  582. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  583. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  584. };
  585. pk4 {
  586. nvidia,pins = "pk4";
  587. nvidia,function = "rsvd1";
  588. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  589. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  590. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  591. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  592. };
  593. pk5 {
  594. nvidia,pins = "pk5";
  595. nvidia,function = "rsvd1";
  596. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  597. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  598. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  599. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  600. };
  601. pk6 {
  602. nvidia,pins = "pk6";
  603. nvidia,function = "rsvd1";
  604. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  605. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  606. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  607. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  608. };
  609. pk7 {
  610. nvidia,pins = "pk7";
  611. nvidia,function = "rsvd1";
  612. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  613. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  614. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  615. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  616. };
  617. pl0 {
  618. nvidia,pins = "pl0";
  619. nvidia,function = "rsvd0";
  620. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  621. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  622. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  623. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  624. };
  625. pl1 {
  626. nvidia,pins = "pl1";
  627. nvidia,function = "rsvd1";
  628. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  629. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  630. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  631. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  632. };
  633. sdmmc1_clk_pm0 {
  634. nvidia,pins = "sdmmc1_clk_pm0";
  635. nvidia,function = "rsvd1";
  636. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  637. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  638. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  639. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  640. };
  641. sdmmc1_cmd_pm1 {
  642. nvidia,pins = "sdmmc1_cmd_pm1";
  643. nvidia,function = "rsvd2";
  644. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  645. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  646. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  647. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  648. };
  649. sdmmc1_dat3_pm2 {
  650. nvidia,pins = "sdmmc1_dat3_pm2";
  651. nvidia,function = "rsvd2";
  652. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  653. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  654. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  655. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  656. };
  657. sdmmc1_dat2_pm3 {
  658. nvidia,pins = "sdmmc1_dat2_pm3";
  659. nvidia,function = "rsvd2";
  660. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  661. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  662. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  663. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  664. };
  665. sdmmc1_dat1_pm4 {
  666. nvidia,pins = "sdmmc1_dat1_pm4";
  667. nvidia,function = "rsvd2";
  668. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  669. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  670. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  671. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  672. };
  673. sdmmc1_dat0_pm5 {
  674. nvidia,pins = "sdmmc1_dat0_pm5";
  675. nvidia,function = "rsvd1";
  676. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  677. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  678. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  679. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  680. };
  681. sdmmc3_clk_pp0 {
  682. nvidia,pins = "sdmmc3_clk_pp0";
  683. nvidia,function = "rsvd1";
  684. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  685. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  686. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  687. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  688. };
  689. sdmmc3_cmd_pp1 {
  690. nvidia,pins = "sdmmc3_cmd_pp1";
  691. nvidia,function = "rsvd1";
  692. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  693. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  694. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  695. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  696. };
  697. sdmmc3_dat3_pp2 {
  698. nvidia,pins = "sdmmc3_dat3_pp2";
  699. nvidia,function = "rsvd1";
  700. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  701. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  702. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  703. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  704. };
  705. sdmmc3_dat2_pp3 {
  706. nvidia,pins = "sdmmc3_dat2_pp3";
  707. nvidia,function = "rsvd1";
  708. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  709. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  710. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  711. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  712. };
  713. sdmmc3_dat1_pp4 {
  714. nvidia,pins = "sdmmc3_dat1_pp4";
  715. nvidia,function = "rsvd1";
  716. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  717. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  718. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  719. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  720. };
  721. sdmmc3_dat0_pp5 {
  722. nvidia,pins = "sdmmc3_dat0_pp5";
  723. nvidia,function = "rsvd1";
  724. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  725. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  726. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  727. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  728. };
  729. cam1_mclk_ps0 {
  730. nvidia,pins = "cam1_mclk_ps0";
  731. nvidia,function = "rsvd1";
  732. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  733. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  734. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  735. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  736. };
  737. cam2_mclk_ps1 {
  738. nvidia,pins = "cam2_mclk_ps1";
  739. nvidia,function = "rsvd1";
  740. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  741. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  742. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  743. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  744. };
  745. cam_i2c_scl_ps2 {
  746. nvidia,pins = "cam_i2c_scl_ps2";
  747. nvidia,function = "rsvd2";
  748. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  749. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  750. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  751. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  752. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  753. };
  754. cam_i2c_sda_ps3 {
  755. nvidia,pins = "cam_i2c_sda_ps3";
  756. nvidia,function = "rsvd2";
  757. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  758. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  759. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  760. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  761. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  762. };
  763. cam_rst_ps4 {
  764. nvidia,pins = "cam_rst_ps4";
  765. nvidia,function = "rsvd1";
  766. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  767. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  768. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  769. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  770. };
  771. cam_af_en_ps5 {
  772. nvidia,pins = "cam_af_en_ps5";
  773. nvidia,function = "rsvd2";
  774. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  775. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  776. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  777. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  778. };
  779. cam_flash_en_ps6 {
  780. nvidia,pins = "cam_flash_en_ps6";
  781. nvidia,function = "rsvd2";
  782. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  783. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  784. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  785. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  786. };
  787. cam1_pwdn_ps7 {
  788. nvidia,pins = "cam1_pwdn_ps7";
  789. nvidia,function = "rsvd1";
  790. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  791. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  792. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  793. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  794. };
  795. cam2_pwdn_pt0 {
  796. nvidia,pins = "cam2_pwdn_pt0";
  797. nvidia,function = "rsvd1";
  798. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  799. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  800. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  801. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  802. };
  803. cam1_strobe_pt1 {
  804. nvidia,pins = "cam1_strobe_pt1";
  805. nvidia,function = "rsvd1";
  806. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  807. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  808. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  809. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  810. };
  811. uart1_tx_pu0 {
  812. nvidia,pins = "uart1_tx_pu0";
  813. nvidia,function = "uarta";
  814. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  815. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  816. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  817. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  818. };
  819. uart1_rx_pu1 {
  820. nvidia,pins = "uart1_rx_pu1";
  821. nvidia,function = "uarta";
  822. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  823. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  824. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  825. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  826. };
  827. uart1_rts_pu2 {
  828. nvidia,pins = "uart1_rts_pu2";
  829. nvidia,function = "uarta";
  830. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  831. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  832. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  833. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  834. };
  835. uart1_cts_pu3 {
  836. nvidia,pins = "uart1_cts_pu3";
  837. nvidia,function = "uarta";
  838. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  839. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  840. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  841. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  842. };
  843. lcd_bl_pwm_pv0 {
  844. nvidia,pins = "lcd_bl_pwm_pv0";
  845. nvidia,function = "pwm0";
  846. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  847. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  848. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  849. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  850. };
  851. lcd_bl_en_pv1 {
  852. nvidia,pins = "lcd_bl_en_pv1";
  853. nvidia,function = "rsvd0";
  854. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  855. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  856. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  857. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  858. };
  859. lcd_rst_pv2 {
  860. nvidia,pins = "lcd_rst_pv2";
  861. nvidia,function = "rsvd0";
  862. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  863. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  864. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  865. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  866. };
  867. lcd_gpio1_pv3 {
  868. nvidia,pins = "lcd_gpio1_pv3";
  869. nvidia,function = "rsvd1";
  870. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  871. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  872. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  873. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  874. };
  875. lcd_gpio2_pv4 {
  876. nvidia,pins = "lcd_gpio2_pv4";
  877. nvidia,function = "pwm1";
  878. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  879. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  880. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  881. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  882. };
  883. ap_ready_pv5 {
  884. nvidia,pins = "ap_ready_pv5";
  885. nvidia,function = "rsvd0";
  886. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  887. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  888. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  889. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  890. };
  891. touch_rst_pv6 {
  892. nvidia,pins = "touch_rst_pv6";
  893. nvidia,function = "rsvd0";
  894. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  895. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  896. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  897. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  898. };
  899. touch_clk_pv7 {
  900. nvidia,pins = "touch_clk_pv7";
  901. nvidia,function = "rsvd1";
  902. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  903. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  904. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  905. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  906. };
  907. modem_wake_ap_px0 {
  908. nvidia,pins = "modem_wake_ap_px0";
  909. nvidia,function = "rsvd0";
  910. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  911. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  912. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  913. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  914. };
  915. touch_int_px1 {
  916. nvidia,pins = "touch_int_px1";
  917. nvidia,function = "rsvd0";
  918. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  919. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  920. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  921. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  922. };
  923. motion_int_px2 {
  924. nvidia,pins = "motion_int_px2";
  925. nvidia,function = "rsvd0";
  926. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  927. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  928. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  929. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  930. };
  931. als_prox_int_px3 {
  932. nvidia,pins = "als_prox_int_px3";
  933. nvidia,function = "rsvd0";
  934. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  935. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  936. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  937. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  938. };
  939. temp_alert_px4 {
  940. nvidia,pins = "temp_alert_px4";
  941. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  942. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  943. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  944. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  945. };
  946. button_power_on_px5 {
  947. nvidia,pins = "button_power_on_px5";
  948. nvidia,function = "rsvd0";
  949. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  950. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  951. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  952. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  953. };
  954. button_vol_up_px6 {
  955. nvidia,pins = "button_vol_up_px6";
  956. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  957. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  958. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  959. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  960. };
  961. button_vol_down_px7 {
  962. nvidia,pins = "button_vol_down_px7";
  963. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  964. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  965. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  966. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  967. };
  968. button_slide_sw_py0 {
  969. nvidia,pins = "button_slide_sw_py0";
  970. nvidia,function = "rsvd0";
  971. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  972. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  973. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  974. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  975. };
  976. button_home_py1 {
  977. nvidia,pins = "button_home_py1";
  978. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  979. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  980. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  981. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  982. };
  983. lcd_te_py2 {
  984. nvidia,pins = "lcd_te_py2";
  985. nvidia,function = "rsvd1";
  986. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  987. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  988. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  989. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  990. };
  991. pwr_i2c_scl_py3 {
  992. nvidia,pins = "pwr_i2c_scl_py3";
  993. nvidia,function = "i2cpmu";
  994. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  995. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  996. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  997. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  998. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  999. };
  1000. pwr_i2c_sda_py4 {
  1001. nvidia,pins = "pwr_i2c_sda_py4";
  1002. nvidia,function = "i2cpmu";
  1003. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1004. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1005. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1006. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1007. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1008. };
  1009. clk_32k_out_py5 {
  1010. nvidia,pins = "clk_32k_out_py5";
  1011. nvidia,function = "rsvd2";
  1012. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1013. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1014. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1015. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1016. };
  1017. pz0 {
  1018. nvidia,pins = "pz0";
  1019. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1020. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1021. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1022. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1023. };
  1024. pz1 {
  1025. nvidia,pins = "pz1";
  1026. nvidia,function = "rsvd2";
  1027. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1028. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1029. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1030. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1031. };
  1032. pz2 {
  1033. nvidia,pins = "pz2";
  1034. nvidia,function = "rsvd2";
  1035. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1036. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1037. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1038. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1039. };
  1040. pz3 {
  1041. nvidia,pins = "pz3";
  1042. nvidia,function = "rsvd1";
  1043. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1044. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1045. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1046. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1047. };
  1048. pz4 {
  1049. nvidia,pins = "pz4";
  1050. nvidia,function = "rsvd1";
  1051. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1052. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1053. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1054. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1055. };
  1056. pz5 {
  1057. nvidia,pins = "pz5";
  1058. nvidia,function = "soc";
  1059. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1060. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1061. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1062. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1063. };
  1064. dap2_fs_paa0 {
  1065. nvidia,pins = "dap2_fs_paa0";
  1066. nvidia,function = "i2s2";
  1067. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1068. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1069. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1070. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1071. };
  1072. dap2_sclk_paa1 {
  1073. nvidia,pins = "dap2_sclk_paa1";
  1074. nvidia,function = "i2s2";
  1075. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1076. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1077. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1078. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1079. };
  1080. dap2_din_paa2 {
  1081. nvidia,pins = "dap2_din_paa2";
  1082. nvidia,function = "i2s2";
  1083. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1084. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1085. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1086. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1087. };
  1088. dap2_dout_paa3 {
  1089. nvidia,pins = "dap2_dout_paa3";
  1090. nvidia,function = "i2s2";
  1091. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1092. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1093. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1094. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1095. };
  1096. aud_mclk_pbb0 {
  1097. nvidia,pins = "aud_mclk_pbb0";
  1098. nvidia,function = "rsvd1";
  1099. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1100. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1101. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1102. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1103. };
  1104. dvfs_pwm_pbb1 {
  1105. nvidia,pins = "dvfs_pwm_pbb1";
  1106. nvidia,function = "cldvfs";
  1107. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1108. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1109. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1110. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1111. };
  1112. dvfs_clk_pbb2 {
  1113. nvidia,pins = "dvfs_clk_pbb2";
  1114. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1115. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1116. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1117. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1118. };
  1119. gpio_x1_aud_pbb3 {
  1120. nvidia,pins = "gpio_x1_aud_pbb3";
  1121. nvidia,function = "rsvd0";
  1122. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1123. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1124. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1125. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1126. };
  1127. gpio_x3_aud_pbb4 {
  1128. nvidia,pins = "gpio_x3_aud_pbb4";
  1129. nvidia,function = "rsvd0";
  1130. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1131. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1132. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1133. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1134. };
  1135. hdmi_cec_pcc0 {
  1136. nvidia,pins = "hdmi_cec_pcc0";
  1137. nvidia,function = "cec";
  1138. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1139. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1140. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1141. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1142. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1143. };
  1144. hdmi_int_dp_hpd_pcc1 {
  1145. nvidia,pins = "hdmi_int_dp_hpd_pcc1";
  1146. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1147. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1148. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1149. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1150. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1151. };
  1152. spdif_out_pcc2 {
  1153. nvidia,pins = "spdif_out_pcc2";
  1154. nvidia,function = "rsvd1";
  1155. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1156. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1157. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1158. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1159. };
  1160. spdif_in_pcc3 {
  1161. nvidia,pins = "spdif_in_pcc3";
  1162. nvidia,function = "rsvd1";
  1163. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1164. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1165. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1166. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1167. };
  1168. usb_vbus_en0_pcc4 {
  1169. nvidia,pins = "usb_vbus_en0_pcc4";
  1170. nvidia,function = "usb";
  1171. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1172. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1173. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1174. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1175. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1176. };
  1177. usb_vbus_en1_pcc5 {
  1178. nvidia,pins = "usb_vbus_en1_pcc5";
  1179. nvidia,function = "usb";
  1180. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1181. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1182. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1183. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1184. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1185. };
  1186. dp_hpd0_pcc6 {
  1187. nvidia,pins = "dp_hpd0_pcc6";
  1188. nvidia,function = "rsvd1";
  1189. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1190. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1191. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1192. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1193. };
  1194. pcc7 {
  1195. nvidia,pins = "pcc7";
  1196. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1197. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1198. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1199. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1200. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1201. };
  1202. spi2_cs1_pdd0 {
  1203. nvidia,pins = "spi2_cs1_pdd0";
  1204. nvidia,function = "rsvd1";
  1205. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1206. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1207. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1208. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1209. };
  1210. qspi_sck_pee0 {
  1211. nvidia,pins = "qspi_sck_pee0";
  1212. nvidia,function = "rsvd1";
  1213. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1214. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1215. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1216. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1217. };
  1218. qspi_cs_n_pee1 {
  1219. nvidia,pins = "qspi_cs_n_pee1";
  1220. nvidia,function = "rsvd1";
  1221. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1222. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1223. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1224. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1225. };
  1226. qspi_io0_pee2 {
  1227. nvidia,pins = "qspi_io0_pee2";
  1228. nvidia,function = "rsvd1";
  1229. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1230. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1231. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1232. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1233. };
  1234. qspi_io1_pee3 {
  1235. nvidia,pins = "qspi_io1_pee3";
  1236. nvidia,function = "rsvd1";
  1237. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1238. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1239. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1240. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1241. };
  1242. qspi_io2_pee4 {
  1243. nvidia,pins = "qspi_io2_pee4";
  1244. nvidia,function = "rsvd1";
  1245. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1246. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1247. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1248. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1249. };
  1250. qspi_io3_pee5 {
  1251. nvidia,pins = "qspi_io3_pee5";
  1252. nvidia,function = "rsvd1";
  1253. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1254. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1255. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1256. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1257. };
  1258. core_pwr_req {
  1259. nvidia,pins = "core_pwr_req";
  1260. nvidia,function = "core";
  1261. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1262. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1263. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1264. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1265. };
  1266. cpu_pwr_req {
  1267. nvidia,pins = "cpu_pwr_req";
  1268. nvidia,function = "rsvd1";
  1269. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1270. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1271. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1272. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1273. };
  1274. pwr_int_n {
  1275. nvidia,pins = "pwr_int_n";
  1276. nvidia,function = "pmi";
  1277. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1278. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1279. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1280. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1281. };
  1282. clk_32k_in {
  1283. nvidia,pins = "clk_32k_in";
  1284. nvidia,function = "clk";
  1285. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1286. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1287. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1288. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1289. };
  1290. jtag_rtck {
  1291. nvidia,pins = "jtag_rtck";
  1292. nvidia,function = "jtag";
  1293. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1294. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1295. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1296. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1297. };
  1298. clk_req {
  1299. nvidia,pins = "clk_req";
  1300. nvidia,function = "rsvd1";
  1301. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1302. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1303. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1304. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1305. };
  1306. shutdown {
  1307. nvidia,pins = "shutdown";
  1308. nvidia,function = "shutdown";
  1309. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1310. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1311. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1312. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1313. };
  1314. };
  1315. };
  1316. serial@70006000 {
  1317. status = "okay";
  1318. };
  1319. i2c@7000d000 {
  1320. status = "okay";
  1321. clock-frequency = <400000>;
  1322. pmic: pmic@3c {
  1323. compatible = "maxim,max77620";
  1324. reg = <0x3c>;
  1325. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  1326. #interrupt-cells = <2>;
  1327. interrupt-controller;
  1328. gpio-controller;
  1329. #gpio-cells = <2>;
  1330. pinctrl-names = "default";
  1331. pinctrl-0 = <&max77620_default>;
  1332. max77620_default: pinmux@0 {
  1333. gpio0 {
  1334. pins = "gpio0";
  1335. function = "gpio";
  1336. };
  1337. gpio1 {
  1338. pins = "gpio1";
  1339. function = "fps-out";
  1340. drive-push-pull = <1>;
  1341. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1342. maxim,active-fps-power-up-slot = <7>;
  1343. maxim,active-fps-power-down-slot = <0>;
  1344. };
  1345. gpio2 {
  1346. pins = "gpio2";
  1347. function = "fps-out";
  1348. drive-open-drain = <1>;
  1349. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1350. };
  1351. gpio3 {
  1352. pins = "gpio3";
  1353. function = "fps-out";
  1354. drive-open-drain = <1>;
  1355. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1356. };
  1357. gpio4 {
  1358. pins = "gpio4";
  1359. function = "32k-out1";
  1360. };
  1361. gpio5_6_7 {
  1362. pins = "gpio5", "gpio6", "gpio7";
  1363. function = "gpio";
  1364. drive-push-pull = <1>;
  1365. };
  1366. };
  1367. hog-0 {
  1368. gpio-hog;
  1369. output-high;
  1370. gpios = <2 GPIO_ACTIVE_HIGH>,
  1371. <7 GPIO_ACTIVE_HIGH>;
  1372. };
  1373. fps {
  1374. #address-cells = <1>;
  1375. #size-cells = <0>;
  1376. fps0 {
  1377. reg = <0>;
  1378. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
  1379. };
  1380. fps1 {
  1381. reg = <1>;
  1382. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
  1383. maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
  1384. };
  1385. fps2 {
  1386. reg = <2>;
  1387. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
  1388. };
  1389. };
  1390. regulators {
  1391. in-ldo0-1-supply = <&max77620_sd2>;
  1392. in-ldo7-8-supply = <&max77620_sd2>;
  1393. max77620_sd0: sd0 {
  1394. regulator-name = "vdd-core";
  1395. regulator-enable-ramp-delay = <146>;
  1396. regulator-min-microvolt = <600000>;
  1397. regulator-max-microvolt = <1400000>;
  1398. regulator-ramp-delay = <27500>;
  1399. regulator-always-on;
  1400. regulator-boot-on;
  1401. maxim,active-fps-power-up-slot = <0>;
  1402. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  1403. };
  1404. max77620_sd1: sd1 {
  1405. regulator-name = "vddio-ddr";
  1406. regulator-enable-ramp-delay = <130>;
  1407. regulator-ramp-delay = <27500>;
  1408. regulator-always-on;
  1409. regulator-boot-on;
  1410. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1411. };
  1412. max77620_sd2: sd2 {
  1413. regulator-name = "vdd-pre-reg";
  1414. regulator-enable-ramp-delay = <176>;
  1415. regulator-min-microvolt = <3000000>;
  1416. regulator-max-microvolt = <3000000>;
  1417. regulator-ramp-delay = <27500>;
  1418. regulator-always-on;
  1419. regulator-boot-on;
  1420. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  1421. maxim,suspend-fps-source = <MAX77620_FPS_SRC_NONE>;
  1422. };
  1423. max77620_sd3: sd3 {
  1424. regulator-name = "vdd-1v8";
  1425. regulator-enable-ramp-delay = <242>;
  1426. regulator-min-microvolt = <1800000>;
  1427. regulator-max-microvolt = <1800000>;
  1428. regulator-ramp-delay = <27500>;
  1429. regulator-always-on;
  1430. regulator-boot-on;
  1431. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1432. };
  1433. max77620_ldo0: ldo0 {
  1434. regulator-name = "avdd-sys";
  1435. regulator-enable-ramp-delay = <26>;
  1436. regulator-min-microvolt = <1200000>;
  1437. regulator-max-microvolt = <1200000>;
  1438. regulator-ramp-delay = <100000>;
  1439. regulator-boot-on;
  1440. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1441. };
  1442. max77620_ldo1: ldo1 {
  1443. regulator-name = "vdd-pex";
  1444. regulator-enable-ramp-delay = <22>;
  1445. regulator-min-microvolt = <1075000>;
  1446. regulator-max-microvolt = <1075000>;
  1447. regulator-ramp-delay = <100000>;
  1448. regulator-always-on;
  1449. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1450. };
  1451. max77620_ldo2: ldo2 {
  1452. regulator-name = "vddio-sdmmc3";
  1453. regulator-enable-ramp-delay = <62>;
  1454. regulator-min-microvolt = <1800000>;
  1455. regulator-max-microvolt = <3300000>;
  1456. regulator-ramp-delay = <100000>;
  1457. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1458. };
  1459. max77620_ldo3: ldo3 {
  1460. regulator-name = "vdd-3v3-eth";
  1461. regulator-enable-ramp-delay = <50>;
  1462. regulator-min-microvolt = <3300000>;
  1463. regulator-max-microvolt = <3300000>;
  1464. regulator-ramp-delay = <100000>;
  1465. regulator-always-on;
  1466. regulator-boot-on;
  1467. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1468. };
  1469. max77620_ldo4: ldo4 {
  1470. regulator-name = "vdd-rtc";
  1471. regulator-enable-ramp-delay = <22>;
  1472. regulator-min-microvolt = <850000>;
  1473. regulator-max-microvolt = <850000>;
  1474. regulator-ramp-delay = <100000>;
  1475. regulator-always-on;
  1476. regulator-boot-on;
  1477. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1478. };
  1479. max77620_ldo5: ldo5 {
  1480. regulator-name = "avdd-ts-hv";
  1481. regulator-enable-ramp-delay = <62>;
  1482. regulator-min-microvolt = <3300000>;
  1483. regulator-max-microvolt = <3300000>;
  1484. regulator-ramp-delay = <100000>;
  1485. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1486. };
  1487. max77620_ldo6: ldo6 {
  1488. regulator-name = "vdd-ts";
  1489. regulator-enable-ramp-delay = <36>;
  1490. regulator-min-microvolt = <1800000>;
  1491. regulator-max-microvolt = <1800000>;
  1492. regulator-ramp-delay = <100000>;
  1493. regulator-boot-on;
  1494. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1495. };
  1496. max77620_ldo7: ldo7 {
  1497. regulator-name = "vdd-gen-pll-edp";
  1498. regulator-enable-ramp-delay = <24>;
  1499. regulator-min-microvolt = <1050000>;
  1500. regulator-max-microvolt = <1050000>;
  1501. regulator-ramp-delay = <100000>;
  1502. regulator-always-on;
  1503. regulator-boot-on;
  1504. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  1505. maxim,suspend-fps-source = <MAX77620_FPS_SRC_NONE>;
  1506. };
  1507. max77620_ldo8: ldo8 {
  1508. regulator-name = "vdd-hdmi-dp";
  1509. regulator-enable-ramp-delay = <22>;
  1510. regulator-min-microvolt = <1050000>;
  1511. regulator-max-microvolt = <1050000>;
  1512. regulator-ramp-delay = <100000>;
  1513. regulator-always-on;
  1514. regulator-boot-on;
  1515. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  1516. };
  1517. };
  1518. };
  1519. };
  1520. pmc@7000e400 {
  1521. nvidia,invert-interrupt;
  1522. nvidia,suspend-mode = <0>;
  1523. nvidia,cpu-pwr-good-time = <0>;
  1524. nvidia,cpu-pwr-off-time = <0>;
  1525. nvidia,core-pwr-good-time = <4587 3876>;
  1526. nvidia,core-pwr-off-time = <39065>;
  1527. nvidia,core-power-req-active-high;
  1528. nvidia,sys-clock-req-active-high;
  1529. status = "okay";
  1530. };
  1531. mmc@700b0600 {
  1532. bus-width = <8>;
  1533. non-removable;
  1534. status = "okay";
  1535. };
  1536. clk32k_in: clock-32k {
  1537. compatible = "fixed-clock";
  1538. clock-frequency = <32768>;
  1539. #clock-cells = <0>;
  1540. };
  1541. gpio-keys {
  1542. compatible = "gpio-keys";
  1543. status = "okay";
  1544. key-power {
  1545. debounce-interval = <30>;
  1546. gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
  1547. label = "Power";
  1548. linux,code = <KEY_POWER>;
  1549. wakeup-event-action = <EV_ACT_ASSERTED>;
  1550. wakeup-source;
  1551. };
  1552. };
  1553. cpus {
  1554. cpu@0 {
  1555. enable-method = "psci";
  1556. };
  1557. cpu@1 {
  1558. enable-method = "psci";
  1559. };
  1560. cpu@2 {
  1561. enable-method = "psci";
  1562. };
  1563. cpu@3 {
  1564. enable-method = "psci";
  1565. };
  1566. idle-states {
  1567. cpu-sleep {
  1568. status = "okay";
  1569. };
  1570. };
  1571. };
  1572. psci {
  1573. compatible = "arm,psci-1.0";
  1574. method = "smc";
  1575. };
  1576. battery_reg: regulator-vdd-ac-bat {
  1577. compatible = "regulator-fixed";
  1578. regulator-name = "vdd-ac-bat";
  1579. regulator-min-microvolt = <5000000>;
  1580. regulator-max-microvolt = <5000000>;
  1581. regulator-always-on;
  1582. };
  1583. vdd_3v3: regulator-vdd-3v3 {
  1584. compatible = "regulator-fixed";
  1585. regulator-name = "vdd-3v3";
  1586. regulator-enable-ramp-delay = <160>;
  1587. regulator-min-microvolt = <3300000>;
  1588. regulator-max-microvolt = <3300000>;
  1589. regulator-always-on;
  1590. gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
  1591. enable-active-high;
  1592. };
  1593. max77620_gpio7: regulator-max77620-gpio7 {
  1594. compatible = "regulator-fixed";
  1595. regulator-name = "max77620-gpio7";
  1596. regulator-enable-ramp-delay = <240>;
  1597. regulator-min-microvolt = <1200000>;
  1598. regulator-max-microvolt = <1200000>;
  1599. vin-supply = <&max77620_ldo0>;
  1600. regulator-always-on;
  1601. regulator-boot-on;
  1602. gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
  1603. enable-active-high;
  1604. };
  1605. lcd_bl_en: regulator-lcd-bl-en {
  1606. compatible = "regulator-fixed";
  1607. regulator-name = "lcd-bl-en";
  1608. regulator-min-microvolt = <1800000>;
  1609. regulator-max-microvolt = <1800000>;
  1610. regulator-boot-on;
  1611. gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
  1612. enable-active-high;
  1613. };
  1614. en_vdd_sd: regulator-vdd-sd {
  1615. compatible = "regulator-fixed";
  1616. regulator-name = "en-vdd-sd";
  1617. regulator-enable-ramp-delay = <472>;
  1618. regulator-min-microvolt = <3300000>;
  1619. regulator-max-microvolt = <3300000>;
  1620. vin-supply = <&vdd_3v3>;
  1621. gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
  1622. enable-active-high;
  1623. };
  1624. en_vdd_cam: regulator-vdd-cam {
  1625. compatible = "regulator-fixed";
  1626. regulator-name = "en-vdd-cam";
  1627. regulator-min-microvolt = <1800000>;
  1628. regulator-max-microvolt = <1800000>;
  1629. gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
  1630. enable-active-high;
  1631. };
  1632. vdd_sys_boost: regulator-vdd-sys-boost {
  1633. compatible = "regulator-fixed";
  1634. regulator-name = "vdd-sys-boost";
  1635. regulator-enable-ramp-delay = <3090>;
  1636. regulator-min-microvolt = <5000000>;
  1637. regulator-max-microvolt = <5000000>;
  1638. regulator-always-on;
  1639. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  1640. enable-active-high;
  1641. };
  1642. vdd_hdmi: regulator-vdd-hdmi {
  1643. compatible = "regulator-fixed";
  1644. regulator-name = "vdd-hdmi";
  1645. regulator-enable-ramp-delay = <468>;
  1646. regulator-min-microvolt = <5000000>;
  1647. regulator-max-microvolt = <5000000>;
  1648. vin-supply = <&vdd_sys_boost>;
  1649. regulator-boot-on;
  1650. gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>;
  1651. enable-active-high;
  1652. };
  1653. en_vdd_cpu_fixed: regulator-vdd-cpu-fixed {
  1654. compatible = "regulator-fixed";
  1655. regulator-name = "vdd-cpu-fixed";
  1656. regulator-min-microvolt = <1000000>;
  1657. regulator-max-microvolt = <1000000>;
  1658. };
  1659. vdd_aux_3v3: regulator-vdd-aux-3v3 {
  1660. compatible = "regulator-fixed";
  1661. regulator-name = "aux-3v3";
  1662. regulator-min-microvolt = <3300000>;
  1663. regulator-max-microvolt = <3300000>;
  1664. };
  1665. vdd_snsr_pm: regulator-vdd-snsr-pm {
  1666. compatible = "regulator-fixed";
  1667. regulator-name = "snsr_pm";
  1668. regulator-min-microvolt = <3300000>;
  1669. regulator-max-microvolt = <3300000>;
  1670. enable-active-high;
  1671. };
  1672. vdd_usb_5v0: regulator-vdd-usb-5v0 {
  1673. compatible = "regulator-fixed";
  1674. status = "disabled";
  1675. regulator-name = "vdd-usb-5v0";
  1676. regulator-min-microvolt = <5000000>;
  1677. regulator-max-microvolt = <5000000>;
  1678. vin-supply = <&vdd_3v3>;
  1679. enable-active-high;
  1680. };
  1681. vdd_cdc_1v2_aud: regulator-vdd-cdc-1v2-aud {
  1682. compatible = "regulator-fixed";
  1683. status = "disabled";
  1684. regulator-name = "vdd_cdc_1v2_aud";
  1685. regulator-min-microvolt = <1200000>;
  1686. regulator-max-microvolt = <1200000>;
  1687. startup-delay-us = <250000>;
  1688. enable-active-high;
  1689. };
  1690. vdd_disp_3v0: regulator-vdd-disp-3v0 {
  1691. compatible = "regulator-fixed";
  1692. regulator-name = "vdd-disp-3v0";
  1693. regulator-enable-ramp-delay = <232>;
  1694. regulator-min-microvolt = <3000000>;
  1695. regulator-max-microvolt = <3000000>;
  1696. regulator-always-on;
  1697. gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
  1698. enable-active-high;
  1699. };
  1700. vdd_fan: regulator-vdd-fan {
  1701. compatible = "regulator-fixed";
  1702. regulator-name = "vdd-fan";
  1703. regulator-enable-ramp-delay = <284>;
  1704. regulator-min-microvolt = <5000000>;
  1705. regulator-max-microvolt = <5000000>;
  1706. gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>;
  1707. enable-active-high;
  1708. };
  1709. usb_vbus1: regulator-usb-vbus1 {
  1710. compatible = "regulator-fixed";
  1711. regulator-name = "usb-vbus1";
  1712. regulator-min-microvolt = <5000000>;
  1713. regulator-max-microvolt = <5000000>;
  1714. gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
  1715. enable-active-high;
  1716. gpio-open-drain;
  1717. };
  1718. usb_vbus2: regulator-usb-vbus2 {
  1719. compatible = "regulator-fixed";
  1720. regulator-name = "usb-vbus2";
  1721. regulator-min-microvolt = <5000000>;
  1722. regulator-max-microvolt = <5000000>;
  1723. gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
  1724. enable-active-high;
  1725. gpio-open-drain;
  1726. };
  1727. vdd_3v3_eth: regulator-vdd-3v3-eth {
  1728. compatible = "regulator-fixed";
  1729. regulator-name = "vdd-3v3-eth-a02";
  1730. regulator-min-microvolt = <3300000>;
  1731. regulator-max-microvolt = <3300000>;
  1732. regulator-always-on;
  1733. regulator-boot-on;
  1734. gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
  1735. enable-active-high;
  1736. gpio-open-drain;
  1737. };
  1738. };