tegra210-p2597.dtsi 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/input/input.h>
  3. / {
  4. model = "NVIDIA Tegra210 P2597 I/O board";
  5. compatible = "nvidia,p2597", "nvidia,tegra210";
  6. aliases {
  7. ethernet = "/usb@70090000/ethernet@1";
  8. };
  9. host1x@50000000 {
  10. dpaux@54040000 {
  11. status = "okay";
  12. };
  13. vi@54080000 {
  14. status = "okay";
  15. avdd-dsi-csi-supply = <&vdd_dsi_csi>;
  16. csi@838 {
  17. status = "okay";
  18. };
  19. };
  20. sor@54580000 {
  21. status = "okay";
  22. avdd-io-hdmi-dp-supply = <&avdd_1v05>;
  23. vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
  24. hdmi-supply = <&vdd_hdmi>;
  25. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  26. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
  27. GPIO_ACTIVE_LOW>;
  28. };
  29. };
  30. pinmux: pinmux@700008d4 {
  31. pinctrl-names = "boot";
  32. pinctrl-0 = <&state_boot>;
  33. state_boot: pinmux {
  34. pex_l0_rst_n_pa0 {
  35. nvidia,pins = "pex_l0_rst_n_pa0";
  36. nvidia,function = "pe0";
  37. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  38. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  39. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  40. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  41. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  42. };
  43. pex_l0_clkreq_n_pa1 {
  44. nvidia,pins = "pex_l0_clkreq_n_pa1";
  45. nvidia,function = "pe0";
  46. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  47. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  48. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  49. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  50. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  51. };
  52. pex_wake_n_pa2 {
  53. nvidia,pins = "pex_wake_n_pa2";
  54. nvidia,function = "pe";
  55. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  56. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  57. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  58. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  59. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  60. };
  61. pex_l1_rst_n_pa3 {
  62. nvidia,pins = "pex_l1_rst_n_pa3";
  63. nvidia,function = "pe1";
  64. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  65. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  66. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  67. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  68. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  69. };
  70. pex_l1_clkreq_n_pa4 {
  71. nvidia,pins = "pex_l1_clkreq_n_pa4";
  72. nvidia,function = "pe1";
  73. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  74. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  75. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  76. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  77. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  78. };
  79. sata_led_active_pa5 {
  80. nvidia,pins = "sata_led_active_pa5";
  81. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  82. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  83. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  84. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  85. };
  86. pa6 {
  87. nvidia,pins = "pa6";
  88. nvidia,function = "sata";
  89. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  90. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  91. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  92. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  93. };
  94. dap1_fs_pb0 {
  95. nvidia,pins = "dap1_fs_pb0";
  96. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  97. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  98. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  99. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  100. };
  101. dap1_din_pb1 {
  102. nvidia,pins = "dap1_din_pb1";
  103. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  104. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  105. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  106. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  107. };
  108. dap1_dout_pb2 {
  109. nvidia,pins = "dap1_dout_pb2";
  110. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  111. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  112. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  113. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  114. };
  115. dap1_sclk_pb3 {
  116. nvidia,pins = "dap1_sclk_pb3";
  117. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  118. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  119. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  120. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  121. };
  122. spi2_mosi_pb4 {
  123. nvidia,pins = "spi2_mosi_pb4";
  124. nvidia,function = "spi2";
  125. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  126. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  127. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  128. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  129. };
  130. spi2_miso_pb5 {
  131. nvidia,pins = "spi2_miso_pb5";
  132. nvidia,function = "spi2";
  133. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  134. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  135. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  136. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  137. };
  138. spi2_sck_pb6 {
  139. nvidia,pins = "spi2_sck_pb6";
  140. nvidia,function = "spi2";
  141. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  142. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  143. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  144. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  145. };
  146. spi2_cs0_pb7 {
  147. nvidia,pins = "spi2_cs0_pb7";
  148. nvidia,function = "spi2";
  149. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  150. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  151. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  152. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  153. };
  154. spi1_mosi_pc0 {
  155. nvidia,pins = "spi1_mosi_pc0";
  156. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  157. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  158. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  159. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  160. };
  161. spi1_miso_pc1 {
  162. nvidia,pins = "spi1_miso_pc1";
  163. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  164. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  165. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  166. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  167. };
  168. spi1_sck_pc2 {
  169. nvidia,pins = "spi1_sck_pc2";
  170. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  171. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  172. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  173. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  174. };
  175. spi1_cs0_pc3 {
  176. nvidia,pins = "spi1_cs0_pc3";
  177. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  178. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  179. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  180. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  181. };
  182. spi1_cs1_pc4 {
  183. nvidia,pins = "spi1_cs1_pc4";
  184. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  185. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  186. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  187. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  188. };
  189. spi4_sck_pc5 {
  190. nvidia,pins = "spi4_sck_pc5";
  191. nvidia,function = "spi4";
  192. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  193. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  194. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  195. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  196. };
  197. spi4_cs0_pc6 {
  198. nvidia,pins = "spi4_cs0_pc6";
  199. nvidia,function = "spi4";
  200. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  201. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  202. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  203. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  204. };
  205. spi4_mosi_pc7 {
  206. nvidia,pins = "spi4_mosi_pc7";
  207. nvidia,function = "spi4";
  208. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  209. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  210. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  211. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  212. };
  213. spi4_miso_pd0 {
  214. nvidia,pins = "spi4_miso_pd0";
  215. nvidia,function = "spi4";
  216. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  217. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  218. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  219. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  220. };
  221. uart3_tx_pd1 {
  222. nvidia,pins = "uart3_tx_pd1";
  223. nvidia,function = "uartc";
  224. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  225. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  226. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  227. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  228. };
  229. uart3_rx_pd2 {
  230. nvidia,pins = "uart3_rx_pd2";
  231. nvidia,function = "uartc";
  232. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  233. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  234. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  235. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  236. };
  237. uart3_rts_pd3 {
  238. nvidia,pins = "uart3_rts_pd3";
  239. nvidia,function = "uartc";
  240. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  241. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  242. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  243. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  244. };
  245. uart3_cts_pd4 {
  246. nvidia,pins = "uart3_cts_pd4";
  247. nvidia,function = "uartc";
  248. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  249. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  250. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  251. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  252. };
  253. dmic1_clk_pe0 {
  254. nvidia,pins = "dmic1_clk_pe0";
  255. nvidia,function = "i2s3";
  256. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  257. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  258. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  259. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  260. };
  261. dmic1_dat_pe1 {
  262. nvidia,pins = "dmic1_dat_pe1";
  263. nvidia,function = "i2s3";
  264. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  265. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  266. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  267. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  268. };
  269. dmic2_clk_pe2 {
  270. nvidia,pins = "dmic2_clk_pe2";
  271. nvidia,function = "i2s3";
  272. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  273. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  274. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  275. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  276. };
  277. dmic2_dat_pe3 {
  278. nvidia,pins = "dmic2_dat_pe3";
  279. nvidia,function = "i2s3";
  280. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  281. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  282. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  283. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  284. };
  285. dmic3_clk_pe4 {
  286. nvidia,pins = "dmic3_clk_pe4";
  287. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  288. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  289. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  290. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  291. };
  292. dmic3_dat_pe5 {
  293. nvidia,pins = "dmic3_dat_pe5";
  294. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  295. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  296. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  297. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  298. };
  299. pe6 {
  300. nvidia,pins = "pe6";
  301. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  302. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  303. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  304. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  305. };
  306. pe7 {
  307. nvidia,pins = "pe7";
  308. nvidia,function = "pwm3";
  309. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  310. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  311. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  312. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  313. };
  314. gen3_i2c_scl_pf0 {
  315. nvidia,pins = "gen3_i2c_scl_pf0";
  316. nvidia,function = "i2c3";
  317. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  318. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  319. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  320. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  321. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  322. };
  323. gen3_i2c_sda_pf1 {
  324. nvidia,pins = "gen3_i2c_sda_pf1";
  325. nvidia,function = "i2c3";
  326. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  327. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  328. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  329. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  330. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  331. };
  332. uart2_tx_pg0 {
  333. nvidia,pins = "uart2_tx_pg0";
  334. nvidia,function = "uartb";
  335. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  336. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  337. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  338. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  339. };
  340. uart2_rx_pg1 {
  341. nvidia,pins = "uart2_rx_pg1";
  342. nvidia,function = "uartb";
  343. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  344. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  345. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  346. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  347. };
  348. uart2_rts_pg2 {
  349. nvidia,pins = "uart2_rts_pg2";
  350. nvidia,function = "uartb";
  351. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  352. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  353. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  354. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  355. };
  356. uart2_cts_pg3 {
  357. nvidia,pins = "uart2_cts_pg3";
  358. nvidia,function = "uartb";
  359. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  360. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  361. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  362. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  363. };
  364. wifi_en_ph0 {
  365. nvidia,pins = "wifi_en_ph0";
  366. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  367. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  368. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  369. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  370. };
  371. wifi_rst_ph1 {
  372. nvidia,pins = "wifi_rst_ph1";
  373. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  374. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  375. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  376. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  377. };
  378. wifi_wake_ap_ph2 {
  379. nvidia,pins = "wifi_wake_ap_ph2";
  380. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  381. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  382. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  383. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  384. };
  385. ap_wake_bt_ph3 {
  386. nvidia,pins = "ap_wake_bt_ph3";
  387. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  388. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  389. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  390. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  391. };
  392. bt_rst_ph4 {
  393. nvidia,pins = "bt_rst_ph4";
  394. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  395. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  396. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  397. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  398. };
  399. bt_wake_ap_ph5 {
  400. nvidia,pins = "bt_wake_ap_ph5";
  401. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  402. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  403. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  404. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  405. };
  406. ph6 {
  407. nvidia,pins = "ph6";
  408. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  409. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  410. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  411. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  412. };
  413. ap_wake_nfc_ph7 {
  414. nvidia,pins = "ap_wake_nfc_ph7";
  415. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  416. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  417. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  418. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  419. };
  420. nfc_en_pi0 {
  421. nvidia,pins = "nfc_en_pi0";
  422. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  423. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  424. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  425. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  426. };
  427. nfc_int_pi1 {
  428. nvidia,pins = "nfc_int_pi1";
  429. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  430. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  431. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  432. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  433. };
  434. gps_en_pi2 {
  435. nvidia,pins = "gps_en_pi2";
  436. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  437. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  438. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  439. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  440. };
  441. gps_rst_pi3 {
  442. nvidia,pins = "gps_rst_pi3";
  443. nvidia,function = "rsvd0";
  444. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  445. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  446. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  447. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  448. };
  449. uart4_tx_pi4 {
  450. nvidia,pins = "uart4_tx_pi4";
  451. nvidia,function = "uartd";
  452. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  453. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  454. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  455. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  456. };
  457. uart4_rx_pi5 {
  458. nvidia,pins = "uart4_rx_pi5";
  459. nvidia,function = "uartd";
  460. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  461. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  462. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  463. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  464. };
  465. uart4_rts_pi6 {
  466. nvidia,pins = "uart4_rts_pi6";
  467. nvidia,function = "uartd";
  468. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  469. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  470. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  471. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  472. };
  473. uart4_cts_pi7 {
  474. nvidia,pins = "uart4_cts_pi7";
  475. nvidia,function = "uartd";
  476. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  477. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  478. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  479. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  480. };
  481. gen1_i2c_sda_pj0 {
  482. nvidia,pins = "gen1_i2c_sda_pj0";
  483. nvidia,function = "i2c1";
  484. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  485. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  486. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  487. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  488. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  489. };
  490. gen1_i2c_scl_pj1 {
  491. nvidia,pins = "gen1_i2c_scl_pj1";
  492. nvidia,function = "i2c1";
  493. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  494. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  495. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  496. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  497. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  498. };
  499. gen2_i2c_scl_pj2 {
  500. nvidia,pins = "gen2_i2c_scl_pj2";
  501. nvidia,function = "i2c2";
  502. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  503. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  504. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  505. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  506. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  507. };
  508. gen2_i2c_sda_pj3 {
  509. nvidia,pins = "gen2_i2c_sda_pj3";
  510. nvidia,function = "i2c2";
  511. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  512. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  513. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  514. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  515. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  516. };
  517. dap4_fs_pj4 {
  518. nvidia,pins = "dap4_fs_pj4";
  519. nvidia,function = "i2s4b";
  520. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  521. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  522. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  523. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  524. };
  525. dap4_din_pj5 {
  526. nvidia,pins = "dap4_din_pj5";
  527. nvidia,function = "i2s4b";
  528. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  529. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  530. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  531. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  532. };
  533. dap4_dout_pj6 {
  534. nvidia,pins = "dap4_dout_pj6";
  535. nvidia,function = "i2s4b";
  536. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  537. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  538. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  539. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  540. };
  541. dap4_sclk_pj7 {
  542. nvidia,pins = "dap4_sclk_pj7";
  543. nvidia,function = "i2s4b";
  544. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  545. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  546. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  547. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  548. };
  549. pk0 {
  550. nvidia,pins = "pk0";
  551. nvidia,function = "i2s5b";
  552. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  553. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  554. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  555. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  556. };
  557. pk1 {
  558. nvidia,pins = "pk1";
  559. nvidia,function = "i2s5b";
  560. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  561. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  562. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  563. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  564. };
  565. pk2 {
  566. nvidia,pins = "pk2";
  567. nvidia,function = "i2s5b";
  568. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  569. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  570. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  571. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  572. };
  573. pk3 {
  574. nvidia,pins = "pk3";
  575. nvidia,function = "i2s5b";
  576. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  577. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  578. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  579. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  580. };
  581. pk4 {
  582. nvidia,pins = "pk4";
  583. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  584. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  585. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  586. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  587. };
  588. pk5 {
  589. nvidia,pins = "pk5";
  590. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  591. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  592. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  593. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  594. };
  595. pk6 {
  596. nvidia,pins = "pk6";
  597. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  598. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  599. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  600. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  601. };
  602. pk7 {
  603. nvidia,pins = "pk7";
  604. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  605. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  606. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  607. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  608. };
  609. pl0 {
  610. nvidia,pins = "pl0";
  611. nvidia,function = "rsvd0";
  612. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  613. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  614. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  615. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  616. };
  617. pl1 {
  618. nvidia,pins = "pl1";
  619. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  620. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  621. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  622. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  623. };
  624. sdmmc1_clk_pm0 {
  625. nvidia,pins = "sdmmc1_clk_pm0";
  626. nvidia,function = "sdmmc1";
  627. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  628. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  629. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  630. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  631. };
  632. sdmmc1_cmd_pm1 {
  633. nvidia,pins = "sdmmc1_cmd_pm1";
  634. nvidia,function = "sdmmc1";
  635. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  636. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  637. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  638. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  639. };
  640. sdmmc1_dat3_pm2 {
  641. nvidia,pins = "sdmmc1_dat3_pm2";
  642. nvidia,function = "sdmmc1";
  643. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  644. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  645. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  646. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  647. };
  648. sdmmc1_dat2_pm3 {
  649. nvidia,pins = "sdmmc1_dat2_pm3";
  650. nvidia,function = "sdmmc1";
  651. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  652. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  653. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  654. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  655. };
  656. sdmmc1_dat1_pm4 {
  657. nvidia,pins = "sdmmc1_dat1_pm4";
  658. nvidia,function = "sdmmc1";
  659. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  660. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  661. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  662. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  663. };
  664. sdmmc1_dat0_pm5 {
  665. nvidia,pins = "sdmmc1_dat0_pm5";
  666. nvidia,function = "sdmmc1";
  667. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  668. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  669. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  670. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  671. };
  672. sdmmc3_clk_pp0 {
  673. nvidia,pins = "sdmmc3_clk_pp0";
  674. nvidia,function = "sdmmc3";
  675. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  676. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  677. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  678. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  679. };
  680. sdmmc3_cmd_pp1 {
  681. nvidia,pins = "sdmmc3_cmd_pp1";
  682. nvidia,function = "sdmmc3";
  683. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  684. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  685. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  686. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  687. };
  688. sdmmc3_dat3_pp2 {
  689. nvidia,pins = "sdmmc3_dat3_pp2";
  690. nvidia,function = "sdmmc3";
  691. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  692. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  693. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  694. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  695. };
  696. sdmmc3_dat2_pp3 {
  697. nvidia,pins = "sdmmc3_dat2_pp3";
  698. nvidia,function = "sdmmc3";
  699. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  700. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  701. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  702. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  703. };
  704. sdmmc3_dat1_pp4 {
  705. nvidia,pins = "sdmmc3_dat1_pp4";
  706. nvidia,function = "sdmmc3";
  707. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  708. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  709. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  710. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  711. };
  712. sdmmc3_dat0_pp5 {
  713. nvidia,pins = "sdmmc3_dat0_pp5";
  714. nvidia,function = "sdmmc3";
  715. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  716. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  717. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  718. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  719. };
  720. cam1_mclk_ps0 {
  721. nvidia,pins = "cam1_mclk_ps0";
  722. nvidia,function = "extperiph3";
  723. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  724. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  725. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  726. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  727. };
  728. cam2_mclk_ps1 {
  729. nvidia,pins = "cam2_mclk_ps1";
  730. nvidia,function = "extperiph3";
  731. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  732. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  733. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  734. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  735. };
  736. cam_i2c_scl_ps2 {
  737. nvidia,pins = "cam_i2c_scl_ps2";
  738. nvidia,function = "i2cvi";
  739. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  740. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  741. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  742. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  743. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  744. };
  745. cam_i2c_sda_ps3 {
  746. nvidia,pins = "cam_i2c_sda_ps3";
  747. nvidia,function = "i2cvi";
  748. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  749. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  750. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  751. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  752. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  753. };
  754. cam_rst_ps4 {
  755. nvidia,pins = "cam_rst_ps4";
  756. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  757. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  758. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  759. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  760. };
  761. cam_af_en_ps5 {
  762. nvidia,pins = "cam_af_en_ps5";
  763. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  764. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  765. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  766. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  767. };
  768. cam_flash_en_ps6 {
  769. nvidia,pins = "cam_flash_en_ps6";
  770. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  771. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  772. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  773. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  774. };
  775. cam1_pwdn_ps7 {
  776. nvidia,pins = "cam1_pwdn_ps7";
  777. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  778. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  779. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  780. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  781. };
  782. cam2_pwdn_pt0 {
  783. nvidia,pins = "cam2_pwdn_pt0";
  784. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  785. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  786. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  787. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  788. };
  789. cam1_strobe_pt1 {
  790. nvidia,pins = "cam1_strobe_pt1";
  791. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  792. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  793. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  794. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  795. };
  796. uart1_tx_pu0 {
  797. nvidia,pins = "uart1_tx_pu0";
  798. nvidia,function = "uarta";
  799. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  800. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  801. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  802. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  803. };
  804. uart1_rx_pu1 {
  805. nvidia,pins = "uart1_rx_pu1";
  806. nvidia,function = "uarta";
  807. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  808. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  809. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  810. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  811. };
  812. uart1_rts_pu2 {
  813. nvidia,pins = "uart1_rts_pu2";
  814. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  815. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  816. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  817. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  818. };
  819. uart1_cts_pu3 {
  820. nvidia,pins = "uart1_cts_pu3";
  821. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  822. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  823. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  824. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  825. };
  826. lcd_bl_pwm_pv0 {
  827. nvidia,pins = "lcd_bl_pwm_pv0";
  828. nvidia,function = "pwm0";
  829. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  830. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  831. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  832. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  833. };
  834. lcd_bl_en_pv1 {
  835. nvidia,pins = "lcd_bl_en_pv1";
  836. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  837. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  838. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  839. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  840. };
  841. lcd_rst_pv2 {
  842. nvidia,pins = "lcd_rst_pv2";
  843. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  844. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  845. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  846. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  847. };
  848. lcd_gpio1_pv3 {
  849. nvidia,pins = "lcd_gpio1_pv3";
  850. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  851. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  852. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  853. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  854. };
  855. lcd_gpio2_pv4 {
  856. nvidia,pins = "lcd_gpio2_pv4";
  857. nvidia,function = "pwm1";
  858. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  859. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  860. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  861. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  862. };
  863. ap_ready_pv5 {
  864. nvidia,pins = "ap_ready_pv5";
  865. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  866. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  867. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  868. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  869. };
  870. touch_rst_pv6 {
  871. nvidia,pins = "touch_rst_pv6";
  872. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  873. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  874. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  875. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  876. };
  877. touch_clk_pv7 {
  878. nvidia,pins = "touch_clk_pv7";
  879. nvidia,function = "touch";
  880. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  881. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  882. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  883. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  884. };
  885. modem_wake_ap_px0 {
  886. nvidia,pins = "modem_wake_ap_px0";
  887. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  888. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  889. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  890. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  891. };
  892. touch_int_px1 {
  893. nvidia,pins = "touch_int_px1";
  894. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  895. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  896. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  897. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  898. };
  899. motion_int_px2 {
  900. nvidia,pins = "motion_int_px2";
  901. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  902. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  903. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  904. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  905. };
  906. als_prox_int_px3 {
  907. nvidia,pins = "als_prox_int_px3";
  908. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  909. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  910. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  911. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  912. };
  913. temp_alert_px4 {
  914. nvidia,pins = "temp_alert_px4";
  915. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  916. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  917. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  918. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  919. };
  920. button_power_on_px5 {
  921. nvidia,pins = "button_power_on_px5";
  922. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  923. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  924. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  925. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  926. };
  927. button_vol_up_px6 {
  928. nvidia,pins = "button_vol_up_px6";
  929. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  930. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  931. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  932. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  933. };
  934. button_vol_down_px7 {
  935. nvidia,pins = "button_vol_down_px7";
  936. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  937. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  938. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  939. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  940. };
  941. button_slide_sw_py0 {
  942. nvidia,pins = "button_slide_sw_py0";
  943. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  944. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  945. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  946. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  947. };
  948. button_home_py1 {
  949. nvidia,pins = "button_home_py1";
  950. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  951. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  952. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  953. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  954. };
  955. lcd_te_py2 {
  956. nvidia,pins = "lcd_te_py2";
  957. nvidia,function = "displaya";
  958. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  959. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  960. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  961. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  962. };
  963. pwr_i2c_scl_py3 {
  964. nvidia,pins = "pwr_i2c_scl_py3";
  965. nvidia,function = "i2cpmu";
  966. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  967. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  968. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  969. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  970. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  971. };
  972. pwr_i2c_sda_py4 {
  973. nvidia,pins = "pwr_i2c_sda_py4";
  974. nvidia,function = "i2cpmu";
  975. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  976. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  977. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  978. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  979. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  980. };
  981. clk_32k_out_py5 {
  982. nvidia,pins = "clk_32k_out_py5";
  983. nvidia,function = "soc";
  984. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  985. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  986. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  987. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  988. };
  989. pz0 {
  990. nvidia,pins = "pz0";
  991. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  992. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  993. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  994. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  995. };
  996. pz1 {
  997. nvidia,pins = "pz1";
  998. nvidia,function = "sdmmc1";
  999. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1000. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1001. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1002. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1003. };
  1004. pz2 {
  1005. nvidia,pins = "pz2";
  1006. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1007. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1008. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1009. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1010. };
  1011. pz3 {
  1012. nvidia,pins = "pz3";
  1013. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1014. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1015. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1016. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1017. };
  1018. pz4 {
  1019. nvidia,pins = "pz4";
  1020. nvidia,function = "sdmmc1";
  1021. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1022. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1023. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1024. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1025. };
  1026. pz5 {
  1027. nvidia,pins = "pz5";
  1028. nvidia,function = "soc";
  1029. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1030. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1031. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1032. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1033. };
  1034. dap2_fs_paa0 {
  1035. nvidia,pins = "dap2_fs_paa0";
  1036. nvidia,function = "i2s2";
  1037. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1038. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1039. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1040. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1041. };
  1042. dap2_sclk_paa1 {
  1043. nvidia,pins = "dap2_sclk_paa1";
  1044. nvidia,function = "i2s2";
  1045. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1046. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1047. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1048. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1049. };
  1050. dap2_din_paa2 {
  1051. nvidia,pins = "dap2_din_paa2";
  1052. nvidia,function = "i2s2";
  1053. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1054. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1055. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1056. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1057. };
  1058. dap2_dout_paa3 {
  1059. nvidia,pins = "dap2_dout_paa3";
  1060. nvidia,function = "i2s2";
  1061. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1062. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1063. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1064. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1065. };
  1066. aud_mclk_pbb0 {
  1067. nvidia,pins = "aud_mclk_pbb0";
  1068. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1069. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1070. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1071. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1072. };
  1073. dvfs_pwm_pbb1 {
  1074. nvidia,pins = "dvfs_pwm_pbb1";
  1075. nvidia,function = "cldvfs";
  1076. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1077. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1078. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1079. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1080. };
  1081. dvfs_clk_pbb2 {
  1082. nvidia,pins = "dvfs_clk_pbb2";
  1083. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1084. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1085. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1086. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1087. };
  1088. gpio_x1_aud_pbb3 {
  1089. nvidia,pins = "gpio_x1_aud_pbb3";
  1090. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1091. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1092. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1093. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1094. };
  1095. gpio_x3_aud_pbb4 {
  1096. nvidia,pins = "gpio_x3_aud_pbb4";
  1097. nvidia,function = "rsvd0";
  1098. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1099. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1100. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1101. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1102. };
  1103. hdmi_cec_pcc0 {
  1104. nvidia,pins = "hdmi_cec_pcc0";
  1105. nvidia,function = "cec";
  1106. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1107. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1108. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1109. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1110. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1111. };
  1112. hdmi_int_dp_hpd_pcc1 {
  1113. nvidia,pins = "hdmi_int_dp_hpd_pcc1";
  1114. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1115. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1116. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1117. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1118. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1119. };
  1120. spdif_out_pcc2 {
  1121. nvidia,pins = "spdif_out_pcc2";
  1122. nvidia,function = "rsvd1";
  1123. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1124. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1125. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1126. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1127. };
  1128. spdif_in_pcc3 {
  1129. nvidia,pins = "spdif_in_pcc3";
  1130. nvidia,function = "rsvd1";
  1131. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1132. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1133. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1134. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1135. };
  1136. usb_vbus_en0_pcc4 {
  1137. nvidia,pins = "usb_vbus_en0_pcc4";
  1138. nvidia,function = "usb";
  1139. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1140. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1141. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1142. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1143. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1144. };
  1145. usb_vbus_en1_pcc5 {
  1146. nvidia,pins = "usb_vbus_en1_pcc5";
  1147. nvidia,function = "usb";
  1148. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1149. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1150. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1151. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1152. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1153. };
  1154. dp_hpd0_pcc6 {
  1155. nvidia,pins = "dp_hpd0_pcc6";
  1156. nvidia,function = "dp";
  1157. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1158. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1159. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1160. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1161. };
  1162. pcc7 {
  1163. nvidia,pins = "pcc7";
  1164. nvidia,function = "rsvd0";
  1165. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1166. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1167. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1168. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1169. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1170. };
  1171. spi2_cs1_pdd0 {
  1172. nvidia,pins = "spi2_cs1_pdd0";
  1173. nvidia,function = "spi2";
  1174. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1175. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1176. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1177. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1178. };
  1179. qspi_sck_pee0 {
  1180. nvidia,pins = "qspi_sck_pee0";
  1181. nvidia,function = "rsvd1";
  1182. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1183. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1184. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1185. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1186. };
  1187. qspi_cs_n_pee1 {
  1188. nvidia,pins = "qspi_cs_n_pee1";
  1189. nvidia,function = "rsvd1";
  1190. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1191. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1192. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1193. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1194. };
  1195. qspi_io0_pee2 {
  1196. nvidia,pins = "qspi_io0_pee2";
  1197. nvidia,function = "rsvd1";
  1198. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1199. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1200. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1201. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1202. };
  1203. qspi_io1_pee3 {
  1204. nvidia,pins = "qspi_io1_pee3";
  1205. nvidia,function = "rsvd1";
  1206. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1207. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1208. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1209. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1210. };
  1211. qspi_io2_pee4 {
  1212. nvidia,pins = "qspi_io2_pee4";
  1213. nvidia,function = "rsvd1";
  1214. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1215. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1216. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1217. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1218. };
  1219. qspi_io3_pee5 {
  1220. nvidia,pins = "qspi_io3_pee5";
  1221. nvidia,function = "rsvd1";
  1222. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1223. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1224. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1225. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1226. };
  1227. core_pwr_req {
  1228. nvidia,pins = "core_pwr_req";
  1229. nvidia,function = "core";
  1230. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1231. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1232. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1233. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1234. };
  1235. cpu_pwr_req {
  1236. nvidia,pins = "cpu_pwr_req";
  1237. nvidia,function = "cpu";
  1238. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1239. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1240. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1241. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1242. };
  1243. pwr_int_n {
  1244. nvidia,pins = "pwr_int_n";
  1245. nvidia,function = "pmi";
  1246. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1247. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1248. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1249. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1250. };
  1251. clk_32k_in {
  1252. nvidia,pins = "clk_32k_in";
  1253. nvidia,function = "clk";
  1254. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1255. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1256. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1257. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1258. };
  1259. jtag_rtck {
  1260. nvidia,pins = "jtag_rtck";
  1261. nvidia,function = "jtag";
  1262. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1263. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1264. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1265. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1266. };
  1267. clk_req {
  1268. nvidia,pins = "clk_req";
  1269. nvidia,function = "rsvd1";
  1270. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1271. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1272. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1273. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1274. };
  1275. shutdown {
  1276. nvidia,pins = "shutdown";
  1277. nvidia,function = "shutdown";
  1278. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1279. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1280. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1281. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1282. };
  1283. };
  1284. dvfs_pwm_active_state: dvfs_pwm_active {
  1285. dvfs_pwm_pbb1 {
  1286. nvidia,pins = "dvfs_pwm_pbb1";
  1287. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1288. };
  1289. };
  1290. dvfs_pwm_inactive_state: dvfs_pwm_inactive {
  1291. dvfs_pwm_pbb1 {
  1292. nvidia,pins = "dvfs_pwm_pbb1";
  1293. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1294. };
  1295. };
  1296. };
  1297. pwm@7000a000 {
  1298. status = "okay";
  1299. };
  1300. i2c@7000c400 {
  1301. status = "okay";
  1302. clock-frequency = <100000>;
  1303. exp1: gpio@74 {
  1304. compatible = "ti,tca9539";
  1305. reg = <0x74>;
  1306. #gpio-cells = <2>;
  1307. gpio-controller;
  1308. };
  1309. exp2: gpio@77 {
  1310. compatible = "ti,tca9539";
  1311. reg = <0x77>;
  1312. #gpio-cells = <2>;
  1313. gpio-controller;
  1314. };
  1315. };
  1316. /* HDMI DDC */
  1317. hdmi_ddc: i2c@7000c700 {
  1318. status = "okay";
  1319. clock-frequency = <100000>;
  1320. };
  1321. sata@70020000 {
  1322. status = "okay";
  1323. phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
  1324. };
  1325. hda@70030000 {
  1326. nvidia,model = "NVIDIA Jetson TX1 HDA";
  1327. status = "okay";
  1328. };
  1329. usb@70090000 {
  1330. phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
  1331. <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
  1332. <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
  1333. <&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>,
  1334. <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>,
  1335. <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
  1336. phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0",
  1337. "usb3-1";
  1338. dvddio-pex-supply = <&vdd_pex_1v05>;
  1339. hvddio-pex-supply = <&vdd_1v8>;
  1340. avdd-usb-supply = <&vdd_3v3_sys>;
  1341. status = "okay";
  1342. #address-cells = <1>;
  1343. #size-cells = <0>;
  1344. ethernet@1 {
  1345. reg = <1>;
  1346. };
  1347. };
  1348. padctl@7009f000 {
  1349. status = "okay";
  1350. avdd-pll-utmip-supply = <&vdd_1v8>;
  1351. avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
  1352. dvdd-pex-pll-supply = <&vdd_pex_1v05>;
  1353. hvdd-pex-pll-e-supply = <&vdd_1v8>;
  1354. pads {
  1355. usb2 {
  1356. status = "okay";
  1357. lanes {
  1358. micro_b: usb2-0 {
  1359. nvidia,function = "xusb";
  1360. status = "okay";
  1361. };
  1362. usb2-1 {
  1363. nvidia,function = "xusb";
  1364. status = "okay";
  1365. };
  1366. usb2-2 {
  1367. nvidia,function = "xusb";
  1368. status = "okay";
  1369. };
  1370. usb2-3 {
  1371. nvidia,function = "xusb";
  1372. status = "okay";
  1373. };
  1374. };
  1375. };
  1376. pcie {
  1377. status = "okay";
  1378. lanes {
  1379. pcie-0 {
  1380. nvidia,function = "pcie-x1";
  1381. status = "okay";
  1382. };
  1383. pcie-1 {
  1384. nvidia,function = "pcie-x4";
  1385. status = "okay";
  1386. };
  1387. pcie-2 {
  1388. nvidia,function = "pcie-x4";
  1389. status = "okay";
  1390. };
  1391. pcie-3 {
  1392. nvidia,function = "pcie-x4";
  1393. status = "okay";
  1394. };
  1395. pcie-4 {
  1396. nvidia,function = "pcie-x4";
  1397. status = "okay";
  1398. };
  1399. pcie-5 {
  1400. nvidia,function = "usb3-ss";
  1401. status = "okay";
  1402. };
  1403. pcie-6 {
  1404. nvidia,function = "usb3-ss";
  1405. status = "okay";
  1406. };
  1407. };
  1408. };
  1409. sata {
  1410. status = "okay";
  1411. lanes {
  1412. sata-0 {
  1413. nvidia,function = "sata";
  1414. status = "okay";
  1415. };
  1416. };
  1417. };
  1418. };
  1419. ports {
  1420. usb2-0 {
  1421. status = "okay";
  1422. vbus-supply = <&vdd_usb_vbus_otg>;
  1423. usb-role-switch;
  1424. mode = "otg";
  1425. connector {
  1426. compatible = "gpio-usb-b-connector",
  1427. "usb-b-connector";
  1428. label = "micro-USB";
  1429. type = "micro";
  1430. vbus-gpios = <&gpio TEGRA_GPIO(Z, 0)
  1431. GPIO_ACTIVE_LOW>;
  1432. id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
  1433. };
  1434. };
  1435. usb2-1 {
  1436. status = "okay";
  1437. vbus-supply = <&vdd_5v0_rtl>;
  1438. mode = "host";
  1439. };
  1440. usb2-2 {
  1441. status = "okay";
  1442. vbus-supply = <&vdd_usb_vbus>;
  1443. mode = "host";
  1444. };
  1445. usb2-3 {
  1446. status = "okay";
  1447. mode = "host";
  1448. };
  1449. usb3-0 {
  1450. nvidia,usb2-companion = <1>;
  1451. status = "okay";
  1452. };
  1453. usb3-1 {
  1454. nvidia,usb2-companion = <2>;
  1455. status = "okay";
  1456. };
  1457. };
  1458. };
  1459. /* MMC/SD */
  1460. mmc@700b0000 {
  1461. status = "okay";
  1462. bus-width = <4>;
  1463. cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
  1464. vqmmc-supply = <&vddio_sdmmc>;
  1465. vmmc-supply = <&vdd_3v3_sd>;
  1466. };
  1467. usb@700d0000 {
  1468. status = "okay";
  1469. phys = <&micro_b>;
  1470. phy-names = "usb2-0";
  1471. avddio-usb-supply = <&vdd_3v3_sys>;
  1472. hvdd-usb-supply = <&vdd_1v8>;
  1473. };
  1474. gpio-keys {
  1475. compatible = "gpio-keys";
  1476. label = "gpio-keys";
  1477. key-power {
  1478. label = "Power";
  1479. gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
  1480. linux,code = <KEY_POWER>;
  1481. wakeup-source;
  1482. };
  1483. key-volume-down {
  1484. label = "Volume Down";
  1485. gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
  1486. linux,code = <KEY_VOLUMEDOWN>;
  1487. };
  1488. key-volume-up {
  1489. label = "Volume Up";
  1490. gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
  1491. linux,code = <KEY_VOLUMEUP>;
  1492. };
  1493. };
  1494. vdd_sys_mux: regulator-vdd-sys-mux {
  1495. compatible = "regulator-fixed";
  1496. regulator-name = "VDD_SYS_MUX";
  1497. regulator-min-microvolt = <5000000>;
  1498. regulator-max-microvolt = <5000000>;
  1499. regulator-always-on;
  1500. regulator-boot-on;
  1501. };
  1502. vdd_5v0_sys: regulator-vdd-5v0-sys {
  1503. compatible = "regulator-fixed";
  1504. regulator-name = "VDD_5V0_SYS";
  1505. regulator-min-microvolt = <5000000>;
  1506. regulator-max-microvolt = <5000000>;
  1507. regulator-always-on;
  1508. regulator-boot-on;
  1509. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  1510. enable-active-high;
  1511. vin-supply = <&vdd_sys_mux>;
  1512. };
  1513. vdd_3v3_sys: regulator-vdd-3v3-sys {
  1514. compatible = "regulator-fixed";
  1515. regulator-name = "VDD_3V3_SYS";
  1516. regulator-min-microvolt = <3300000>;
  1517. regulator-max-microvolt = <3300000>;
  1518. regulator-always-on;
  1519. regulator-boot-on;
  1520. gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
  1521. enable-active-high;
  1522. vin-supply = <&vdd_sys_mux>;
  1523. regulator-enable-ramp-delay = <160>;
  1524. };
  1525. vdd_5v0_io: regulator-vdd-5v0-io {
  1526. compatible = "regulator-fixed";
  1527. regulator-name = "VDD_5V0_IO_SYS";
  1528. regulator-min-microvolt = <5000000>;
  1529. regulator-max-microvolt = <5000000>;
  1530. regulator-always-on;
  1531. regulator-boot-on;
  1532. };
  1533. vdd_3v3_sd: regulator-vdd-3v3-sd {
  1534. compatible = "regulator-fixed";
  1535. regulator-name = "VDD_3V3_SD";
  1536. regulator-min-microvolt = <3300000>;
  1537. regulator-max-microvolt = <3300000>;
  1538. gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
  1539. enable-active-high;
  1540. vin-supply = <&vdd_3v3_sys>;
  1541. regulator-enable-ramp-delay = <472>;
  1542. };
  1543. vdd_dsi_csi: regulator-vdd-dsi-csi {
  1544. compatible = "regulator-fixed";
  1545. regulator-name = "AVDD_DSI_CSI_1V2";
  1546. regulator-min-microvolt = <1200000>;
  1547. regulator-max-microvolt = <1200000>;
  1548. vin-supply = <&vdd_sys_1v2>;
  1549. };
  1550. vdd_3v3_dis: regulator-vdd-3v3-dis {
  1551. compatible = "regulator-fixed";
  1552. regulator-name = "VDD_DIS_3V3_LCD";
  1553. regulator-min-microvolt = <3300000>;
  1554. regulator-max-microvolt = <3300000>;
  1555. regulator-always-on;
  1556. gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
  1557. enable-active-high;
  1558. vin-supply = <&vdd_3v3_sys>;
  1559. };
  1560. vdd_1v8_dis: regulator-vdd-1v8-dis {
  1561. compatible = "regulator-fixed";
  1562. regulator-name = "VDD_LCD_1V8_DIS";
  1563. regulator-min-microvolt = <1800000>;
  1564. regulator-max-microvolt = <1800000>;
  1565. regulator-always-on;
  1566. gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
  1567. enable-active-high;
  1568. vin-supply = <&vdd_1v8>;
  1569. };
  1570. vdd_5v0_rtl: regulator-vdd-5v0-rtl {
  1571. compatible = "regulator-fixed";
  1572. regulator-name = "RTL_5V";
  1573. regulator-min-microvolt = <5000000>;
  1574. regulator-max-microvolt = <5000000>;
  1575. gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  1576. enable-active-high;
  1577. vin-supply = <&vdd_5v0_sys>;
  1578. };
  1579. vdd_usb_vbus: regulator-vdd-usb-vbus {
  1580. compatible = "regulator-fixed";
  1581. regulator-name = "USB_VBUS_EN1";
  1582. regulator-min-microvolt = <5000000>;
  1583. regulator-max-microvolt = <5000000>;
  1584. gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
  1585. enable-active-high;
  1586. vin-supply = <&vdd_5v0_sys>;
  1587. };
  1588. vdd_hdmi: regulator-vdd-hdmi {
  1589. compatible = "regulator-fixed";
  1590. regulator-name = "VDD_HDMI_5V0";
  1591. regulator-min-microvolt = <5000000>;
  1592. regulator-max-microvolt = <5000000>;
  1593. gpio = <&exp1 12 GPIO_ACTIVE_HIGH>;
  1594. enable-active-high;
  1595. vin-supply = <&vdd_5v0_sys>;
  1596. };
  1597. vdd_cam_1v2: regulator-vdd-cam-1v2 {
  1598. compatible = "regulator-fixed";
  1599. regulator-name = "vdd-cam-1v2";
  1600. regulator-min-microvolt = <1200000>;
  1601. regulator-max-microvolt = <1200000>;
  1602. gpio = <&exp2 10 GPIO_ACTIVE_HIGH>;
  1603. enable-active-high;
  1604. vin-supply = <&vdd_3v3_sys>;
  1605. };
  1606. vdd_cam_2v8: regulator-vdd-cam-2v8 {
  1607. compatible = "regulator-fixed";
  1608. regulator-name = "vdd-cam-2v8";
  1609. regulator-min-microvolt = <2800000>;
  1610. regulator-max-microvolt = <2800000>;
  1611. gpio = <&exp1 13 GPIO_ACTIVE_HIGH>;
  1612. enable-active-high;
  1613. vin-supply = <&vdd_3v3_sys>;
  1614. };
  1615. vdd_cam_1v8: regulator-vdd-cam-1v8 {
  1616. compatible = "regulator-fixed";
  1617. regulator-name = "vdd-cam-1v8";
  1618. regulator-min-microvolt = <1800000>;
  1619. regulator-max-microvolt = <1800000>;
  1620. gpio = <&exp2 9 GPIO_ACTIVE_HIGH>;
  1621. enable-active-high;
  1622. vin-supply = <&vdd_3v3_sys>;
  1623. };
  1624. vdd_usb_vbus_otg: regulator-vdd-usb-vbus-otg {
  1625. compatible = "regulator-fixed";
  1626. regulator-name = "USB_VBUS_EN0";
  1627. regulator-min-microvolt = <5000000>;
  1628. regulator-max-microvolt = <5000000>;
  1629. gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
  1630. enable-active-high;
  1631. vin-supply = <&vdd_5v0_sys>;
  1632. };
  1633. };