tegra210-p2371-2180.dts 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include "tegra210-p2180.dtsi"
  4. #include "tegra210-p2597.dtsi"
  5. / {
  6. model = "NVIDIA Jetson TX1 Developer Kit";
  7. compatible = "nvidia,p2371-2180", "nvidia,tegra210";
  8. pcie@1003000 {
  9. status = "okay";
  10. hvddio-pex-supply = <&vdd_1v8>;
  11. dvddio-pex-supply = <&vdd_pex_1v05>;
  12. vddio-pex-ctl-supply = <&vdd_1v8>;
  13. pci@1,0 {
  14. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
  15. <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
  16. <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
  17. <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
  18. phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
  19. status = "okay";
  20. };
  21. pci@2,0 {
  22. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
  23. phy-names = "pcie-0";
  24. status = "okay";
  25. };
  26. };
  27. host1x@50000000 {
  28. dsi@54300000 {
  29. status = "okay";
  30. avdd-dsi-csi-supply = <&vdd_dsi_csi>;
  31. panel@0 {
  32. compatible = "auo,b080uan01";
  33. reg = <0>;
  34. enable-gpios = <&gpio TEGRA_GPIO(V, 2)
  35. GPIO_ACTIVE_HIGH>;
  36. power-supply = <&vdd_5v0_io>;
  37. backlight = <&backlight>;
  38. };
  39. };
  40. };
  41. i2c@7000c400 {
  42. backlight: backlight@2c {
  43. compatible = "ti,lp8557";
  44. reg = <0x2c>;
  45. power-supply = <&vdd_3v3_sys>;
  46. dev-ctrl = /bits/ 8 <0x80>;
  47. init-brt = /bits/ 8 <0xff>;
  48. pwm-period = <29334>;
  49. pwms = <&pwm 0 29334>;
  50. pwm-names = "lp8557";
  51. /* 3 LED string */
  52. rom_14h {
  53. rom-addr = /bits/ 8 <0x14>;
  54. rom-val = /bits/ 8 <0x87>;
  55. };
  56. /* boost frequency 1 MHz */
  57. rom_13h {
  58. rom-addr = /bits/ 8 <0x13>;
  59. rom-val = /bits/ 8 <0x01>;
  60. };
  61. };
  62. };
  63. i2c@7000c500 {
  64. /* carrier board ID EEPROM */
  65. eeprom@57 {
  66. compatible = "atmel,24c02";
  67. reg = <0x57>;
  68. label = "system";
  69. vcc-supply = <&vdd_1v8>;
  70. address-width = <8>;
  71. pagesize = <8>;
  72. size = <256>;
  73. read-only;
  74. };
  75. };
  76. clock@70110000 {
  77. status = "okay";
  78. nvidia,cf = <6>;
  79. nvidia,ci = <0>;
  80. nvidia,cg = <2>;
  81. nvidia,droop-ctrl = <0x00000f00>;
  82. nvidia,force-mode = <1>;
  83. nvidia,sample-rate = <25000>;
  84. nvidia,pwm-min-microvolts = <708000>;
  85. nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
  86. nvidia,pwm-to-pmic;
  87. nvidia,pwm-tristate-microvolts = <1000000>;
  88. nvidia,pwm-voltage-step-microvolts = <19200>;
  89. pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
  90. pinctrl-0 = <&dvfs_pwm_active_state>;
  91. pinctrl-1 = <&dvfs_pwm_inactive_state>;
  92. };
  93. aconnect@702c0000 {
  94. status = "okay";
  95. dma-controller@702e2000 {
  96. status = "okay";
  97. };
  98. interrupt-controller@702f9000 {
  99. status = "okay";
  100. };
  101. ahub@702d0800 {
  102. status = "okay";
  103. admaif@702d0000 {
  104. status = "okay";
  105. };
  106. i2s@702d1000 {
  107. status = "okay";
  108. ports {
  109. #address-cells = <1>;
  110. #size-cells = <0>;
  111. port@0 {
  112. reg = <0>;
  113. i2s1_cif_ep: endpoint {
  114. remote-endpoint = <&xbar_i2s1_ep>;
  115. };
  116. };
  117. i2s1_port: port@1 {
  118. reg = <1>;
  119. i2s1_dap_ep: endpoint {
  120. dai-format = "i2s";
  121. /* Placeholder for external Codec */
  122. };
  123. };
  124. };
  125. };
  126. i2s@702d1100 {
  127. status = "okay";
  128. ports {
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. port@0 {
  132. reg = <0>;
  133. i2s2_cif_ep: endpoint {
  134. remote-endpoint = <&xbar_i2s2_ep>;
  135. };
  136. };
  137. i2s2_port: port@1 {
  138. reg = <1>;
  139. i2s2_dap_ep: endpoint {
  140. dai-format = "i2s";
  141. /* Placeholder for external Codec */
  142. };
  143. };
  144. };
  145. };
  146. i2s@702d1200 {
  147. status = "okay";
  148. ports {
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. port@0 {
  152. reg = <0>;
  153. i2s3_cif_ep: endpoint {
  154. remote-endpoint = <&xbar_i2s3_ep>;
  155. };
  156. };
  157. i2s3_port: port@1 {
  158. reg = <1>;
  159. i2s3_dap_ep: endpoint {
  160. dai-format = "i2s";
  161. /* Placeholder for external Codec */
  162. };
  163. };
  164. };
  165. };
  166. i2s@702d1300 {
  167. status = "okay";
  168. ports {
  169. #address-cells = <1>;
  170. #size-cells = <0>;
  171. port@0 {
  172. reg = <0>;
  173. i2s4_cif_ep: endpoint {
  174. remote-endpoint = <&xbar_i2s4_ep>;
  175. };
  176. };
  177. i2s4_port: port@1 {
  178. reg = <1>;
  179. i2s4_dap_ep: endpoint {
  180. dai-format = "i2s";
  181. /* Placeholder for external Codec */
  182. };
  183. };
  184. };
  185. };
  186. i2s@702d1400 {
  187. status = "okay";
  188. ports {
  189. #address-cells = <1>;
  190. #size-cells = <0>;
  191. port@0 {
  192. reg = <0>;
  193. i2s5_cif_ep: endpoint {
  194. remote-endpoint = <&xbar_i2s5_ep>;
  195. };
  196. };
  197. i2s5_port: port@1 {
  198. reg = <1>;
  199. i2s5_dap_ep: endpoint {
  200. dai-format = "i2s";
  201. /* Placeholder for external Codec */
  202. };
  203. };
  204. };
  205. };
  206. dmic@702d4000 {
  207. status = "okay";
  208. ports {
  209. #address-cells = <1>;
  210. #size-cells = <0>;
  211. port@0 {
  212. reg = <0>;
  213. dmic1_cif_ep: endpoint {
  214. remote-endpoint = <&xbar_dmic1_ep>;
  215. };
  216. };
  217. dmic1_port: port@1 {
  218. reg = <1>;
  219. dmic1_dap_ep: endpoint {
  220. /* Placeholder for external Codec */
  221. };
  222. };
  223. };
  224. };
  225. dmic@702d4100 {
  226. status = "okay";
  227. ports {
  228. #address-cells = <1>;
  229. #size-cells = <0>;
  230. port@0 {
  231. reg = <0>;
  232. dmic2_cif_ep: endpoint {
  233. remote-endpoint = <&xbar_dmic2_ep>;
  234. };
  235. };
  236. dmic2_port: port@1 {
  237. reg = <1>;
  238. dmic2_dap_ep: endpoint {
  239. /* Placeholder for external Codec */
  240. };
  241. };
  242. };
  243. };
  244. dmic@702d4200 {
  245. status = "okay";
  246. ports {
  247. #address-cells = <1>;
  248. #size-cells = <0>;
  249. port@0 {
  250. reg = <0>;
  251. dmic3_cif_ep: endpoint {
  252. remote-endpoint = <&xbar_dmic3_ep>;
  253. };
  254. };
  255. dmic3_port: port@1 {
  256. reg = <1>;
  257. dmic3_dap_ep: endpoint {
  258. /* Placeholder for external Codec */
  259. };
  260. };
  261. };
  262. };
  263. sfc@702d2000 {
  264. status = "okay";
  265. ports {
  266. #address-cells = <1>;
  267. #size-cells = <0>;
  268. port@0 {
  269. reg = <0>;
  270. sfc1_cif_in_ep: endpoint {
  271. remote-endpoint = <&xbar_sfc1_in_ep>;
  272. };
  273. };
  274. sfc1_out_port: port@1 {
  275. reg = <1>;
  276. sfc1_cif_out_ep: endpoint {
  277. remote-endpoint = <&xbar_sfc1_out_ep>;
  278. };
  279. };
  280. };
  281. };
  282. sfc@702d2200 {
  283. status = "okay";
  284. ports {
  285. #address-cells = <1>;
  286. #size-cells = <0>;
  287. port@0 {
  288. reg = <0>;
  289. sfc2_cif_in_ep: endpoint {
  290. remote-endpoint = <&xbar_sfc2_in_ep>;
  291. };
  292. };
  293. sfc2_out_port: port@1 {
  294. reg = <1>;
  295. sfc2_cif_out_ep: endpoint {
  296. remote-endpoint = <&xbar_sfc2_out_ep>;
  297. };
  298. };
  299. };
  300. };
  301. sfc@702d2400 {
  302. status = "okay";
  303. ports {
  304. #address-cells = <1>;
  305. #size-cells = <0>;
  306. port@0 {
  307. reg = <0>;
  308. sfc3_cif_in_ep: endpoint {
  309. remote-endpoint = <&xbar_sfc3_in_ep>;
  310. };
  311. };
  312. sfc3_out_port: port@1 {
  313. reg = <1>;
  314. sfc3_cif_out_ep: endpoint {
  315. remote-endpoint = <&xbar_sfc3_out_ep>;
  316. };
  317. };
  318. };
  319. };
  320. sfc@702d2600 {
  321. status = "okay";
  322. ports {
  323. #address-cells = <1>;
  324. #size-cells = <0>;
  325. port@0 {
  326. reg = <0>;
  327. sfc4_cif_in_ep: endpoint {
  328. remote-endpoint = <&xbar_sfc4_in_ep>;
  329. };
  330. };
  331. sfc4_out_port: port@1 {
  332. reg = <1>;
  333. sfc4_cif_out_ep: endpoint {
  334. remote-endpoint = <&xbar_sfc4_out_ep>;
  335. };
  336. };
  337. };
  338. };
  339. mvc@702da000 {
  340. status = "okay";
  341. ports {
  342. #address-cells = <1>;
  343. #size-cells = <0>;
  344. port@0 {
  345. reg = <0>;
  346. mvc1_cif_in_ep: endpoint {
  347. remote-endpoint = <&xbar_mvc1_in_ep>;
  348. };
  349. };
  350. mvc1_out_port: port@1 {
  351. reg = <1>;
  352. mvc1_cif_out_ep: endpoint {
  353. remote-endpoint = <&xbar_mvc1_out_ep>;
  354. };
  355. };
  356. };
  357. };
  358. mvc@702da200 {
  359. status = "okay";
  360. ports {
  361. #address-cells = <1>;
  362. #size-cells = <0>;
  363. port@0 {
  364. reg = <0>;
  365. mvc2_cif_in_ep: endpoint {
  366. remote-endpoint = <&xbar_mvc2_in_ep>;
  367. };
  368. };
  369. mvc2_out_port: port@1 {
  370. reg = <1>;
  371. mvc2_cif_out_ep: endpoint {
  372. remote-endpoint = <&xbar_mvc2_out_ep>;
  373. };
  374. };
  375. };
  376. };
  377. amx@702d3000 {
  378. status = "okay";
  379. ports {
  380. #address-cells = <1>;
  381. #size-cells = <0>;
  382. port@0 {
  383. reg = <0>;
  384. amx1_in1_ep: endpoint {
  385. remote-endpoint = <&xbar_amx1_in1_ep>;
  386. };
  387. };
  388. port@1 {
  389. reg = <1>;
  390. amx1_in2_ep: endpoint {
  391. remote-endpoint = <&xbar_amx1_in2_ep>;
  392. };
  393. };
  394. port@2 {
  395. reg = <2>;
  396. amx1_in3_ep: endpoint {
  397. remote-endpoint = <&xbar_amx1_in3_ep>;
  398. };
  399. };
  400. port@3 {
  401. reg = <3>;
  402. amx1_in4_ep: endpoint {
  403. remote-endpoint = <&xbar_amx1_in4_ep>;
  404. };
  405. };
  406. amx1_out_port: port@4 {
  407. reg = <4>;
  408. amx1_out_ep: endpoint {
  409. remote-endpoint = <&xbar_amx1_out_ep>;
  410. };
  411. };
  412. };
  413. };
  414. amx@702d3100 {
  415. status = "okay";
  416. ports {
  417. #address-cells = <1>;
  418. #size-cells = <0>;
  419. port@0 {
  420. reg = <0>;
  421. amx2_in1_ep: endpoint {
  422. remote-endpoint = <&xbar_amx2_in1_ep>;
  423. };
  424. };
  425. port@1 {
  426. reg = <1>;
  427. amx2_in2_ep: endpoint {
  428. remote-endpoint = <&xbar_amx2_in2_ep>;
  429. };
  430. };
  431. amx2_in3_port: port@2 {
  432. reg = <2>;
  433. amx2_in3_ep: endpoint {
  434. remote-endpoint = <&xbar_amx2_in3_ep>;
  435. };
  436. };
  437. amx2_in4_port: port@3 {
  438. reg = <3>;
  439. amx2_in4_ep: endpoint {
  440. remote-endpoint = <&xbar_amx2_in4_ep>;
  441. };
  442. };
  443. amx2_out_port: port@4 {
  444. reg = <4>;
  445. amx2_out_ep: endpoint {
  446. remote-endpoint = <&xbar_amx2_out_ep>;
  447. };
  448. };
  449. };
  450. };
  451. adx@702d3800 {
  452. status = "okay";
  453. ports {
  454. #address-cells = <1>;
  455. #size-cells = <0>;
  456. port@0 {
  457. reg = <0>;
  458. adx1_in_ep: endpoint {
  459. remote-endpoint = <&xbar_adx1_in_ep>;
  460. };
  461. };
  462. adx1_out1_port: port@1 {
  463. reg = <1>;
  464. adx1_out1_ep: endpoint {
  465. remote-endpoint = <&xbar_adx1_out1_ep>;
  466. };
  467. };
  468. adx1_out2_port: port@2 {
  469. reg = <2>;
  470. adx1_out2_ep: endpoint {
  471. remote-endpoint = <&xbar_adx1_out2_ep>;
  472. };
  473. };
  474. adx1_out3_port: port@3 {
  475. reg = <3>;
  476. adx1_out3_ep: endpoint {
  477. remote-endpoint = <&xbar_adx1_out3_ep>;
  478. };
  479. };
  480. adx1_out4_port: port@4 {
  481. reg = <4>;
  482. adx1_out4_ep: endpoint {
  483. remote-endpoint = <&xbar_adx1_out4_ep>;
  484. };
  485. };
  486. };
  487. };
  488. adx@702d3900 {
  489. status = "okay";
  490. ports {
  491. #address-cells = <1>;
  492. #size-cells = <0>;
  493. port@0 {
  494. reg = <0>;
  495. adx2_in_ep: endpoint {
  496. remote-endpoint = <&xbar_adx2_in_ep>;
  497. };
  498. };
  499. adx2_out1_port: port@1 {
  500. reg = <1>;
  501. adx2_out1_ep: endpoint {
  502. remote-endpoint = <&xbar_adx2_out1_ep>;
  503. };
  504. };
  505. adx2_out2_port: port@2 {
  506. reg = <2>;
  507. adx2_out2_ep: endpoint {
  508. remote-endpoint = <&xbar_adx2_out2_ep>;
  509. };
  510. };
  511. adx2_out3_port: port@3 {
  512. reg = <3>;
  513. adx2_out3_ep: endpoint {
  514. remote-endpoint = <&xbar_adx2_out3_ep>;
  515. };
  516. };
  517. adx2_out4_port: port@4 {
  518. reg = <4>;
  519. adx2_out4_ep: endpoint {
  520. remote-endpoint = <&xbar_adx2_out4_ep>;
  521. };
  522. };
  523. };
  524. };
  525. processing-engine@702d8000 {
  526. status = "okay";
  527. ports {
  528. #address-cells = <1>;
  529. #size-cells = <0>;
  530. port@0 {
  531. reg = <0x0>;
  532. ope1_cif_in_ep: endpoint {
  533. remote-endpoint = <&xbar_ope1_in_ep>;
  534. };
  535. };
  536. ope1_out_port: port@1 {
  537. reg = <0x1>;
  538. ope1_cif_out_ep: endpoint {
  539. remote-endpoint = <&xbar_ope1_out_ep>;
  540. };
  541. };
  542. };
  543. };
  544. processing-engine@702d8400 {
  545. status = "okay";
  546. ports {
  547. #address-cells = <1>;
  548. #size-cells = <0>;
  549. port@0 {
  550. reg = <0x0>;
  551. ope2_cif_in_ep: endpoint {
  552. remote-endpoint = <&xbar_ope2_in_ep>;
  553. };
  554. };
  555. ope2_out_port: port@1 {
  556. reg = <0x1>;
  557. ope2_cif_out_ep: endpoint {
  558. remote-endpoint = <&xbar_ope2_out_ep>;
  559. };
  560. };
  561. };
  562. };
  563. amixer@702dbb00 {
  564. status = "okay";
  565. ports {
  566. #address-cells = <1>;
  567. #size-cells = <0>;
  568. port@0 {
  569. reg = <0x0>;
  570. mixer_in1_ep: endpoint {
  571. remote-endpoint = <&xbar_mixer_in1_ep>;
  572. };
  573. };
  574. port@1 {
  575. reg = <0x1>;
  576. mixer_in2_ep: endpoint {
  577. remote-endpoint = <&xbar_mixer_in2_ep>;
  578. };
  579. };
  580. port@2 {
  581. reg = <0x2>;
  582. mixer_in3_ep: endpoint {
  583. remote-endpoint = <&xbar_mixer_in3_ep>;
  584. };
  585. };
  586. port@3 {
  587. reg = <0x3>;
  588. mixer_in4_ep: endpoint {
  589. remote-endpoint = <&xbar_mixer_in4_ep>;
  590. };
  591. };
  592. port@4 {
  593. reg = <0x4>;
  594. mixer_in5_ep: endpoint {
  595. remote-endpoint = <&xbar_mixer_in5_ep>;
  596. };
  597. };
  598. port@5 {
  599. reg = <0x5>;
  600. mixer_in6_ep: endpoint {
  601. remote-endpoint = <&xbar_mixer_in6_ep>;
  602. };
  603. };
  604. port@6 {
  605. reg = <0x6>;
  606. mixer_in7_ep: endpoint {
  607. remote-endpoint = <&xbar_mixer_in7_ep>;
  608. };
  609. };
  610. port@7 {
  611. reg = <0x7>;
  612. mixer_in8_ep: endpoint {
  613. remote-endpoint = <&xbar_mixer_in8_ep>;
  614. };
  615. };
  616. port@8 {
  617. reg = <0x8>;
  618. mixer_in9_ep: endpoint {
  619. remote-endpoint = <&xbar_mixer_in9_ep>;
  620. };
  621. };
  622. port@9 {
  623. reg = <0x9>;
  624. mixer_in10_ep: endpoint {
  625. remote-endpoint = <&xbar_mixer_in10_ep>;
  626. };
  627. };
  628. mixer_out1_port: port@a {
  629. reg = <0xa>;
  630. mixer_out1_ep: endpoint {
  631. remote-endpoint = <&xbar_mixer_out1_ep>;
  632. };
  633. };
  634. mixer_out2_port: port@b {
  635. reg = <0xb>;
  636. mixer_out2_ep: endpoint {
  637. remote-endpoint = <&xbar_mixer_out2_ep>;
  638. };
  639. };
  640. mixer_out3_port: port@c {
  641. reg = <0xc>;
  642. mixer_out3_ep: endpoint {
  643. remote-endpoint = <&xbar_mixer_out3_ep>;
  644. };
  645. };
  646. mixer_out4_port: port@d {
  647. reg = <0xd>;
  648. mixer_out4_ep: endpoint {
  649. remote-endpoint = <&xbar_mixer_out4_ep>;
  650. };
  651. };
  652. mixer_out5_port: port@e {
  653. reg = <0xe>;
  654. mixer_out5_ep: endpoint {
  655. remote-endpoint = <&xbar_mixer_out5_ep>;
  656. };
  657. };
  658. };
  659. };
  660. ports {
  661. xbar_i2s1_port: port@a {
  662. reg = <0xa>;
  663. xbar_i2s1_ep: endpoint {
  664. remote-endpoint = <&i2s1_cif_ep>;
  665. };
  666. };
  667. xbar_i2s2_port: port@b {
  668. reg = <0xb>;
  669. xbar_i2s2_ep: endpoint {
  670. remote-endpoint = <&i2s2_cif_ep>;
  671. };
  672. };
  673. xbar_i2s3_port: port@c {
  674. reg = <0xc>;
  675. xbar_i2s3_ep: endpoint {
  676. remote-endpoint = <&i2s3_cif_ep>;
  677. };
  678. };
  679. xbar_i2s4_port: port@d {
  680. reg = <0xd>;
  681. xbar_i2s4_ep: endpoint {
  682. remote-endpoint = <&i2s4_cif_ep>;
  683. };
  684. };
  685. xbar_i2s5_port: port@e {
  686. reg = <0xe>;
  687. xbar_i2s5_ep: endpoint {
  688. remote-endpoint = <&i2s5_cif_ep>;
  689. };
  690. };
  691. xbar_dmic1_port: port@f {
  692. reg = <0xf>;
  693. xbar_dmic1_ep: endpoint {
  694. remote-endpoint = <&dmic1_cif_ep>;
  695. };
  696. };
  697. xbar_dmic2_port: port@10 {
  698. reg = <0x10>;
  699. xbar_dmic2_ep: endpoint {
  700. remote-endpoint = <&dmic2_cif_ep>;
  701. };
  702. };
  703. xbar_dmic3_port: port@11 {
  704. reg = <0x11>;
  705. xbar_dmic3_ep: endpoint {
  706. remote-endpoint = <&dmic3_cif_ep>;
  707. };
  708. };
  709. xbar_sfc1_in_port: port@12 {
  710. reg = <0x12>;
  711. xbar_sfc1_in_ep: endpoint {
  712. remote-endpoint = <&sfc1_cif_in_ep>;
  713. };
  714. };
  715. port@13 {
  716. reg = <0x13>;
  717. xbar_sfc1_out_ep: endpoint {
  718. remote-endpoint = <&sfc1_cif_out_ep>;
  719. };
  720. };
  721. xbar_sfc2_in_port: port@14 {
  722. reg = <0x14>;
  723. xbar_sfc2_in_ep: endpoint {
  724. remote-endpoint = <&sfc2_cif_in_ep>;
  725. };
  726. };
  727. port@15 {
  728. reg = <0x15>;
  729. xbar_sfc2_out_ep: endpoint {
  730. remote-endpoint = <&sfc2_cif_out_ep>;
  731. };
  732. };
  733. xbar_sfc3_in_port: port@16 {
  734. reg = <0x16>;
  735. xbar_sfc3_in_ep: endpoint {
  736. remote-endpoint = <&sfc3_cif_in_ep>;
  737. };
  738. };
  739. port@17 {
  740. reg = <0x17>;
  741. xbar_sfc3_out_ep: endpoint {
  742. remote-endpoint = <&sfc3_cif_out_ep>;
  743. };
  744. };
  745. xbar_sfc4_in_port: port@18 {
  746. reg = <0x18>;
  747. xbar_sfc4_in_ep: endpoint {
  748. remote-endpoint = <&sfc4_cif_in_ep>;
  749. };
  750. };
  751. port@19 {
  752. reg = <0x19>;
  753. xbar_sfc4_out_ep: endpoint {
  754. remote-endpoint = <&sfc4_cif_out_ep>;
  755. };
  756. };
  757. xbar_mvc1_in_port: port@1a {
  758. reg = <0x1a>;
  759. xbar_mvc1_in_ep: endpoint {
  760. remote-endpoint = <&mvc1_cif_in_ep>;
  761. };
  762. };
  763. port@1b {
  764. reg = <0x1b>;
  765. xbar_mvc1_out_ep: endpoint {
  766. remote-endpoint = <&mvc1_cif_out_ep>;
  767. };
  768. };
  769. xbar_mvc2_in_port: port@1c {
  770. reg = <0x1c>;
  771. xbar_mvc2_in_ep: endpoint {
  772. remote-endpoint = <&mvc2_cif_in_ep>;
  773. };
  774. };
  775. port@1d {
  776. reg = <0x1d>;
  777. xbar_mvc2_out_ep: endpoint {
  778. remote-endpoint = <&mvc2_cif_out_ep>;
  779. };
  780. };
  781. xbar_amx1_in1_port: port@1e {
  782. reg = <0x1e>;
  783. xbar_amx1_in1_ep: endpoint {
  784. remote-endpoint = <&amx1_in1_ep>;
  785. };
  786. };
  787. xbar_amx1_in2_port: port@1f {
  788. reg = <0x1f>;
  789. xbar_amx1_in2_ep: endpoint {
  790. remote-endpoint = <&amx1_in2_ep>;
  791. };
  792. };
  793. xbar_amx1_in3_port: port@20 {
  794. reg = <0x20>;
  795. xbar_amx1_in3_ep: endpoint {
  796. remote-endpoint = <&amx1_in3_ep>;
  797. };
  798. };
  799. xbar_amx1_in4_port: port@21 {
  800. reg = <0x21>;
  801. xbar_amx1_in4_ep: endpoint {
  802. remote-endpoint = <&amx1_in4_ep>;
  803. };
  804. };
  805. port@22 {
  806. reg = <0x22>;
  807. xbar_amx1_out_ep: endpoint {
  808. remote-endpoint = <&amx1_out_ep>;
  809. };
  810. };
  811. xbar_amx2_in1_port: port@23 {
  812. reg = <0x23>;
  813. xbar_amx2_in1_ep: endpoint {
  814. remote-endpoint = <&amx2_in1_ep>;
  815. };
  816. };
  817. xbar_amx2_in2_port: port@24 {
  818. reg = <0x24>;
  819. xbar_amx2_in2_ep: endpoint {
  820. remote-endpoint = <&amx2_in2_ep>;
  821. };
  822. };
  823. xbar_amx2_in3_port: port@25 {
  824. reg = <0x25>;
  825. xbar_amx2_in3_ep: endpoint {
  826. remote-endpoint = <&amx2_in3_ep>;
  827. };
  828. };
  829. xbar_amx2_in4_port: port@26 {
  830. reg = <0x26>;
  831. xbar_amx2_in4_ep: endpoint {
  832. remote-endpoint = <&amx2_in4_ep>;
  833. };
  834. };
  835. port@27 {
  836. reg = <0x27>;
  837. xbar_amx2_out_ep: endpoint {
  838. remote-endpoint = <&amx2_out_ep>;
  839. };
  840. };
  841. xbar_adx1_in_port: port@28 {
  842. reg = <0x28>;
  843. xbar_adx1_in_ep: endpoint {
  844. remote-endpoint = <&adx1_in_ep>;
  845. };
  846. };
  847. port@29 {
  848. reg = <0x29>;
  849. xbar_adx1_out1_ep: endpoint {
  850. remote-endpoint = <&adx1_out1_ep>;
  851. };
  852. };
  853. port@2a {
  854. reg = <0x2a>;
  855. xbar_adx1_out2_ep: endpoint {
  856. remote-endpoint = <&adx1_out2_ep>;
  857. };
  858. };
  859. port@2b {
  860. reg = <0x2b>;
  861. xbar_adx1_out3_ep: endpoint {
  862. remote-endpoint = <&adx1_out3_ep>;
  863. };
  864. };
  865. port@2c {
  866. reg = <0x2c>;
  867. xbar_adx1_out4_ep: endpoint {
  868. remote-endpoint = <&adx1_out4_ep>;
  869. };
  870. };
  871. xbar_adx2_in_port: port@2d {
  872. reg = <0x2d>;
  873. xbar_adx2_in_ep: endpoint {
  874. remote-endpoint = <&adx2_in_ep>;
  875. };
  876. };
  877. port@2e {
  878. reg = <0x2e>;
  879. xbar_adx2_out1_ep: endpoint {
  880. remote-endpoint = <&adx2_out1_ep>;
  881. };
  882. };
  883. port@2f {
  884. reg = <0x2f>;
  885. xbar_adx2_out2_ep: endpoint {
  886. remote-endpoint = <&adx2_out2_ep>;
  887. };
  888. };
  889. port@30 {
  890. reg = <0x30>;
  891. xbar_adx2_out3_ep: endpoint {
  892. remote-endpoint = <&adx2_out3_ep>;
  893. };
  894. };
  895. port@31 {
  896. reg = <0x31>;
  897. xbar_adx2_out4_ep: endpoint {
  898. remote-endpoint = <&adx2_out4_ep>;
  899. };
  900. };
  901. xbar_mixer_in1_port: port@32 {
  902. reg = <0x32>;
  903. xbar_mixer_in1_ep: endpoint {
  904. remote-endpoint = <&mixer_in1_ep>;
  905. };
  906. };
  907. xbar_mixer_in2_port: port@33 {
  908. reg = <0x33>;
  909. xbar_mixer_in2_ep: endpoint {
  910. remote-endpoint = <&mixer_in2_ep>;
  911. };
  912. };
  913. xbar_mixer_in3_port: port@34 {
  914. reg = <0x34>;
  915. xbar_mixer_in3_ep: endpoint {
  916. remote-endpoint = <&mixer_in3_ep>;
  917. };
  918. };
  919. xbar_mixer_in4_port: port@35 {
  920. reg = <0x35>;
  921. xbar_mixer_in4_ep: endpoint {
  922. remote-endpoint = <&mixer_in4_ep>;
  923. };
  924. };
  925. xbar_mixer_in5_port: port@36 {
  926. reg = <0x36>;
  927. xbar_mixer_in5_ep: endpoint {
  928. remote-endpoint = <&mixer_in5_ep>;
  929. };
  930. };
  931. xbar_mixer_in6_port: port@37 {
  932. reg = <0x37>;
  933. xbar_mixer_in6_ep: endpoint {
  934. remote-endpoint = <&mixer_in6_ep>;
  935. };
  936. };
  937. xbar_mixer_in7_port: port@38 {
  938. reg = <0x38>;
  939. xbar_mixer_in7_ep: endpoint {
  940. remote-endpoint = <&mixer_in7_ep>;
  941. };
  942. };
  943. xbar_mixer_in8_port: port@39 {
  944. reg = <0x39>;
  945. xbar_mixer_in8_ep: endpoint {
  946. remote-endpoint = <&mixer_in8_ep>;
  947. };
  948. };
  949. xbar_mixer_in9_port: port@3a {
  950. reg = <0x3a>;
  951. xbar_mixer_in9_ep: endpoint {
  952. remote-endpoint = <&mixer_in9_ep>;
  953. };
  954. };
  955. xbar_mixer_in10_port: port@3b {
  956. reg = <0x3b>;
  957. xbar_mixer_in10_ep: endpoint {
  958. remote-endpoint = <&mixer_in10_ep>;
  959. };
  960. };
  961. port@3c {
  962. reg = <0x3c>;
  963. xbar_mixer_out1_ep: endpoint {
  964. remote-endpoint = <&mixer_out1_ep>;
  965. };
  966. };
  967. port@3d {
  968. reg = <0x3d>;
  969. xbar_mixer_out2_ep: endpoint {
  970. remote-endpoint = <&mixer_out2_ep>;
  971. };
  972. };
  973. port@3e {
  974. reg = <0x3e>;
  975. xbar_mixer_out3_ep: endpoint {
  976. remote-endpoint = <&mixer_out3_ep>;
  977. };
  978. };
  979. port@3f {
  980. reg = <0x3f>;
  981. xbar_mixer_out4_ep: endpoint {
  982. remote-endpoint = <&mixer_out4_ep>;
  983. };
  984. };
  985. port@40 {
  986. reg = <0x40>;
  987. xbar_mixer_out5_ep: endpoint {
  988. remote-endpoint = <&mixer_out5_ep>;
  989. };
  990. };
  991. xbar_ope1_in_port: port@41 {
  992. reg = <0x41>;
  993. xbar_ope1_in_ep: endpoint {
  994. remote-endpoint = <&ope1_cif_in_ep>;
  995. };
  996. };
  997. port@42 {
  998. reg = <0x42>;
  999. xbar_ope1_out_ep: endpoint {
  1000. remote-endpoint = <&ope1_cif_out_ep>;
  1001. };
  1002. };
  1003. xbar_ope2_in_port: port@43 {
  1004. reg = <0x43>;
  1005. xbar_ope2_in_ep: endpoint {
  1006. remote-endpoint = <&ope2_cif_in_ep>;
  1007. };
  1008. };
  1009. port@44 {
  1010. reg = <0x44>;
  1011. xbar_ope2_out_ep: endpoint {
  1012. remote-endpoint = <&ope2_cif_out_ep>;
  1013. };
  1014. };
  1015. };
  1016. };
  1017. };
  1018. sound {
  1019. compatible = "nvidia,tegra210-audio-graph-card";
  1020. status = "okay";
  1021. dais = /* FE */
  1022. <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
  1023. <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
  1024. <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
  1025. <&admaif10_port>,
  1026. /* Router */
  1027. <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
  1028. <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_dmic1_port>,
  1029. <&xbar_dmic2_port>, <&xbar_dmic3_port>,
  1030. <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
  1031. <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
  1032. <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
  1033. <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
  1034. <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
  1035. <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
  1036. <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
  1037. <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
  1038. <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
  1039. <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
  1040. <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
  1041. <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
  1042. <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
  1043. <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
  1044. /* HW accelerators */
  1045. <&sfc1_out_port>, <&sfc2_out_port>,
  1046. <&sfc3_out_port>, <&sfc4_out_port>,
  1047. <&mvc1_out_port>, <&mvc2_out_port>,
  1048. <&amx1_out_port>, <&amx2_out_port>,
  1049. <&adx1_out1_port>, <&adx1_out2_port>,
  1050. <&adx1_out3_port>, <&adx1_out4_port>,
  1051. <&adx2_out1_port>, <&adx2_out2_port>,
  1052. <&adx2_out3_port>, <&adx2_out4_port>,
  1053. <&mixer_out1_port>, <&mixer_out2_port>,
  1054. <&mixer_out3_port>, <&mixer_out4_port>,
  1055. <&mixer_out5_port>,
  1056. <&ope1_out_port>, <&ope2_out_port>,
  1057. /* I/O DAP Ports */
  1058. <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
  1059. <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
  1060. label = "NVIDIA Jetson TX1 APE";
  1061. };
  1062. };