tegra186-p2771-0000.dts 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/linux-event-codes.h>
  4. #include <dt-bindings/input/gpio-keys.h>
  5. #include "tegra186-p3310.dtsi"
  6. / {
  7. model = "NVIDIA Jetson TX2 Developer Kit";
  8. compatible = "nvidia,p2771-0000", "nvidia,tegra186";
  9. aconnect@2900000 {
  10. status = "okay";
  11. dma-controller@2930000 {
  12. status = "okay";
  13. };
  14. interrupt-controller@2a40000 {
  15. status = "okay";
  16. };
  17. ahub@2900800 {
  18. status = "okay";
  19. ports {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. port@0 {
  23. reg = <0x0>;
  24. xbar_admaif0_ep: endpoint {
  25. remote-endpoint = <&admaif0_ep>;
  26. };
  27. };
  28. port@1 {
  29. reg = <0x1>;
  30. xbar_admaif1_ep: endpoint {
  31. remote-endpoint = <&admaif1_ep>;
  32. };
  33. };
  34. port@2 {
  35. reg = <0x2>;
  36. xbar_admaif2_ep: endpoint {
  37. remote-endpoint = <&admaif2_ep>;
  38. };
  39. };
  40. port@3 {
  41. reg = <0x3>;
  42. xbar_admaif3_ep: endpoint {
  43. remote-endpoint = <&admaif3_ep>;
  44. };
  45. };
  46. port@4 {
  47. reg = <0x4>;
  48. xbar_admaif4_ep: endpoint {
  49. remote-endpoint = <&admaif4_ep>;
  50. };
  51. };
  52. port@5 {
  53. reg = <0x5>;
  54. xbar_admaif5_ep: endpoint {
  55. remote-endpoint = <&admaif5_ep>;
  56. };
  57. };
  58. port@6 {
  59. reg = <0x6>;
  60. xbar_admaif6_ep: endpoint {
  61. remote-endpoint = <&admaif6_ep>;
  62. };
  63. };
  64. port@7 {
  65. reg = <0x7>;
  66. xbar_admaif7_ep: endpoint {
  67. remote-endpoint = <&admaif7_ep>;
  68. };
  69. };
  70. port@8 {
  71. reg = <0x8>;
  72. xbar_admaif8_ep: endpoint {
  73. remote-endpoint = <&admaif8_ep>;
  74. };
  75. };
  76. port@9 {
  77. reg = <0x9>;
  78. xbar_admaif9_ep: endpoint {
  79. remote-endpoint = <&admaif9_ep>;
  80. };
  81. };
  82. port@a {
  83. reg = <0xa>;
  84. xbar_admaif10_ep: endpoint {
  85. remote-endpoint = <&admaif10_ep>;
  86. };
  87. };
  88. port@b {
  89. reg = <0xb>;
  90. xbar_admaif11_ep: endpoint {
  91. remote-endpoint = <&admaif11_ep>;
  92. };
  93. };
  94. port@c {
  95. reg = <0xc>;
  96. xbar_admaif12_ep: endpoint {
  97. remote-endpoint = <&admaif12_ep>;
  98. };
  99. };
  100. port@d {
  101. reg = <0xd>;
  102. xbar_admaif13_ep: endpoint {
  103. remote-endpoint = <&admaif13_ep>;
  104. };
  105. };
  106. port@e {
  107. reg = <0xe>;
  108. xbar_admaif14_ep: endpoint {
  109. remote-endpoint = <&admaif14_ep>;
  110. };
  111. };
  112. port@f {
  113. reg = <0xf>;
  114. xbar_admaif15_ep: endpoint {
  115. remote-endpoint = <&admaif15_ep>;
  116. };
  117. };
  118. port@10 {
  119. reg = <0x10>;
  120. xbar_admaif16_ep: endpoint {
  121. remote-endpoint = <&admaif16_ep>;
  122. };
  123. };
  124. port@11 {
  125. reg = <0x11>;
  126. xbar_admaif17_ep: endpoint {
  127. remote-endpoint = <&admaif17_ep>;
  128. };
  129. };
  130. port@12 {
  131. reg = <0x12>;
  132. xbar_admaif18_ep: endpoint {
  133. remote-endpoint = <&admaif18_ep>;
  134. };
  135. };
  136. port@13 {
  137. reg = <0x13>;
  138. xbar_admaif19_ep: endpoint {
  139. remote-endpoint = <&admaif19_ep>;
  140. };
  141. };
  142. xbar_i2s1_port: port@14 {
  143. reg = <0x14>;
  144. xbar_i2s1_ep: endpoint {
  145. remote-endpoint = <&i2s1_cif_ep>;
  146. };
  147. };
  148. xbar_i2s2_port: port@15 {
  149. reg = <0x15>;
  150. xbar_i2s2_ep: endpoint {
  151. remote-endpoint = <&i2s2_cif_ep>;
  152. };
  153. };
  154. xbar_i2s3_port: port@16 {
  155. reg = <0x16>;
  156. xbar_i2s3_ep: endpoint {
  157. remote-endpoint = <&i2s3_cif_ep>;
  158. };
  159. };
  160. xbar_i2s4_port: port@17 {
  161. reg = <0x17>;
  162. xbar_i2s4_ep: endpoint {
  163. remote-endpoint = <&i2s4_cif_ep>;
  164. };
  165. };
  166. xbar_i2s5_port: port@18 {
  167. reg = <0x18>;
  168. xbar_i2s5_ep: endpoint {
  169. remote-endpoint = <&i2s5_cif_ep>;
  170. };
  171. };
  172. xbar_i2s6_port: port@19 {
  173. reg = <0x19>;
  174. xbar_i2s6_ep: endpoint {
  175. remote-endpoint = <&i2s6_cif_ep>;
  176. };
  177. };
  178. xbar_dmic1_port: port@1a {
  179. reg = <0x1a>;
  180. xbar_dmic1_ep: endpoint {
  181. remote-endpoint = <&dmic1_cif_ep>;
  182. };
  183. };
  184. xbar_dmic2_port: port@1b {
  185. reg = <0x1b>;
  186. xbar_dmic2_ep: endpoint {
  187. remote-endpoint = <&dmic2_cif_ep>;
  188. };
  189. };
  190. xbar_dmic3_port: port@1c {
  191. reg = <0x1c>;
  192. xbar_dmic3_ep: endpoint {
  193. remote-endpoint = <&dmic3_cif_ep>;
  194. };
  195. };
  196. xbar_dspk1_port: port@1e {
  197. reg = <0x1e>;
  198. xbar_dspk1_ep: endpoint {
  199. remote-endpoint = <&dspk1_cif_ep>;
  200. };
  201. };
  202. xbar_dspk2_port: port@1f {
  203. reg = <0x1f>;
  204. xbar_dspk2_ep: endpoint {
  205. remote-endpoint = <&dspk2_cif_ep>;
  206. };
  207. };
  208. xbar_sfc1_in_port: port@20 {
  209. reg = <0x20>;
  210. xbar_sfc1_in_ep: endpoint {
  211. remote-endpoint = <&sfc1_cif_in_ep>;
  212. };
  213. };
  214. port@21 {
  215. reg = <0x21>;
  216. xbar_sfc1_out_ep: endpoint {
  217. remote-endpoint = <&sfc1_cif_out_ep>;
  218. };
  219. };
  220. xbar_sfc2_in_port: port@22 {
  221. reg = <0x22>;
  222. xbar_sfc2_in_ep: endpoint {
  223. remote-endpoint = <&sfc2_cif_in_ep>;
  224. };
  225. };
  226. port@23 {
  227. reg = <0x23>;
  228. xbar_sfc2_out_ep: endpoint {
  229. remote-endpoint = <&sfc2_cif_out_ep>;
  230. };
  231. };
  232. xbar_sfc3_in_port: port@24 {
  233. reg = <0x24>;
  234. xbar_sfc3_in_ep: endpoint {
  235. remote-endpoint = <&sfc3_cif_in_ep>;
  236. };
  237. };
  238. port@25 {
  239. reg = <0x25>;
  240. xbar_sfc3_out_ep: endpoint {
  241. remote-endpoint = <&sfc3_cif_out_ep>;
  242. };
  243. };
  244. xbar_sfc4_in_port: port@26 {
  245. reg = <0x26>;
  246. xbar_sfc4_in_ep: endpoint {
  247. remote-endpoint = <&sfc4_cif_in_ep>;
  248. };
  249. };
  250. port@27 {
  251. reg = <0x27>;
  252. xbar_sfc4_out_ep: endpoint {
  253. remote-endpoint = <&sfc4_cif_out_ep>;
  254. };
  255. };
  256. xbar_mvc1_in_port: port@28 {
  257. reg = <0x28>;
  258. xbar_mvc1_in_ep: endpoint {
  259. remote-endpoint = <&mvc1_cif_in_ep>;
  260. };
  261. };
  262. port@29 {
  263. reg = <0x29>;
  264. xbar_mvc1_out_ep: endpoint {
  265. remote-endpoint = <&mvc1_cif_out_ep>;
  266. };
  267. };
  268. xbar_mvc2_in_port: port@2a {
  269. reg = <0x2a>;
  270. xbar_mvc2_in_ep: endpoint {
  271. remote-endpoint = <&mvc2_cif_in_ep>;
  272. };
  273. };
  274. port@2b {
  275. reg = <0x2b>;
  276. xbar_mvc2_out_ep: endpoint {
  277. remote-endpoint = <&mvc2_cif_out_ep>;
  278. };
  279. };
  280. xbar_amx1_in1_port: port@2c {
  281. reg = <0x2c>;
  282. xbar_amx1_in1_ep: endpoint {
  283. remote-endpoint = <&amx1_in1_ep>;
  284. };
  285. };
  286. xbar_amx1_in2_port: port@2d {
  287. reg = <0x2d>;
  288. xbar_amx1_in2_ep: endpoint {
  289. remote-endpoint = <&amx1_in2_ep>;
  290. };
  291. };
  292. xbar_amx1_in3_port: port@2e {
  293. reg = <0x2e>;
  294. xbar_amx1_in3_ep: endpoint {
  295. remote-endpoint = <&amx1_in3_ep>;
  296. };
  297. };
  298. xbar_amx1_in4_port: port@2f {
  299. reg = <0x2f>;
  300. xbar_amx1_in4_ep: endpoint {
  301. remote-endpoint = <&amx1_in4_ep>;
  302. };
  303. };
  304. port@30 {
  305. reg = <0x30>;
  306. xbar_amx1_out_ep: endpoint {
  307. remote-endpoint = <&amx1_out_ep>;
  308. };
  309. };
  310. xbar_amx2_in1_port: port@31 {
  311. reg = <0x31>;
  312. xbar_amx2_in1_ep: endpoint {
  313. remote-endpoint = <&amx2_in1_ep>;
  314. };
  315. };
  316. xbar_amx2_in2_port: port@32 {
  317. reg = <0x32>;
  318. xbar_amx2_in2_ep: endpoint {
  319. remote-endpoint = <&amx2_in2_ep>;
  320. };
  321. };
  322. xbar_amx2_in3_port: port@33 {
  323. reg = <0x33>;
  324. xbar_amx2_in3_ep: endpoint {
  325. remote-endpoint = <&amx2_in3_ep>;
  326. };
  327. };
  328. xbar_amx2_in4_port: port@34 {
  329. reg = <0x34>;
  330. xbar_amx2_in4_ep: endpoint {
  331. remote-endpoint = <&amx2_in4_ep>;
  332. };
  333. };
  334. port@35 {
  335. reg = <0x35>;
  336. xbar_amx2_out_ep: endpoint {
  337. remote-endpoint = <&amx2_out_ep>;
  338. };
  339. };
  340. xbar_amx3_in1_port: port@36 {
  341. reg = <0x36>;
  342. xbar_amx3_in1_ep: endpoint {
  343. remote-endpoint = <&amx3_in1_ep>;
  344. };
  345. };
  346. xbar_amx3_in2_port: port@37 {
  347. reg = <0x37>;
  348. xbar_amx3_in2_ep: endpoint {
  349. remote-endpoint = <&amx3_in2_ep>;
  350. };
  351. };
  352. xbar_amx3_in3_port: port@38 {
  353. reg = <0x38>;
  354. xbar_amx3_in3_ep: endpoint {
  355. remote-endpoint = <&amx3_in3_ep>;
  356. };
  357. };
  358. xbar_amx3_in4_port: port@39 {
  359. reg = <0x39>;
  360. xbar_amx3_in4_ep: endpoint {
  361. remote-endpoint = <&amx3_in4_ep>;
  362. };
  363. };
  364. port@3a {
  365. reg = <0x3a>;
  366. xbar_amx3_out_ep: endpoint {
  367. remote-endpoint = <&amx3_out_ep>;
  368. };
  369. };
  370. xbar_amx4_in1_port: port@3b {
  371. reg = <0x3b>;
  372. xbar_amx4_in1_ep: endpoint {
  373. remote-endpoint = <&amx4_in1_ep>;
  374. };
  375. };
  376. xbar_amx4_in2_port: port@3c {
  377. reg = <0x3c>;
  378. xbar_amx4_in2_ep: endpoint {
  379. remote-endpoint = <&amx4_in2_ep>;
  380. };
  381. };
  382. xbar_amx4_in3_port: port@3d {
  383. reg = <0x3d>;
  384. xbar_amx4_in3_ep: endpoint {
  385. remote-endpoint = <&amx4_in3_ep>;
  386. };
  387. };
  388. xbar_amx4_in4_port: port@3e {
  389. reg = <0x3e>;
  390. xbar_amx4_in4_ep: endpoint {
  391. remote-endpoint = <&amx4_in4_ep>;
  392. };
  393. };
  394. port@3f {
  395. reg = <0x3f>;
  396. xbar_amx4_out_ep: endpoint {
  397. remote-endpoint = <&amx4_out_ep>;
  398. };
  399. };
  400. xbar_adx1_in_port: port@40 {
  401. reg = <0x40>;
  402. xbar_adx1_in_ep: endpoint {
  403. remote-endpoint = <&adx1_in_ep>;
  404. };
  405. };
  406. port@41 {
  407. reg = <0x41>;
  408. xbar_adx1_out1_ep: endpoint {
  409. remote-endpoint = <&adx1_out1_ep>;
  410. };
  411. };
  412. port@42 {
  413. reg = <0x42>;
  414. xbar_adx1_out2_ep: endpoint {
  415. remote-endpoint = <&adx1_out2_ep>;
  416. };
  417. };
  418. port@43 {
  419. reg = <0x43>;
  420. xbar_adx1_out3_ep: endpoint {
  421. remote-endpoint = <&adx1_out3_ep>;
  422. };
  423. };
  424. port@44 {
  425. reg = <0x44>;
  426. xbar_adx1_out4_ep: endpoint {
  427. remote-endpoint = <&adx1_out4_ep>;
  428. };
  429. };
  430. xbar_adx2_in_port: port@45 {
  431. reg = <0x45>;
  432. xbar_adx2_in_ep: endpoint {
  433. remote-endpoint = <&adx2_in_ep>;
  434. };
  435. };
  436. port@46 {
  437. reg = <0x46>;
  438. xbar_adx2_out1_ep: endpoint {
  439. remote-endpoint = <&adx2_out1_ep>;
  440. };
  441. };
  442. port@47 {
  443. reg = <0x47>;
  444. xbar_adx2_out2_ep: endpoint {
  445. remote-endpoint = <&adx2_out2_ep>;
  446. };
  447. };
  448. port@48 {
  449. reg = <0x48>;
  450. xbar_adx2_out3_ep: endpoint {
  451. remote-endpoint = <&adx2_out3_ep>;
  452. };
  453. };
  454. port@49 {
  455. reg = <0x49>;
  456. xbar_adx2_out4_ep: endpoint {
  457. remote-endpoint = <&adx2_out4_ep>;
  458. };
  459. };
  460. xbar_adx3_in_port: port@4a {
  461. reg = <0x4a>;
  462. xbar_adx3_in_ep: endpoint {
  463. remote-endpoint = <&adx3_in_ep>;
  464. };
  465. };
  466. port@4b {
  467. reg = <0x4b>;
  468. xbar_adx3_out1_ep: endpoint {
  469. remote-endpoint = <&adx3_out1_ep>;
  470. };
  471. };
  472. port@4c {
  473. reg = <0x4c>;
  474. xbar_adx3_out2_ep: endpoint {
  475. remote-endpoint = <&adx3_out2_ep>;
  476. };
  477. };
  478. port@4d {
  479. reg = <0x4d>;
  480. xbar_adx3_out3_ep: endpoint {
  481. remote-endpoint = <&adx3_out3_ep>;
  482. };
  483. };
  484. port@4e {
  485. reg = <0x4e>;
  486. xbar_adx3_out4_ep: endpoint {
  487. remote-endpoint = <&adx3_out4_ep>;
  488. };
  489. };
  490. xbar_adx4_in_port: port@4f {
  491. reg = <0x4f>;
  492. xbar_adx4_in_ep: endpoint {
  493. remote-endpoint = <&adx4_in_ep>;
  494. };
  495. };
  496. port@50 {
  497. reg = <0x50>;
  498. xbar_adx4_out1_ep: endpoint {
  499. remote-endpoint = <&adx4_out1_ep>;
  500. };
  501. };
  502. port@51 {
  503. reg = <0x51>;
  504. xbar_adx4_out2_ep: endpoint {
  505. remote-endpoint = <&adx4_out2_ep>;
  506. };
  507. };
  508. port@52 {
  509. reg = <0x52>;
  510. xbar_adx4_out3_ep: endpoint {
  511. remote-endpoint = <&adx4_out3_ep>;
  512. };
  513. };
  514. port@53 {
  515. reg = <0x53>;
  516. xbar_adx4_out4_ep: endpoint {
  517. remote-endpoint = <&adx4_out4_ep>;
  518. };
  519. };
  520. xbar_mixer_in1_port: port@54 {
  521. reg = <0x54>;
  522. xbar_mixer_in1_ep: endpoint {
  523. remote-endpoint = <&mixer_in1_ep>;
  524. };
  525. };
  526. xbar_mixer_in2_port: port@55 {
  527. reg = <0x55>;
  528. xbar_mixer_in2_ep: endpoint {
  529. remote-endpoint = <&mixer_in2_ep>;
  530. };
  531. };
  532. xbar_mixer_in3_port: port@56 {
  533. reg = <0x56>;
  534. xbar_mixer_in3_ep: endpoint {
  535. remote-endpoint = <&mixer_in3_ep>;
  536. };
  537. };
  538. xbar_mixer_in4_port: port@57 {
  539. reg = <0x57>;
  540. xbar_mixer_in4_ep: endpoint {
  541. remote-endpoint = <&mixer_in4_ep>;
  542. };
  543. };
  544. xbar_mixer_in5_port: port@58 {
  545. reg = <0x58>;
  546. xbar_mixer_in5_ep: endpoint {
  547. remote-endpoint = <&mixer_in5_ep>;
  548. };
  549. };
  550. xbar_mixer_in6_port: port@59 {
  551. reg = <0x59>;
  552. xbar_mixer_in6_ep: endpoint {
  553. remote-endpoint = <&mixer_in6_ep>;
  554. };
  555. };
  556. xbar_mixer_in7_port: port@5a {
  557. reg = <0x5a>;
  558. xbar_mixer_in7_ep: endpoint {
  559. remote-endpoint = <&mixer_in7_ep>;
  560. };
  561. };
  562. xbar_mixer_in8_port: port@5b {
  563. reg = <0x5b>;
  564. xbar_mixer_in8_ep: endpoint {
  565. remote-endpoint = <&mixer_in8_ep>;
  566. };
  567. };
  568. xbar_mixer_in9_port: port@5c {
  569. reg = <0x5c>;
  570. xbar_mixer_in9_ep: endpoint {
  571. remote-endpoint = <&mixer_in9_ep>;
  572. };
  573. };
  574. xbar_mixer_in10_port: port@5d {
  575. reg = <0x5d>;
  576. xbar_mixer_in10_ep: endpoint {
  577. remote-endpoint = <&mixer_in10_ep>;
  578. };
  579. };
  580. port@5e {
  581. reg = <0x5e>;
  582. xbar_mixer_out1_ep: endpoint {
  583. remote-endpoint = <&mixer_out1_ep>;
  584. };
  585. };
  586. port@5f {
  587. reg = <0x5f>;
  588. xbar_mixer_out2_ep: endpoint {
  589. remote-endpoint = <&mixer_out2_ep>;
  590. };
  591. };
  592. port@60 {
  593. reg = <0x60>;
  594. xbar_mixer_out3_ep: endpoint {
  595. remote-endpoint = <&mixer_out3_ep>;
  596. };
  597. };
  598. port@61 {
  599. reg = <0x61>;
  600. xbar_mixer_out4_ep: endpoint {
  601. remote-endpoint = <&mixer_out4_ep>;
  602. };
  603. };
  604. port@62 {
  605. reg = <0x62>;
  606. xbar_mixer_out5_ep: endpoint {
  607. remote-endpoint = <&mixer_out5_ep>;
  608. };
  609. };
  610. xbar_asrc_in1_port: port@63 {
  611. reg = <0x63>;
  612. xbar_asrc_in1_ep: endpoint {
  613. remote-endpoint = <&asrc_in1_ep>;
  614. };
  615. };
  616. port@64 {
  617. reg = <0x64>;
  618. xbar_asrc_out1_ep: endpoint {
  619. remote-endpoint = <&asrc_out1_ep>;
  620. };
  621. };
  622. xbar_asrc_in2_port: port@65 {
  623. reg = <0x65>;
  624. xbar_asrc_in2_ep: endpoint {
  625. remote-endpoint = <&asrc_in2_ep>;
  626. };
  627. };
  628. port@66 {
  629. reg = <0x66>;
  630. xbar_asrc_out2_ep: endpoint {
  631. remote-endpoint = <&asrc_out2_ep>;
  632. };
  633. };
  634. xbar_asrc_in3_port: port@67 {
  635. reg = <0x67>;
  636. xbar_asrc_in3_ep: endpoint {
  637. remote-endpoint = <&asrc_in3_ep>;
  638. };
  639. };
  640. port@68 {
  641. reg = <0x68>;
  642. xbar_asrc_out3_ep: endpoint {
  643. remote-endpoint = <&asrc_out3_ep>;
  644. };
  645. };
  646. xbar_asrc_in4_port: port@69 {
  647. reg = <0x69>;
  648. xbar_asrc_in4_ep: endpoint {
  649. remote-endpoint = <&asrc_in4_ep>;
  650. };
  651. };
  652. port@6a {
  653. reg = <0x6a>;
  654. xbar_asrc_out4_ep: endpoint {
  655. remote-endpoint = <&asrc_out4_ep>;
  656. };
  657. };
  658. xbar_asrc_in5_port: port@6b {
  659. reg = <0x6b>;
  660. xbar_asrc_in5_ep: endpoint {
  661. remote-endpoint = <&asrc_in5_ep>;
  662. };
  663. };
  664. port@6c {
  665. reg = <0x6c>;
  666. xbar_asrc_out5_ep: endpoint {
  667. remote-endpoint = <&asrc_out5_ep>;
  668. };
  669. };
  670. xbar_asrc_in6_port: port@6d {
  671. reg = <0x6d>;
  672. xbar_asrc_in6_ep: endpoint {
  673. remote-endpoint = <&asrc_in6_ep>;
  674. };
  675. };
  676. port@6e {
  677. reg = <0x6e>;
  678. xbar_asrc_out6_ep: endpoint {
  679. remote-endpoint = <&asrc_out6_ep>;
  680. };
  681. };
  682. xbar_asrc_in7_port: port@6f {
  683. reg = <0x6f>;
  684. xbar_asrc_in7_ep: endpoint {
  685. remote-endpoint = <&asrc_in7_ep>;
  686. };
  687. };
  688. xbar_ope1_in_port: port@70 {
  689. reg = <0x70>;
  690. xbar_ope1_in_ep: endpoint {
  691. remote-endpoint = <&ope1_cif_in_ep>;
  692. };
  693. };
  694. port@71 {
  695. reg = <0x71>;
  696. xbar_ope1_out_ep: endpoint {
  697. remote-endpoint = <&ope1_cif_out_ep>;
  698. };
  699. };
  700. };
  701. admaif@290f000 {
  702. status = "okay";
  703. ports {
  704. #address-cells = <1>;
  705. #size-cells = <0>;
  706. admaif0_port: port@0 {
  707. reg = <0x0>;
  708. admaif0_ep: endpoint {
  709. remote-endpoint = <&xbar_admaif0_ep>;
  710. };
  711. };
  712. admaif1_port: port@1 {
  713. reg = <0x1>;
  714. admaif1_ep: endpoint {
  715. remote-endpoint = <&xbar_admaif1_ep>;
  716. };
  717. };
  718. admaif2_port: port@2 {
  719. reg = <0x2>;
  720. admaif2_ep: endpoint {
  721. remote-endpoint = <&xbar_admaif2_ep>;
  722. };
  723. };
  724. admaif3_port: port@3 {
  725. reg = <0x3>;
  726. admaif3_ep: endpoint {
  727. remote-endpoint = <&xbar_admaif3_ep>;
  728. };
  729. };
  730. admaif4_port: port@4 {
  731. reg = <0x4>;
  732. admaif4_ep: endpoint {
  733. remote-endpoint = <&xbar_admaif4_ep>;
  734. };
  735. };
  736. admaif5_port: port@5 {
  737. reg = <0x5>;
  738. admaif5_ep: endpoint {
  739. remote-endpoint = <&xbar_admaif5_ep>;
  740. };
  741. };
  742. admaif6_port: port@6 {
  743. reg = <0x6>;
  744. admaif6_ep: endpoint {
  745. remote-endpoint = <&xbar_admaif6_ep>;
  746. };
  747. };
  748. admaif7_port: port@7 {
  749. reg = <0x7>;
  750. admaif7_ep: endpoint {
  751. remote-endpoint = <&xbar_admaif7_ep>;
  752. };
  753. };
  754. admaif8_port: port@8 {
  755. reg = <0x8>;
  756. admaif8_ep: endpoint {
  757. remote-endpoint = <&xbar_admaif8_ep>;
  758. };
  759. };
  760. admaif9_port: port@9 {
  761. reg = <0x9>;
  762. admaif9_ep: endpoint {
  763. remote-endpoint = <&xbar_admaif9_ep>;
  764. };
  765. };
  766. admaif10_port: port@a {
  767. reg = <0xa>;
  768. admaif10_ep: endpoint {
  769. remote-endpoint = <&xbar_admaif10_ep>;
  770. };
  771. };
  772. admaif11_port: port@b {
  773. reg = <0xb>;
  774. admaif11_ep: endpoint {
  775. remote-endpoint = <&xbar_admaif11_ep>;
  776. };
  777. };
  778. admaif12_port: port@c {
  779. reg = <0xc>;
  780. admaif12_ep: endpoint {
  781. remote-endpoint = <&xbar_admaif12_ep>;
  782. };
  783. };
  784. admaif13_port: port@d {
  785. reg = <0xd>;
  786. admaif13_ep: endpoint {
  787. remote-endpoint = <&xbar_admaif13_ep>;
  788. };
  789. };
  790. admaif14_port: port@e {
  791. reg = <0xe>;
  792. admaif14_ep: endpoint {
  793. remote-endpoint = <&xbar_admaif14_ep>;
  794. };
  795. };
  796. admaif15_port: port@f {
  797. reg = <0xf>;
  798. admaif15_ep: endpoint {
  799. remote-endpoint = <&xbar_admaif15_ep>;
  800. };
  801. };
  802. admaif16_port: port@10 {
  803. reg = <0x10>;
  804. admaif16_ep: endpoint {
  805. remote-endpoint = <&xbar_admaif16_ep>;
  806. };
  807. };
  808. admaif17_port: port@11 {
  809. reg = <0x11>;
  810. admaif17_ep: endpoint {
  811. remote-endpoint = <&xbar_admaif17_ep>;
  812. };
  813. };
  814. admaif18_port: port@12 {
  815. reg = <0x12>;
  816. admaif18_ep: endpoint {
  817. remote-endpoint = <&xbar_admaif18_ep>;
  818. };
  819. };
  820. admaif19_port: port@13 {
  821. reg = <0x13>;
  822. admaif19_ep: endpoint {
  823. remote-endpoint = <&xbar_admaif19_ep>;
  824. };
  825. };
  826. };
  827. };
  828. i2s@2901000 {
  829. status = "okay";
  830. ports {
  831. #address-cells = <1>;
  832. #size-cells = <0>;
  833. port@0 {
  834. reg = <0>;
  835. i2s1_cif_ep: endpoint {
  836. remote-endpoint = <&xbar_i2s1_ep>;
  837. };
  838. };
  839. i2s1_port: port@1 {
  840. reg = <1>;
  841. i2s1_dap_ep: endpoint {
  842. dai-format = "i2s";
  843. /* Placeholder for external Codec */
  844. };
  845. };
  846. };
  847. };
  848. i2s@2901100 {
  849. status = "okay";
  850. ports {
  851. #address-cells = <1>;
  852. #size-cells = <0>;
  853. port@0 {
  854. reg = <0>;
  855. i2s2_cif_ep: endpoint {
  856. remote-endpoint = <&xbar_i2s2_ep>;
  857. };
  858. };
  859. i2s2_port: port@1 {
  860. reg = <1>;
  861. i2s2_dap_ep: endpoint {
  862. dai-format = "i2s";
  863. /* Placeholder for external Codec */
  864. };
  865. };
  866. };
  867. };
  868. i2s@2901200 {
  869. status = "okay";
  870. ports {
  871. #address-cells = <1>;
  872. #size-cells = <0>;
  873. port@0 {
  874. reg = <0>;
  875. i2s3_cif_ep: endpoint {
  876. remote-endpoint = <&xbar_i2s3_ep>;
  877. };
  878. };
  879. i2s3_port: port@1 {
  880. reg = <1>;
  881. i2s3_dap_ep: endpoint {
  882. dai-format = "i2s";
  883. /* Placeholder for external Codec */
  884. };
  885. };
  886. };
  887. };
  888. i2s@2901300 {
  889. status = "okay";
  890. ports {
  891. #address-cells = <1>;
  892. #size-cells = <0>;
  893. port@0 {
  894. reg = <0>;
  895. i2s4_cif_ep: endpoint {
  896. remote-endpoint = <&xbar_i2s4_ep>;
  897. };
  898. };
  899. i2s4_port: port@1 {
  900. reg = <1>;
  901. i2s4_dap_ep: endpoint {
  902. dai-format = "i2s";
  903. /* Placeholder for external Codec */
  904. };
  905. };
  906. };
  907. };
  908. i2s@2901400 {
  909. status = "okay";
  910. ports {
  911. #address-cells = <1>;
  912. #size-cells = <0>;
  913. port@0 {
  914. reg = <0>;
  915. i2s5_cif_ep: endpoint {
  916. remote-endpoint = <&xbar_i2s5_ep>;
  917. };
  918. };
  919. i2s5_port: port@1 {
  920. reg = <1>;
  921. i2s5_dap_ep: endpoint {
  922. dai-format = "i2s";
  923. /* Placeholder for external Codec */
  924. };
  925. };
  926. };
  927. };
  928. i2s@2901500 {
  929. status = "okay";
  930. ports {
  931. #address-cells = <1>;
  932. #size-cells = <0>;
  933. port@0 {
  934. reg = <0>;
  935. i2s6_cif_ep: endpoint {
  936. remote-endpoint = <&xbar_i2s6_ep>;
  937. };
  938. };
  939. i2s6_port: port@1 {
  940. reg = <1>;
  941. i2s6_dap_ep: endpoint {
  942. dai-format = "i2s";
  943. /* Placeholder for external Codec */
  944. };
  945. };
  946. };
  947. };
  948. dmic@2904000 {
  949. status = "okay";
  950. ports {
  951. #address-cells = <1>;
  952. #size-cells = <0>;
  953. port@0 {
  954. reg = <0>;
  955. dmic1_cif_ep: endpoint {
  956. remote-endpoint = <&xbar_dmic1_ep>;
  957. };
  958. };
  959. dmic1_port: port@1 {
  960. reg = <1>;
  961. dmic1_dap_ep: endpoint {
  962. /* Place holder for external Codec */
  963. };
  964. };
  965. };
  966. };
  967. dmic@2904100 {
  968. status = "okay";
  969. ports {
  970. #address-cells = <1>;
  971. #size-cells = <0>;
  972. port@0 {
  973. reg = <0>;
  974. dmic2_cif_ep: endpoint {
  975. remote-endpoint = <&xbar_dmic2_ep>;
  976. };
  977. };
  978. dmic2_port: port@1 {
  979. reg = <1>;
  980. dmic2_dap_ep: endpoint {
  981. /* Place holder for external Codec */
  982. };
  983. };
  984. };
  985. };
  986. dmic@2904200 {
  987. status = "okay";
  988. ports {
  989. #address-cells = <1>;
  990. #size-cells = <0>;
  991. port@0 {
  992. reg = <0>;
  993. dmic3_cif_ep: endpoint {
  994. remote-endpoint = <&xbar_dmic3_ep>;
  995. };
  996. };
  997. dmic3_port: port@1 {
  998. reg = <1>;
  999. dmic3_dap_ep: endpoint {
  1000. /* Place holder for external Codec */
  1001. };
  1002. };
  1003. };
  1004. };
  1005. dspk@2905000 {
  1006. status = "okay";
  1007. ports {
  1008. #address-cells = <1>;
  1009. #size-cells = <0>;
  1010. port@0 {
  1011. reg = <0>;
  1012. dspk1_cif_ep: endpoint {
  1013. remote-endpoint = <&xbar_dspk1_ep>;
  1014. };
  1015. };
  1016. dspk1_port: port@1 {
  1017. reg = <1>;
  1018. dspk1_dap_ep: endpoint {
  1019. /* Place holder for external Codec */
  1020. };
  1021. };
  1022. };
  1023. };
  1024. dspk@2905100 {
  1025. status = "okay";
  1026. ports {
  1027. #address-cells = <1>;
  1028. #size-cells = <0>;
  1029. port@0 {
  1030. reg = <0>;
  1031. dspk2_cif_ep: endpoint {
  1032. remote-endpoint = <&xbar_dspk2_ep>;
  1033. };
  1034. };
  1035. dspk2_port: port@1 {
  1036. reg = <1>;
  1037. dspk2_dap_ep: endpoint {
  1038. /* Place holder for external Codec */
  1039. };
  1040. };
  1041. };
  1042. };
  1043. sfc@2902000 {
  1044. status = "okay";
  1045. ports {
  1046. #address-cells = <1>;
  1047. #size-cells = <0>;
  1048. port@0 {
  1049. reg = <0>;
  1050. sfc1_cif_in_ep: endpoint {
  1051. remote-endpoint = <&xbar_sfc1_in_ep>;
  1052. convert-rate = <44100>;
  1053. };
  1054. };
  1055. sfc1_out_port: port@1 {
  1056. reg = <1>;
  1057. sfc1_cif_out_ep: endpoint {
  1058. remote-endpoint = <&xbar_sfc1_out_ep>;
  1059. convert-rate = <48000>;
  1060. };
  1061. };
  1062. };
  1063. };
  1064. sfc@2902200 {
  1065. status = "okay";
  1066. ports {
  1067. #address-cells = <1>;
  1068. #size-cells = <0>;
  1069. port@0 {
  1070. reg = <0>;
  1071. sfc2_cif_in_ep: endpoint {
  1072. remote-endpoint = <&xbar_sfc2_in_ep>;
  1073. };
  1074. };
  1075. sfc2_out_port: port@1 {
  1076. reg = <1>;
  1077. sfc2_cif_out_ep: endpoint {
  1078. remote-endpoint = <&xbar_sfc2_out_ep>;
  1079. };
  1080. };
  1081. };
  1082. };
  1083. sfc@2902400 {
  1084. status = "okay";
  1085. ports {
  1086. #address-cells = <1>;
  1087. #size-cells = <0>;
  1088. port@0 {
  1089. reg = <0>;
  1090. sfc3_cif_in_ep: endpoint {
  1091. remote-endpoint = <&xbar_sfc3_in_ep>;
  1092. };
  1093. };
  1094. sfc3_out_port: port@1 {
  1095. reg = <1>;
  1096. sfc3_cif_out_ep: endpoint {
  1097. remote-endpoint = <&xbar_sfc3_out_ep>;
  1098. };
  1099. };
  1100. };
  1101. };
  1102. sfc@2902600 {
  1103. status = "okay";
  1104. ports {
  1105. #address-cells = <1>;
  1106. #size-cells = <0>;
  1107. port@0 {
  1108. reg = <0>;
  1109. sfc4_cif_in_ep: endpoint {
  1110. remote-endpoint = <&xbar_sfc4_in_ep>;
  1111. };
  1112. };
  1113. sfc4_out_port: port@1 {
  1114. reg = <1>;
  1115. sfc4_cif_out_ep: endpoint {
  1116. remote-endpoint = <&xbar_sfc4_out_ep>;
  1117. };
  1118. };
  1119. };
  1120. };
  1121. mvc@290a000 {
  1122. status = "okay";
  1123. ports {
  1124. #address-cells = <1>;
  1125. #size-cells = <0>;
  1126. port@0 {
  1127. reg = <0>;
  1128. mvc1_cif_in_ep: endpoint {
  1129. remote-endpoint = <&xbar_mvc1_in_ep>;
  1130. };
  1131. };
  1132. mvc1_out_port: port@1 {
  1133. reg = <1>;
  1134. mvc1_cif_out_ep: endpoint {
  1135. remote-endpoint = <&xbar_mvc1_out_ep>;
  1136. };
  1137. };
  1138. };
  1139. };
  1140. mvc@290a200 {
  1141. status = "okay";
  1142. ports {
  1143. #address-cells = <1>;
  1144. #size-cells = <0>;
  1145. port@0 {
  1146. reg = <0>;
  1147. mvc2_cif_in_ep: endpoint {
  1148. remote-endpoint = <&xbar_mvc2_in_ep>;
  1149. };
  1150. };
  1151. mvc2_out_port: port@1 {
  1152. reg = <1>;
  1153. mvc2_cif_out_ep: endpoint {
  1154. remote-endpoint = <&xbar_mvc2_out_ep>;
  1155. };
  1156. };
  1157. };
  1158. };
  1159. amx@2903000 {
  1160. status = "okay";
  1161. ports {
  1162. #address-cells = <1>;
  1163. #size-cells = <0>;
  1164. port@0 {
  1165. reg = <0>;
  1166. amx1_in1_ep: endpoint {
  1167. remote-endpoint = <&xbar_amx1_in1_ep>;
  1168. };
  1169. };
  1170. port@1 {
  1171. reg = <1>;
  1172. amx1_in2_ep: endpoint {
  1173. remote-endpoint = <&xbar_amx1_in2_ep>;
  1174. };
  1175. };
  1176. port@2 {
  1177. reg = <2>;
  1178. amx1_in3_ep: endpoint {
  1179. remote-endpoint = <&xbar_amx1_in3_ep>;
  1180. };
  1181. };
  1182. port@3 {
  1183. reg = <3>;
  1184. amx1_in4_ep: endpoint {
  1185. remote-endpoint = <&xbar_amx1_in4_ep>;
  1186. };
  1187. };
  1188. amx1_out_port: port@4 {
  1189. reg = <4>;
  1190. amx1_out_ep: endpoint {
  1191. remote-endpoint = <&xbar_amx1_out_ep>;
  1192. };
  1193. };
  1194. };
  1195. };
  1196. amx@2903100 {
  1197. status = "okay";
  1198. ports {
  1199. #address-cells = <1>;
  1200. #size-cells = <0>;
  1201. port@0 {
  1202. reg = <0>;
  1203. amx2_in1_ep: endpoint {
  1204. remote-endpoint = <&xbar_amx2_in1_ep>;
  1205. };
  1206. };
  1207. port@1 {
  1208. reg = <1>;
  1209. amx2_in2_ep: endpoint {
  1210. remote-endpoint = <&xbar_amx2_in2_ep>;
  1211. };
  1212. };
  1213. amx2_in3_port: port@2 {
  1214. reg = <2>;
  1215. amx2_in3_ep: endpoint {
  1216. remote-endpoint = <&xbar_amx2_in3_ep>;
  1217. };
  1218. };
  1219. amx2_in4_port: port@3 {
  1220. reg = <3>;
  1221. amx2_in4_ep: endpoint {
  1222. remote-endpoint = <&xbar_amx2_in4_ep>;
  1223. };
  1224. };
  1225. amx2_out_port: port@4 {
  1226. reg = <4>;
  1227. amx2_out_ep: endpoint {
  1228. remote-endpoint = <&xbar_amx2_out_ep>;
  1229. };
  1230. };
  1231. };
  1232. };
  1233. amx@2903200 {
  1234. status = "okay";
  1235. ports {
  1236. #address-cells = <1>;
  1237. #size-cells = <0>;
  1238. port@0 {
  1239. reg = <0>;
  1240. amx3_in1_ep: endpoint {
  1241. remote-endpoint = <&xbar_amx3_in1_ep>;
  1242. };
  1243. };
  1244. port@1 {
  1245. reg = <1>;
  1246. amx3_in2_ep: endpoint {
  1247. remote-endpoint = <&xbar_amx3_in2_ep>;
  1248. };
  1249. };
  1250. port@2 {
  1251. reg = <2>;
  1252. amx3_in3_ep: endpoint {
  1253. remote-endpoint = <&xbar_amx3_in3_ep>;
  1254. };
  1255. };
  1256. port@3 {
  1257. reg = <3>;
  1258. amx3_in4_ep: endpoint {
  1259. remote-endpoint = <&xbar_amx3_in4_ep>;
  1260. };
  1261. };
  1262. amx3_out_port: port@4 {
  1263. reg = <4>;
  1264. amx3_out_ep: endpoint {
  1265. remote-endpoint = <&xbar_amx3_out_ep>;
  1266. };
  1267. };
  1268. };
  1269. };
  1270. amx@2903300 {
  1271. status = "okay";
  1272. ports {
  1273. #address-cells = <1>;
  1274. #size-cells = <0>;
  1275. port@0 {
  1276. reg = <0>;
  1277. amx4_in1_ep: endpoint {
  1278. remote-endpoint = <&xbar_amx4_in1_ep>;
  1279. };
  1280. };
  1281. port@1 {
  1282. reg = <1>;
  1283. amx4_in2_ep: endpoint {
  1284. remote-endpoint = <&xbar_amx4_in2_ep>;
  1285. };
  1286. };
  1287. port@2 {
  1288. reg = <2>;
  1289. amx4_in3_ep: endpoint {
  1290. remote-endpoint = <&xbar_amx4_in3_ep>;
  1291. };
  1292. };
  1293. port@3 {
  1294. reg = <3>;
  1295. amx4_in4_ep: endpoint {
  1296. remote-endpoint = <&xbar_amx4_in4_ep>;
  1297. };
  1298. };
  1299. amx4_out_port: port@4 {
  1300. reg = <4>;
  1301. amx4_out_ep: endpoint {
  1302. remote-endpoint = <&xbar_amx4_out_ep>;
  1303. };
  1304. };
  1305. };
  1306. };
  1307. adx@2903800 {
  1308. status = "okay";
  1309. ports {
  1310. #address-cells = <1>;
  1311. #size-cells = <0>;
  1312. port@0 {
  1313. reg = <0>;
  1314. adx1_in_ep: endpoint {
  1315. remote-endpoint = <&xbar_adx1_in_ep>;
  1316. };
  1317. };
  1318. adx1_out1_port: port@1 {
  1319. reg = <1>;
  1320. adx1_out1_ep: endpoint {
  1321. remote-endpoint = <&xbar_adx1_out1_ep>;
  1322. };
  1323. };
  1324. adx1_out2_port: port@2 {
  1325. reg = <2>;
  1326. adx1_out2_ep: endpoint {
  1327. remote-endpoint = <&xbar_adx1_out2_ep>;
  1328. };
  1329. };
  1330. adx1_out3_port: port@3 {
  1331. reg = <3>;
  1332. adx1_out3_ep: endpoint {
  1333. remote-endpoint = <&xbar_adx1_out3_ep>;
  1334. };
  1335. };
  1336. adx1_out4_port: port@4 {
  1337. reg = <4>;
  1338. adx1_out4_ep: endpoint {
  1339. remote-endpoint = <&xbar_adx1_out4_ep>;
  1340. };
  1341. };
  1342. };
  1343. };
  1344. adx@2903900 {
  1345. status = "okay";
  1346. ports {
  1347. #address-cells = <1>;
  1348. #size-cells = <0>;
  1349. port@0 {
  1350. reg = <0>;
  1351. adx2_in_ep: endpoint {
  1352. remote-endpoint = <&xbar_adx2_in_ep>;
  1353. };
  1354. };
  1355. adx2_out1_port: port@1 {
  1356. reg = <1>;
  1357. adx2_out1_ep: endpoint {
  1358. remote-endpoint = <&xbar_adx2_out1_ep>;
  1359. };
  1360. };
  1361. adx2_out2_port: port@2 {
  1362. reg = <2>;
  1363. adx2_out2_ep: endpoint {
  1364. remote-endpoint = <&xbar_adx2_out2_ep>;
  1365. };
  1366. };
  1367. adx2_out3_port: port@3 {
  1368. reg = <3>;
  1369. adx2_out3_ep: endpoint {
  1370. remote-endpoint = <&xbar_adx2_out3_ep>;
  1371. };
  1372. };
  1373. adx2_out4_port: port@4 {
  1374. reg = <4>;
  1375. adx2_out4_ep: endpoint {
  1376. remote-endpoint = <&xbar_adx2_out4_ep>;
  1377. };
  1378. };
  1379. };
  1380. };
  1381. adx@2903a00 {
  1382. status = "okay";
  1383. ports {
  1384. #address-cells = <1>;
  1385. #size-cells = <0>;
  1386. port@0 {
  1387. reg = <0>;
  1388. adx3_in_ep: endpoint {
  1389. remote-endpoint = <&xbar_adx3_in_ep>;
  1390. };
  1391. };
  1392. adx3_out1_port: port@1 {
  1393. reg = <1>;
  1394. adx3_out1_ep: endpoint {
  1395. remote-endpoint = <&xbar_adx3_out1_ep>;
  1396. };
  1397. };
  1398. adx3_out2_port: port@2 {
  1399. reg = <2>;
  1400. adx3_out2_ep: endpoint {
  1401. remote-endpoint = <&xbar_adx3_out2_ep>;
  1402. };
  1403. };
  1404. adx3_out3_port: port@3 {
  1405. reg = <3>;
  1406. adx3_out3_ep: endpoint {
  1407. remote-endpoint = <&xbar_adx3_out3_ep>;
  1408. };
  1409. };
  1410. adx3_out4_port: port@4 {
  1411. reg = <4>;
  1412. adx3_out4_ep: endpoint {
  1413. remote-endpoint = <&xbar_adx3_out4_ep>;
  1414. };
  1415. };
  1416. };
  1417. };
  1418. adx@2903b00 {
  1419. status = "okay";
  1420. ports {
  1421. #address-cells = <1>;
  1422. #size-cells = <0>;
  1423. port@0 {
  1424. reg = <0>;
  1425. adx4_in_ep: endpoint {
  1426. remote-endpoint = <&xbar_adx4_in_ep>;
  1427. };
  1428. };
  1429. adx4_out1_port: port@1 {
  1430. reg = <1>;
  1431. adx4_out1_ep: endpoint {
  1432. remote-endpoint = <&xbar_adx4_out1_ep>;
  1433. };
  1434. };
  1435. adx4_out2_port: port@2 {
  1436. reg = <2>;
  1437. adx4_out2_ep: endpoint {
  1438. remote-endpoint = <&xbar_adx4_out2_ep>;
  1439. };
  1440. };
  1441. adx4_out3_port: port@3 {
  1442. reg = <3>;
  1443. adx4_out3_ep: endpoint {
  1444. remote-endpoint = <&xbar_adx4_out3_ep>;
  1445. };
  1446. };
  1447. adx4_out4_port: port@4 {
  1448. reg = <4>;
  1449. adx4_out4_ep: endpoint {
  1450. remote-endpoint = <&xbar_adx4_out4_ep>;
  1451. };
  1452. };
  1453. };
  1454. };
  1455. processing-engine@2908000 {
  1456. status = "okay";
  1457. ports {
  1458. #address-cells = <1>;
  1459. #size-cells = <0>;
  1460. port@0 {
  1461. reg = <0x0>;
  1462. ope1_cif_in_ep: endpoint {
  1463. remote-endpoint = <&xbar_ope1_in_ep>;
  1464. };
  1465. };
  1466. ope1_out_port: port@1 {
  1467. reg = <0x1>;
  1468. ope1_cif_out_ep: endpoint {
  1469. remote-endpoint = <&xbar_ope1_out_ep>;
  1470. };
  1471. };
  1472. };
  1473. };
  1474. amixer@290bb00 {
  1475. status = "okay";
  1476. ports {
  1477. #address-cells = <1>;
  1478. #size-cells = <0>;
  1479. port@0 {
  1480. reg = <0x0>;
  1481. mixer_in1_ep: endpoint {
  1482. remote-endpoint = <&xbar_mixer_in1_ep>;
  1483. };
  1484. };
  1485. port@1 {
  1486. reg = <0x1>;
  1487. mixer_in2_ep: endpoint {
  1488. remote-endpoint = <&xbar_mixer_in2_ep>;
  1489. };
  1490. };
  1491. port@2 {
  1492. reg = <0x2>;
  1493. mixer_in3_ep: endpoint {
  1494. remote-endpoint = <&xbar_mixer_in3_ep>;
  1495. };
  1496. };
  1497. port@3 {
  1498. reg = <0x3>;
  1499. mixer_in4_ep: endpoint {
  1500. remote-endpoint = <&xbar_mixer_in4_ep>;
  1501. };
  1502. };
  1503. port@4 {
  1504. reg = <0x4>;
  1505. mixer_in5_ep: endpoint {
  1506. remote-endpoint = <&xbar_mixer_in5_ep>;
  1507. };
  1508. };
  1509. port@5 {
  1510. reg = <0x5>;
  1511. mixer_in6_ep: endpoint {
  1512. remote-endpoint = <&xbar_mixer_in6_ep>;
  1513. };
  1514. };
  1515. port@6 {
  1516. reg = <0x6>;
  1517. mixer_in7_ep: endpoint {
  1518. remote-endpoint = <&xbar_mixer_in7_ep>;
  1519. };
  1520. };
  1521. port@7 {
  1522. reg = <0x7>;
  1523. mixer_in8_ep: endpoint {
  1524. remote-endpoint = <&xbar_mixer_in8_ep>;
  1525. };
  1526. };
  1527. port@8 {
  1528. reg = <0x8>;
  1529. mixer_in9_ep: endpoint {
  1530. remote-endpoint = <&xbar_mixer_in9_ep>;
  1531. };
  1532. };
  1533. port@9 {
  1534. reg = <0x9>;
  1535. mixer_in10_ep: endpoint {
  1536. remote-endpoint = <&xbar_mixer_in10_ep>;
  1537. };
  1538. };
  1539. mixer_out1_port: port@a {
  1540. reg = <0xa>;
  1541. mixer_out1_ep: endpoint {
  1542. remote-endpoint = <&xbar_mixer_out1_ep>;
  1543. };
  1544. };
  1545. mixer_out2_port: port@b {
  1546. reg = <0xb>;
  1547. mixer_out2_ep: endpoint {
  1548. remote-endpoint = <&xbar_mixer_out2_ep>;
  1549. };
  1550. };
  1551. mixer_out3_port: port@c {
  1552. reg = <0xc>;
  1553. mixer_out3_ep: endpoint {
  1554. remote-endpoint = <&xbar_mixer_out3_ep>;
  1555. };
  1556. };
  1557. mixer_out4_port: port@d {
  1558. reg = <0xd>;
  1559. mixer_out4_ep: endpoint {
  1560. remote-endpoint = <&xbar_mixer_out4_ep>;
  1561. };
  1562. };
  1563. mixer_out5_port: port@e {
  1564. reg = <0xe>;
  1565. mixer_out5_ep: endpoint {
  1566. remote-endpoint = <&xbar_mixer_out5_ep>;
  1567. };
  1568. };
  1569. };
  1570. };
  1571. asrc@2910000 {
  1572. status = "okay";
  1573. ports {
  1574. #address-cells = <1>;
  1575. #size-cells = <0>;
  1576. port@0 {
  1577. reg = <0x0>;
  1578. asrc_in1_ep: endpoint {
  1579. remote-endpoint = <&xbar_asrc_in1_ep>;
  1580. };
  1581. };
  1582. port@1 {
  1583. reg = <0x1>;
  1584. asrc_in2_ep: endpoint {
  1585. remote-endpoint = <&xbar_asrc_in2_ep>;
  1586. };
  1587. };
  1588. port@2 {
  1589. reg = <0x2>;
  1590. asrc_in3_ep: endpoint {
  1591. remote-endpoint = <&xbar_asrc_in3_ep>;
  1592. };
  1593. };
  1594. port@3 {
  1595. reg = <0x3>;
  1596. asrc_in4_ep: endpoint {
  1597. remote-endpoint = <&xbar_asrc_in4_ep>;
  1598. };
  1599. };
  1600. port@4 {
  1601. reg = <0x4>;
  1602. asrc_in5_ep: endpoint {
  1603. remote-endpoint = <&xbar_asrc_in5_ep>;
  1604. };
  1605. };
  1606. port@5 {
  1607. reg = <0x5>;
  1608. asrc_in6_ep: endpoint {
  1609. remote-endpoint = <&xbar_asrc_in6_ep>;
  1610. };
  1611. };
  1612. port@6 {
  1613. reg = <0x6>;
  1614. asrc_in7_ep: endpoint {
  1615. remote-endpoint = <&xbar_asrc_in7_ep>;
  1616. };
  1617. };
  1618. asrc_out1_port: port@7 {
  1619. reg = <0x7>;
  1620. asrc_out1_ep: endpoint {
  1621. remote-endpoint = <&xbar_asrc_out1_ep>;
  1622. };
  1623. };
  1624. asrc_out2_port: port@8 {
  1625. reg = <0x8>;
  1626. asrc_out2_ep: endpoint {
  1627. remote-endpoint = <&xbar_asrc_out2_ep>;
  1628. };
  1629. };
  1630. asrc_out3_port: port@9 {
  1631. reg = <0x9>;
  1632. asrc_out3_ep: endpoint {
  1633. remote-endpoint = <&xbar_asrc_out3_ep>;
  1634. };
  1635. };
  1636. asrc_out4_port: port@a {
  1637. reg = <0xa>;
  1638. asrc_out4_ep: endpoint {
  1639. remote-endpoint = <&xbar_asrc_out4_ep>;
  1640. };
  1641. };
  1642. asrc_out5_port: port@b {
  1643. reg = <0xb>;
  1644. asrc_out5_ep: endpoint {
  1645. remote-endpoint = <&xbar_asrc_out5_ep>;
  1646. };
  1647. };
  1648. asrc_out6_port: port@c {
  1649. reg = <0xc>;
  1650. asrc_out6_ep: endpoint {
  1651. remote-endpoint = <&xbar_asrc_out6_ep>;
  1652. };
  1653. };
  1654. };
  1655. };
  1656. };
  1657. };
  1658. i2c@3160000 {
  1659. power-monitor@42 {
  1660. compatible = "ti,ina3221";
  1661. reg = <0x42>;
  1662. #address-cells = <1>;
  1663. #size-cells = <0>;
  1664. input@0 {
  1665. reg = <0x0>;
  1666. label = "VDD_MUX";
  1667. shunt-resistor-micro-ohms = <20000>;
  1668. };
  1669. input@1 {
  1670. reg = <0x1>;
  1671. label = "VDD_5V0_IO_SYS";
  1672. shunt-resistor-micro-ohms = <5000>;
  1673. };
  1674. input@2 {
  1675. reg = <0x2>;
  1676. label = "VDD_3V3_SYS";
  1677. shunt-resistor-micro-ohms = <10000>;
  1678. };
  1679. };
  1680. power-monitor@43 {
  1681. compatible = "ti,ina3221";
  1682. reg = <0x43>;
  1683. #address-cells = <1>;
  1684. #size-cells = <0>;
  1685. input@0 {
  1686. reg = <0x0>;
  1687. label = "VDD_3V3_IO_SLP";
  1688. shunt-resistor-micro-ohms = <10000>;
  1689. };
  1690. input@1 {
  1691. reg = <0x1>;
  1692. label = "VDD_1V8_IO";
  1693. shunt-resistor-micro-ohms = <10000>;
  1694. };
  1695. input@2 {
  1696. reg = <0x2>;
  1697. label = "VDD_M2_IN";
  1698. shunt-resistor-micro-ohms = <10000>;
  1699. };
  1700. };
  1701. exp1: gpio@74 {
  1702. compatible = "ti,tca9539";
  1703. reg = <0x74>;
  1704. interrupt-parent = <&gpio>;
  1705. interrupts = <TEGRA186_MAIN_GPIO(Y, 0)
  1706. GPIO_ACTIVE_LOW>;
  1707. #gpio-cells = <2>;
  1708. gpio-controller;
  1709. vcc-supply = <&vdd_3v3_sys>;
  1710. };
  1711. exp2: gpio@77 {
  1712. compatible = "ti,tca9539";
  1713. reg = <0x77>;
  1714. interrupt-parent = <&gpio>;
  1715. interrupts = <TEGRA186_MAIN_GPIO(Y, 6)
  1716. GPIO_ACTIVE_LOW>;
  1717. #gpio-cells = <2>;
  1718. gpio-controller;
  1719. vcc-supply = <&vdd_1v8>;
  1720. };
  1721. };
  1722. /* SDMMC1 (SD/MMC) */
  1723. mmc@3400000 {
  1724. status = "okay";
  1725. vmmc-supply = <&vdd_sd>;
  1726. };
  1727. hda@3510000 {
  1728. nvidia,model = "NVIDIA Jetson TX2 HDA";
  1729. status = "okay";
  1730. };
  1731. padctl@3520000 {
  1732. status = "okay";
  1733. avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
  1734. avdd-usb-supply = <&vdd_3v3_sys>;
  1735. vclamp-usb-supply = <&vdd_1v8>;
  1736. vddio-hsic-supply = <&gnd>;
  1737. pads {
  1738. usb2 {
  1739. status = "okay";
  1740. lanes {
  1741. micro_b: usb2-0 {
  1742. nvidia,function = "xusb";
  1743. status = "okay";
  1744. };
  1745. usb2-1 {
  1746. nvidia,function = "xusb";
  1747. status = "okay";
  1748. };
  1749. usb2-2 {
  1750. nvidia,function = "xusb";
  1751. status = "okay";
  1752. };
  1753. };
  1754. };
  1755. usb3 {
  1756. status = "okay";
  1757. lanes {
  1758. usb3-0 {
  1759. nvidia,function = "xusb";
  1760. status = "okay";
  1761. };
  1762. usb3-1 {
  1763. nvidia,function = "xusb";
  1764. status = "okay";
  1765. };
  1766. usb3-2 {
  1767. nvidia,function = "xusb";
  1768. status = "okay";
  1769. };
  1770. };
  1771. };
  1772. };
  1773. ports {
  1774. usb2-0 {
  1775. status = "okay";
  1776. mode = "otg";
  1777. vbus-supply = <&vdd_usb0>;
  1778. usb-role-switch;
  1779. connector {
  1780. compatible = "gpio-usb-b-connector",
  1781. "usb-b-connector";
  1782. label = "micro-USB";
  1783. type = "micro";
  1784. vbus-gpios = <&gpio
  1785. TEGRA186_MAIN_GPIO(X, 7)
  1786. GPIO_ACTIVE_LOW>;
  1787. id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
  1788. };
  1789. };
  1790. usb2-1 {
  1791. status = "okay";
  1792. mode = "host";
  1793. vbus-supply = <&vdd_usb1>;
  1794. };
  1795. usb3-0 {
  1796. nvidia,usb2-companion = <1>;
  1797. vbus-supply = <&vdd_usb1>;
  1798. status = "okay";
  1799. };
  1800. };
  1801. };
  1802. usb@3530000 {
  1803. status = "okay";
  1804. phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
  1805. <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
  1806. <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>;
  1807. phy-names = "usb2-0", "usb2-1", "usb3-0";
  1808. };
  1809. usb@3550000 {
  1810. status = "okay";
  1811. phys = <&micro_b>;
  1812. phy-names = "usb2-0";
  1813. };
  1814. i2c@c250000 {
  1815. /* carrier board ID EEPROM */
  1816. eeprom@57 {
  1817. compatible = "atmel,24c02";
  1818. reg = <0x57>;
  1819. label = "system";
  1820. vcc-supply = <&vdd_1v8>;
  1821. address-width = <8>;
  1822. pagesize = <8>;
  1823. size = <256>;
  1824. read-only;
  1825. };
  1826. };
  1827. pcie@10003000 {
  1828. status = "okay";
  1829. dvdd-pex-supply = <&vdd_pex>;
  1830. hvdd-pex-pll-supply = <&vdd_1v8>;
  1831. hvdd-pex-supply = <&vdd_1v8>;
  1832. vddio-pexctl-aud-supply = <&vdd_1v8>;
  1833. pci@1,0 {
  1834. nvidia,num-lanes = <4>;
  1835. status = "okay";
  1836. };
  1837. pci@2,0 {
  1838. nvidia,num-lanes = <0>;
  1839. status = "disabled";
  1840. };
  1841. pci@3,0 {
  1842. nvidia,num-lanes = <1>;
  1843. status = "disabled";
  1844. };
  1845. };
  1846. host1x@13e00000 {
  1847. status = "okay";
  1848. dpaux@15040000 {
  1849. status = "okay";
  1850. };
  1851. display-hub@15200000 {
  1852. status = "okay";
  1853. };
  1854. dsi@15300000 {
  1855. status = "disabled";
  1856. };
  1857. /* DP on E3320 */
  1858. sor@15540000 {
  1859. status = "okay";
  1860. avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
  1861. vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
  1862. nvidia,dpaux = <&dpaux>;
  1863. };
  1864. sor@15580000 {
  1865. status = "okay";
  1866. avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
  1867. vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
  1868. hdmi-supply = <&vdd_hdmi>;
  1869. nvidia,ddc-i2c-bus = <&ddc>;
  1870. nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1)
  1871. GPIO_ACTIVE_LOW>;
  1872. };
  1873. dpaux@155c0000 {
  1874. status = "okay";
  1875. };
  1876. };
  1877. sata@3507000 {
  1878. status = "okay";
  1879. };
  1880. gpio-keys {
  1881. compatible = "gpio-keys";
  1882. key-power {
  1883. label = "Power";
  1884. gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0)
  1885. GPIO_ACTIVE_LOW>;
  1886. linux,input-type = <EV_KEY>;
  1887. linux,code = <KEY_POWER>;
  1888. debounce-interval = <10>;
  1889. wakeup-event-action = <EV_ACT_ASSERTED>;
  1890. wakeup-source;
  1891. };
  1892. key-volume-up {
  1893. label = "Volume Up";
  1894. gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1)
  1895. GPIO_ACTIVE_LOW>;
  1896. linux,input-type = <EV_KEY>;
  1897. linux,code = <KEY_VOLUMEUP>;
  1898. debounce-interval = <10>;
  1899. };
  1900. key-volume-down {
  1901. label = "Volume Down";
  1902. gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2)
  1903. GPIO_ACTIVE_LOW>;
  1904. linux,input-type = <EV_KEY>;
  1905. linux,code = <KEY_VOLUMEDOWN>;
  1906. debounce-interval = <10>;
  1907. };
  1908. };
  1909. vdd_sd: regulator-vdd-sd {
  1910. compatible = "regulator-fixed";
  1911. regulator-name = "SD_CARD_SW_PWR";
  1912. regulator-min-microvolt = <3300000>;
  1913. regulator-max-microvolt = <3300000>;
  1914. gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
  1915. enable-active-high;
  1916. vin-supply = <&vdd_3v3_sys>;
  1917. };
  1918. vdd_hdmi: regulator-vdd-hdmi {
  1919. compatible = "regulator-fixed";
  1920. regulator-name = "VDD_HDMI_5V0";
  1921. regulator-min-microvolt = <5000000>;
  1922. regulator-max-microvolt = <5000000>;
  1923. gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
  1924. enable-active-high;
  1925. vin-supply = <&vdd_5v0_sys>;
  1926. };
  1927. vdd_usb0: regulator-vdd-usb0 {
  1928. compatible = "regulator-fixed";
  1929. regulator-name = "VDD_USB0";
  1930. regulator-min-microvolt = <5000000>;
  1931. regulator-max-microvolt = <5000000>;
  1932. gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
  1933. enable-active-high;
  1934. vin-supply = <&vdd_5v0_sys>;
  1935. };
  1936. vdd_usb1: regulator-vdd-usb1 {
  1937. compatible = "regulator-fixed";
  1938. regulator-name = "VDD_USB1";
  1939. regulator-min-microvolt = <5000000>;
  1940. regulator-max-microvolt = <5000000>;
  1941. gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
  1942. enable-active-high;
  1943. vin-supply = <&vdd_5v0_sys>;
  1944. };
  1945. sound {
  1946. compatible = "nvidia,tegra186-audio-graph-card";
  1947. status = "okay";
  1948. dais = /* FE */
  1949. <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
  1950. <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
  1951. <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
  1952. <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
  1953. <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
  1954. /* Router */
  1955. <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
  1956. <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>,
  1957. <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>,
  1958. <&xbar_dspk1_port>, <&xbar_dspk2_port>,
  1959. <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
  1960. <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
  1961. <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
  1962. <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
  1963. <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
  1964. <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
  1965. <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
  1966. <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
  1967. <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
  1968. <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
  1969. <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
  1970. <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
  1971. <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
  1972. <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
  1973. <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
  1974. <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
  1975. <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
  1976. <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
  1977. <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
  1978. <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
  1979. <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
  1980. <&xbar_asrc_in7_port>,
  1981. <&xbar_ope1_in_port>,
  1982. /* HW accelerators */
  1983. <&sfc1_out_port>, <&sfc2_out_port>,
  1984. <&sfc3_out_port>, <&sfc4_out_port>,
  1985. <&mvc1_out_port>, <&mvc2_out_port>,
  1986. <&amx1_out_port>, <&amx2_out_port>,
  1987. <&amx3_out_port>, <&amx4_out_port>,
  1988. <&adx1_out1_port>, <&adx1_out2_port>,
  1989. <&adx1_out3_port>, <&adx1_out4_port>,
  1990. <&adx2_out1_port>, <&adx2_out2_port>,
  1991. <&adx2_out3_port>, <&adx2_out4_port>,
  1992. <&adx3_out1_port>, <&adx3_out2_port>,
  1993. <&adx3_out3_port>, <&adx3_out4_port>,
  1994. <&adx4_out1_port>, <&adx4_out2_port>,
  1995. <&adx4_out3_port>, <&adx4_out4_port>,
  1996. <&mixer_out1_port>, <&mixer_out2_port>,
  1997. <&mixer_out3_port>, <&mixer_out4_port>,
  1998. <&mixer_out5_port>,
  1999. <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
  2000. <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
  2001. <&ope1_out_port>,
  2002. /* I/O */
  2003. <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
  2004. <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
  2005. <&dmic3_port>, <&dspk1_port>, <&dspk2_port>;
  2006. label = "NVIDIA Jetson TX2 APE";
  2007. };
  2008. };