nuvoton-common-npcm8xx.dtsi 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2021 Nuvoton Technology [email protected]
  3. #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
  4. #include <dt-bindings/interrupt-controller/arm-gic.h>
  5. #include <dt-bindings/interrupt-controller/irq.h>
  6. / {
  7. #address-cells = <2>;
  8. #size-cells = <2>;
  9. interrupt-parent = <&gic>;
  10. soc {
  11. #address-cells = <2>;
  12. #size-cells = <2>;
  13. compatible = "simple-bus";
  14. interrupt-parent = <&gic>;
  15. ranges;
  16. gcr: system-controller@f0800000 {
  17. compatible = "nuvoton,npcm845-gcr", "syscon";
  18. reg = <0x0 0xf0800000 0x0 0x1000>;
  19. };
  20. gic: interrupt-controller@dfff9000 {
  21. compatible = "arm,gic-400";
  22. reg = <0x0 0xdfff9000 0x0 0x1000>,
  23. <0x0 0xdfffa000 0x0 0x2000>,
  24. <0x0 0xdfffc000 0x0 0x2000>,
  25. <0x0 0xdfffe000 0x0 0x2000>;
  26. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  27. #interrupt-cells = <3>;
  28. interrupt-controller;
  29. #address-cells = <0>;
  30. ppi-partitions {
  31. ppi_cluster0: interrupt-partition-0 {
  32. affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
  33. };
  34. };
  35. };
  36. };
  37. ahb {
  38. #address-cells = <2>;
  39. #size-cells = <2>;
  40. compatible = "simple-bus";
  41. interrupt-parent = <&gic>;
  42. ranges;
  43. rstc: reset-controller@f0801000 {
  44. compatible = "nuvoton,npcm845-reset";
  45. reg = <0x0 0xf0801000 0x0 0x78>;
  46. #reset-cells = <2>;
  47. nuvoton,sysgcr = <&gcr>;
  48. };
  49. clk: clock-controller@f0801000 {
  50. compatible = "nuvoton,npcm845-clk";
  51. #clock-cells = <1>;
  52. reg = <0x0 0xf0801000 0x0 0x1000>;
  53. };
  54. apb {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "simple-bus";
  58. interrupt-parent = <&gic>;
  59. ranges = <0x0 0x0 0xf0000000 0x00300000>,
  60. <0xfff00000 0x0 0xfff00000 0x00016000>;
  61. timer0: timer@8000 {
  62. compatible = "nuvoton,npcm845-timer";
  63. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  64. reg = <0x8000 0x1C>;
  65. clocks = <&clk NPCM8XX_CLK_REFCLK>;
  66. clock-names = "refclk";
  67. };
  68. serial0: serial@0 {
  69. compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
  70. reg = <0x0 0x1000>;
  71. clocks = <&clk NPCM8XX_CLK_UART>;
  72. interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  73. reg-shift = <2>;
  74. status = "disabled";
  75. };
  76. serial1: serial@1000 {
  77. compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
  78. reg = <0x1000 0x1000>;
  79. clocks = <&clk NPCM8XX_CLK_UART>;
  80. interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  81. reg-shift = <2>;
  82. status = "disabled";
  83. };
  84. serial2: serial@2000 {
  85. compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
  86. reg = <0x2000 0x1000>;
  87. clocks = <&clk NPCM8XX_CLK_UART>;
  88. interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  89. reg-shift = <2>;
  90. status = "disabled";
  91. };
  92. serial3: serial@3000 {
  93. compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
  94. reg = <0x3000 0x1000>;
  95. clocks = <&clk NPCM8XX_CLK_UART>;
  96. interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
  97. reg-shift = <2>;
  98. status = "disabled";
  99. };
  100. serial4: serial@4000 {
  101. compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
  102. reg = <0x4000 0x1000>;
  103. clocks = <&clk NPCM8XX_CLK_UART>;
  104. interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
  105. reg-shift = <2>;
  106. status = "disabled";
  107. };
  108. serial5: serial@5000 {
  109. compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
  110. reg = <0x5000 0x1000>;
  111. clocks = <&clk NPCM8XX_CLK_UART>;
  112. interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
  113. reg-shift = <2>;
  114. status = "disabled";
  115. };
  116. serial6: serial@6000 {
  117. compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
  118. reg = <0x6000 0x1000>;
  119. clocks = <&clk NPCM8XX_CLK_UART>;
  120. interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
  121. reg-shift = <2>;
  122. status = "disabled";
  123. };
  124. watchdog0: watchdog@801c {
  125. compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
  126. interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  127. reg = <0x801c 0x4>;
  128. status = "disabled";
  129. clocks = <&clk NPCM8XX_CLK_REFCLK>;
  130. syscon = <&gcr>;
  131. };
  132. watchdog1: watchdog@901c {
  133. compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
  134. interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  135. reg = <0x901c 0x4>;
  136. status = "disabled";
  137. clocks = <&clk NPCM8XX_CLK_REFCLK>;
  138. syscon = <&gcr>;
  139. };
  140. watchdog2: watchdog@a01c {
  141. compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
  142. interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
  143. reg = <0xa01c 0x4>;
  144. status = "disabled";
  145. clocks = <&clk NPCM8XX_CLK_REFCLK>;
  146. syscon = <&gcr>;
  147. };
  148. };
  149. };
  150. };