mt8195-evb.dts 2.9 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright (C) 2021 MediaTek Inc.
  4. * Author: Seiya Wang <[email protected]>
  5. */
  6. /dts-v1/;
  7. #include "mt8195.dtsi"
  8. / {
  9. model = "MediaTek MT8195 evaluation board";
  10. compatible = "mediatek,mt8195-evb", "mediatek,mt8195";
  11. aliases {
  12. serial0 = &uart0;
  13. };
  14. chosen {
  15. stdout-path = "serial0:921600n8";
  16. };
  17. memory@40000000 {
  18. device_type = "memory";
  19. reg = <0 0x40000000 0 0x80000000>;
  20. };
  21. };
  22. &auxadc {
  23. status = "okay";
  24. };
  25. &i2c0 {
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&i2c0_pin>;
  28. clock-frequency = <100000>;
  29. status = "okay";
  30. };
  31. &i2c1 {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&i2c1_pin>;
  34. clock-frequency = <400000>;
  35. status = "okay";
  36. };
  37. &i2c4 {
  38. pinctrl-names = "default";
  39. pinctrl-0 = <&i2c4_pin>;
  40. clock-frequency = <400000>;
  41. status = "okay";
  42. };
  43. &i2c6 {
  44. pinctrl-names = "default";
  45. pinctrl-0 = <&i2c6_pin>;
  46. clock-frequency = <400000>;
  47. status = "okay";
  48. };
  49. &nor_flash {
  50. status = "okay";
  51. pinctrl-names = "default";
  52. pinctrl-0 = <&nor_pins_default>;
  53. flash@0 {
  54. compatible = "jedec,spi-nor";
  55. reg = <0>;
  56. spi-max-frequency = <50000000>;
  57. };
  58. };
  59. &pio {
  60. i2c0_pin: i2c0-pins {
  61. pins {
  62. pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
  63. <PINMUX_GPIO9__FUNC_SCL0>;
  64. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  65. mediatek,drive-strength-adv = <0>;
  66. drive-strength = <6>;
  67. };
  68. };
  69. i2c1_pin: i2c1-pins {
  70. pins {
  71. pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
  72. <PINMUX_GPIO11__FUNC_SCL1>;
  73. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  74. mediatek,drive-strength-adv = <0>;
  75. drive-strength = <6>;
  76. };
  77. };
  78. i2c4_pin: i2c4-pins {
  79. pins {
  80. pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
  81. <PINMUX_GPIO17__FUNC_SCL4>;
  82. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  83. mediatek,drive-strength-adv = <7>;
  84. };
  85. };
  86. i2c6_pin: i2c6-pins {
  87. pins {
  88. pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
  89. <PINMUX_GPIO26__FUNC_SCL6>;
  90. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  91. };
  92. };
  93. i2c7_pin: i2c7-pins {
  94. pins {
  95. pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
  96. <PINMUX_GPIO28__FUNC_SDA7>;
  97. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  98. };
  99. };
  100. nor_pins_default: nor-pins {
  101. pins0 {
  102. pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
  103. <PINMUX_GPIO141__FUNC_SPINOR_CK>,
  104. <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
  105. bias-pull-down;
  106. };
  107. pins1 {
  108. pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>,
  109. <PINMUX_GPIO130__FUNC_SPINOR_IO2>,
  110. <PINMUX_GPIO131__FUNC_SPINOR_IO3>;
  111. bias-pull-up;
  112. };
  113. };
  114. uart0_pin: uart0-pins {
  115. pins {
  116. pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
  117. <PINMUX_GPIO99__FUNC_URXD0>;
  118. };
  119. };
  120. };
  121. &u3phy0 {
  122. status = "okay";
  123. };
  124. &u3phy1 {
  125. status = "okay";
  126. };
  127. &u3phy2 {
  128. status = "okay";
  129. };
  130. &u3phy3 {
  131. status = "okay";
  132. };
  133. &uart0 {
  134. pinctrl-names = "default";
  135. pinctrl-0 = <&uart0_pin>;
  136. status = "okay";
  137. };
  138. &xhci0 {
  139. status = "okay";
  140. };
  141. &xhci1 {
  142. status = "okay";
  143. };
  144. &xhci2 {
  145. status = "okay";
  146. };
  147. &xhci3 {
  148. /* This controller is connected with a BT device.
  149. * Disable usb2 lpm to prevent known issues.
  150. */
  151. usb2-lpm-disable;
  152. status = "okay";
  153. };