mt8195-cherry.dtsi 19 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright (C) 2021 MediaTek Inc.
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/spmi/spmi.h>
  7. #include "mt8195.dtsi"
  8. #include "mt6359.dtsi"
  9. / {
  10. aliases {
  11. i2c0 = &i2c0;
  12. i2c1 = &i2c1;
  13. i2c2 = &i2c2;
  14. i2c3 = &i2c3;
  15. i2c4 = &i2c4;
  16. i2c5 = &i2c5;
  17. i2c7 = &i2c7;
  18. mmc0 = &mmc0;
  19. mmc1 = &mmc1;
  20. serial0 = &uart0;
  21. };
  22. chosen {
  23. stdout-path = "serial0:115200n8";
  24. };
  25. memory@40000000 {
  26. device_type = "memory";
  27. reg = <0 0x40000000 0 0x80000000>;
  28. };
  29. /* system wide LDO 3.3V power rail */
  30. pp3300_z5: regulator-pp3300-ldo-z5 {
  31. compatible = "regulator-fixed";
  32. regulator-name = "pp3300_ldo_z5";
  33. regulator-always-on;
  34. regulator-boot-on;
  35. regulator-min-microvolt = <3300000>;
  36. regulator-max-microvolt = <3300000>;
  37. vin-supply = <&ppvar_sys>;
  38. };
  39. /* separately switched 3.3V power rail */
  40. pp3300_s3: regulator-pp3300-s3 {
  41. compatible = "regulator-fixed";
  42. regulator-name = "pp3300_s3";
  43. /* automatically sequenced by PMIC EXT_PMIC_EN2 */
  44. regulator-always-on;
  45. regulator-boot-on;
  46. regulator-min-microvolt = <3300000>;
  47. regulator-max-microvolt = <3300000>;
  48. vin-supply = <&pp3300_z2>;
  49. };
  50. /* system wide 3.3V power rail */
  51. pp3300_z2: regulator-pp3300-z2 {
  52. compatible = "regulator-fixed";
  53. regulator-name = "pp3300_z2";
  54. /* EN pin tied to pp4200_z2, which is controlled by EC */
  55. regulator-always-on;
  56. regulator-boot-on;
  57. regulator-min-microvolt = <3300000>;
  58. regulator-max-microvolt = <3300000>;
  59. vin-supply = <&ppvar_sys>;
  60. };
  61. /* system wide 4.2V power rail */
  62. pp4200_z2: regulator-pp4200-z2 {
  63. compatible = "regulator-fixed";
  64. regulator-name = "pp4200_z2";
  65. /* controlled by EC */
  66. regulator-always-on;
  67. regulator-boot-on;
  68. regulator-min-microvolt = <4200000>;
  69. regulator-max-microvolt = <4200000>;
  70. vin-supply = <&ppvar_sys>;
  71. };
  72. /* system wide switching 5.0V power rail */
  73. pp5000_s5: regulator-pp5000-s5 {
  74. compatible = "regulator-fixed";
  75. regulator-name = "pp5000_s5";
  76. /* controlled by EC */
  77. regulator-always-on;
  78. regulator-boot-on;
  79. regulator-min-microvolt = <5000000>;
  80. regulator-max-microvolt = <5000000>;
  81. vin-supply = <&ppvar_sys>;
  82. };
  83. /* system wide semi-regulated power rail from battery or USB */
  84. ppvar_sys: regulator-ppvar-sys {
  85. compatible = "regulator-fixed";
  86. regulator-name = "ppvar_sys";
  87. regulator-always-on;
  88. regulator-boot-on;
  89. };
  90. usb_vbus: regulator-5v0-usb-vbus {
  91. compatible = "regulator-fixed";
  92. regulator-name = "usb-vbus";
  93. regulator-min-microvolt = <5000000>;
  94. regulator-max-microvolt = <5000000>;
  95. enable-active-high;
  96. regulator-always-on;
  97. };
  98. reserved_memory: reserved-memory {
  99. #address-cells = <2>;
  100. #size-cells = <2>;
  101. ranges;
  102. scp_mem: memory@50000000 {
  103. compatible = "shared-dma-pool";
  104. reg = <0 0x50000000 0 0x2900000>;
  105. no-map;
  106. };
  107. };
  108. };
  109. &i2c0 {
  110. status = "okay";
  111. clock-frequency = <400000>;
  112. pinctrl-names = "default";
  113. pinctrl-0 = <&i2c0_pins>;
  114. };
  115. &i2c1 {
  116. status = "okay";
  117. clock-frequency = <400000>;
  118. i2c-scl-internal-delay-ns = <12500>;
  119. pinctrl-names = "default";
  120. pinctrl-0 = <&i2c1_pins>;
  121. trackpad@15 {
  122. compatible = "elan,ekth3000";
  123. reg = <0x15>;
  124. interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>;
  125. pinctrl-names = "default";
  126. pinctrl-0 = <&trackpad_pins>;
  127. vcc-supply = <&pp3300_s3>;
  128. wakeup-source;
  129. };
  130. };
  131. &i2c2 {
  132. status = "okay";
  133. clock-frequency = <400000>;
  134. pinctrl-names = "default";
  135. pinctrl-0 = <&i2c2_pins>;
  136. };
  137. &i2c3 {
  138. status = "okay";
  139. clock-frequency = <400000>;
  140. pinctrl-names = "default";
  141. pinctrl-0 = <&i2c3_pins>;
  142. tpm@50 {
  143. compatible = "google,cr50";
  144. reg = <0x50>;
  145. interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
  146. pinctrl-names = "default";
  147. pinctrl-0 = <&cr50_int>;
  148. };
  149. };
  150. &i2c4 {
  151. status = "okay";
  152. clock-frequency = <400000>;
  153. pinctrl-names = "default";
  154. pinctrl-0 = <&i2c4_pins>;
  155. ts_10: touchscreen@10 {
  156. compatible = "hid-over-i2c";
  157. reg = <0x10>;
  158. hid-descr-addr = <0x0001>;
  159. interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>;
  160. pinctrl-names = "default";
  161. pinctrl-0 = <&touchscreen_pins>;
  162. post-power-on-delay-ms = <10>;
  163. vdd-supply = <&pp3300_s3>;
  164. status = "disabled";
  165. };
  166. };
  167. &i2c5 {
  168. status = "okay";
  169. clock-frequency = <400000>;
  170. pinctrl-names = "default";
  171. pinctrl-0 = <&i2c5_pins>;
  172. };
  173. &i2c7 {
  174. status = "okay";
  175. clock-frequency = <400000>;
  176. pinctrl-names = "default";
  177. pinctrl-0 = <&i2c7_pins>;
  178. pmic@34 {
  179. #interrupt-cells = <2>;
  180. compatible = "mediatek,mt6360";
  181. reg = <0x34>;
  182. interrupt-controller;
  183. interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>;
  184. interrupt-names = "IRQB";
  185. pinctrl-names = "default";
  186. pinctrl-0 = <&subpmic_default>;
  187. wakeup-source;
  188. };
  189. };
  190. &mmc0 {
  191. status = "okay";
  192. bus-width = <8>;
  193. cap-mmc-highspeed;
  194. cap-mmc-hw-reset;
  195. hs400-ds-delay = <0x14c11>;
  196. max-frequency = <200000000>;
  197. mmc-hs200-1_8v;
  198. mmc-hs400-1_8v;
  199. no-sdio;
  200. no-sd;
  201. non-removable;
  202. pinctrl-names = "default", "state_uhs";
  203. pinctrl-0 = <&mmc0_pins_default>;
  204. pinctrl-1 = <&mmc0_pins_uhs>;
  205. vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
  206. vqmmc-supply = <&mt6359_vufs_ldo_reg>;
  207. };
  208. &mmc1 {
  209. status = "okay";
  210. bus-width = <4>;
  211. cap-sd-highspeed;
  212. cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
  213. max-frequency = <200000000>;
  214. no-mmc;
  215. no-sdio;
  216. pinctrl-names = "default", "state_uhs";
  217. pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>;
  218. pinctrl-1 = <&mmc1_pins_default>;
  219. sd-uhs-sdr50;
  220. sd-uhs-sdr104;
  221. vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
  222. vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
  223. };
  224. /* for CPU-L */
  225. &mt6359_vcore_buck_reg {
  226. regulator-always-on;
  227. };
  228. /* for CORE */
  229. &mt6359_vgpu11_buck_reg {
  230. regulator-always-on;
  231. };
  232. &mt6359_vgpu11_sshub_buck_reg {
  233. regulator-always-on;
  234. regulator-min-microvolt = <550000>;
  235. regulator-max-microvolt = <550000>;
  236. };
  237. /* for CORE SRAM */
  238. &mt6359_vpu_buck_reg {
  239. regulator-always-on;
  240. };
  241. &mt6359_vrf12_ldo_reg {
  242. regulator-always-on;
  243. };
  244. /* for GPU SRAM */
  245. &mt6359_vsram_others_ldo_reg {
  246. regulator-always-on;
  247. regulator-min-microvolt = <750000>;
  248. regulator-max-microvolt = <750000>;
  249. };
  250. &mt6359_vufs_ldo_reg {
  251. regulator-always-on;
  252. };
  253. &nor_flash {
  254. status = "okay";
  255. pinctrl-names = "default";
  256. pinctrl-0 = <&nor_pins_default>;
  257. flash@0 {
  258. compatible = "jedec,spi-nor";
  259. reg = <0>;
  260. spi-max-frequency = <52000000>;
  261. spi-rx-bus-width = <2>;
  262. spi-tx-bus-width = <2>;
  263. };
  264. };
  265. &pio {
  266. mediatek,rsel-resistance-in-si-unit;
  267. pinctrl-names = "default";
  268. pinctrl-0 = <&pio_default>;
  269. /* 144 lines */
  270. gpio-line-names =
  271. "I2S_SPKR_MCLK",
  272. "I2S_SPKR_DATAIN",
  273. "I2S_SPKR_LRCK",
  274. "I2S_SPKR_BCLK",
  275. "EC_AP_INT_ODL",
  276. /*
  277. * AP_FLASH_WP_L is crossystem ABI. Schematics
  278. * call it AP_FLASH_WP_ODL.
  279. */
  280. "AP_FLASH_WP_L",
  281. "TCHPAD_INT_ODL",
  282. "EDP_HPD_1V8",
  283. "AP_I2C_CAM_SDA",
  284. "AP_I2C_CAM_SCL",
  285. "AP_I2C_TCHPAD_SDA_1V8",
  286. "AP_I2C_TCHPAD_SCL_1V8",
  287. "AP_I2C_AUD_SDA",
  288. "AP_I2C_AUD_SCL",
  289. "AP_I2C_TPM_SDA_1V8",
  290. "AP_I2C_TPM_SCL_1V8",
  291. "AP_I2C_TCHSCR_SDA_1V8",
  292. "AP_I2C_TCHSCR_SCL_1V8",
  293. "EC_AP_HPD_OD",
  294. "",
  295. "PCIE_NVME_RST_L",
  296. "PCIE_NVME_CLKREQ_ODL",
  297. "PCIE_RST_1V8_L",
  298. "PCIE_CLKREQ_1V8_ODL",
  299. "PCIE_WAKE_1V8_ODL",
  300. "CLK_24M_CAM0",
  301. "CAM1_SEN_EN",
  302. "AP_I2C_PWR_SCL_1V8",
  303. "AP_I2C_PWR_SDA_1V8",
  304. "AP_I2C_MISC_SCL",
  305. "AP_I2C_MISC_SDA",
  306. "EN_PP5000_HDMI_X",
  307. "AP_HDMITX_HTPLG",
  308. "",
  309. "AP_HDMITX_SCL_1V8",
  310. "AP_HDMITX_SDA_1V8",
  311. "AP_RTC_CLK32K",
  312. "AP_EC_WATCHDOG_L",
  313. "SRCLKENA0",
  314. "SRCLKENA1",
  315. "PWRAP_SPI0_CS_L",
  316. "PWRAP_SPI0_CK",
  317. "PWRAP_SPI0_MOSI",
  318. "PWRAP_SPI0_MISO",
  319. "SPMI_SCL",
  320. "SPMI_SDA",
  321. "",
  322. "",
  323. "",
  324. "I2S_HP_DATAIN",
  325. "I2S_HP_MCLK",
  326. "I2S_HP_BCK",
  327. "I2S_HP_LRCK",
  328. "I2S_HP_DATAOUT",
  329. "SD_CD_ODL",
  330. "EN_PP3300_DISP_X",
  331. "TCHSCR_RST_1V8_L",
  332. "TCHSCR_REPORT_DISABLE",
  333. "EN_PP3300_WLAN_X",
  334. "BT_KILL_1V8_L",
  335. "I2S_SPKR_DATAOUT",
  336. "WIFI_KILL_1V8_L",
  337. "BEEP_ON",
  338. "SCP_I2C_SENSOR_SCL_1V8",
  339. "SCP_I2C_SENSOR_SDA_1V8",
  340. "",
  341. "",
  342. "",
  343. "",
  344. "AUD_CLK_MOSI",
  345. "AUD_SYNC_MOSI",
  346. "AUD_DAT_MOSI0",
  347. "AUD_DAT_MOSI1",
  348. "AUD_DAT_MISO0",
  349. "AUD_DAT_MISO1",
  350. "AUD_DAT_MISO2",
  351. "SCP_VREQ_VAO",
  352. "AP_SPI_GSC_TPM_CLK",
  353. "AP_SPI_GSC_TPM_MOSI",
  354. "AP_SPI_GSC_TPM_CS_L",
  355. "AP_SPI_GSC_TPM_MISO",
  356. "EN_PP1000_CAM_X",
  357. "AP_EDP_BKLTEN",
  358. "",
  359. "USB3_HUB_RST_L",
  360. "",
  361. "WLAN_ALERT_ODL",
  362. "EC_IN_RW_ODL",
  363. "GSC_AP_INT_ODL",
  364. "HP_INT_ODL",
  365. "CAM0_RST_L",
  366. "CAM1_RST_L",
  367. "TCHSCR_INT_1V8_L",
  368. "CAM1_DET_L",
  369. "RST_ALC1011_L",
  370. "",
  371. "",
  372. "BL_PWM_1V8",
  373. "UART_AP_TX_DBG_RX",
  374. "UART_DBG_TX_AP_RX",
  375. "EN_SPKR",
  376. "AP_EC_WARM_RST_REQ",
  377. "UART_SCP_TX_DBGCON_RX",
  378. "UART_DBGCON_TX_SCP_RX",
  379. "",
  380. "",
  381. "KPCOL0",
  382. "",
  383. "MT6315_GPU_INT",
  384. "MT6315_PROC_BC_INT",
  385. "SD_CMD",
  386. "SD_CLK",
  387. "SD_DAT0",
  388. "SD_DAT1",
  389. "SD_DAT2",
  390. "SD_DAT3",
  391. "EMMC_DAT7",
  392. "EMMC_DAT6",
  393. "EMMC_DAT5",
  394. "EMMC_DAT4",
  395. "EMMC_RSTB",
  396. "EMMC_CMD",
  397. "EMMC_CLK",
  398. "EMMC_DAT3",
  399. "EMMC_DAT2",
  400. "EMMC_DAT1",
  401. "EMMC_DAT0",
  402. "EMMC_DSL",
  403. "",
  404. "",
  405. "MT6360_INT_ODL",
  406. "SCP_JTAG0_TRSTN",
  407. "AP_SPI_EC_CS_L",
  408. "AP_SPI_EC_CLK",
  409. "AP_SPI_EC_MOSI",
  410. "AP_SPI_EC_MISO",
  411. "SCP_JTAG0_TMS",
  412. "SCP_JTAG0_TCK",
  413. "SCP_JTAG0_TDO",
  414. "SCP_JTAG0_TDI",
  415. "AP_SPI_FLASH_CS_L",
  416. "AP_SPI_FLASH_CLK",
  417. "AP_SPI_FLASH_MOSI",
  418. "AP_SPI_FLASH_MISO";
  419. cr50_int: cr50-irq-default-pins {
  420. pins-gsc-ap-int-odl {
  421. pinmux = <PINMUX_GPIO88__FUNC_GPIO88>;
  422. input-enable;
  423. };
  424. };
  425. cros_ec_int: cros-ec-irq-default-pins {
  426. pins-ec-ap-int-odl {
  427. pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
  428. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  429. input-enable;
  430. };
  431. };
  432. i2c0_pins: i2c0-default-pins {
  433. pins-bus {
  434. pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
  435. <PINMUX_GPIO9__FUNC_SCL0>;
  436. bias-disable;
  437. drive-strength-microamp = <1000>;
  438. };
  439. };
  440. i2c1_pins: i2c1-default-pins {
  441. pins-bus {
  442. pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
  443. <PINMUX_GPIO11__FUNC_SCL1>;
  444. bias-pull-up = <1000>;
  445. drive-strength-microamp = <1000>;
  446. };
  447. };
  448. i2c2_pins: i2c2-default-pins {
  449. pins-bus {
  450. pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
  451. <PINMUX_GPIO13__FUNC_SCL2>;
  452. bias-disable;
  453. drive-strength-microamp = <1000>;
  454. };
  455. };
  456. i2c3_pins: i2c3-default-pins {
  457. pins-bus {
  458. pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
  459. <PINMUX_GPIO15__FUNC_SCL3>;
  460. bias-pull-up = <1000>;
  461. drive-strength-microamp = <1000>;
  462. };
  463. };
  464. i2c4_pins: i2c4-default-pins {
  465. pins-bus {
  466. pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
  467. <PINMUX_GPIO17__FUNC_SCL4>;
  468. bias-pull-up = <1000>;
  469. drive-strength = <4>;
  470. };
  471. };
  472. i2c5_pins: i2c5-default-pins {
  473. pins-bus {
  474. pinmux = <PINMUX_GPIO29__FUNC_SCL5>,
  475. <PINMUX_GPIO30__FUNC_SDA5>;
  476. bias-disable;
  477. drive-strength-microamp = <1000>;
  478. };
  479. };
  480. i2c7_pins: i2c7-default-pins {
  481. pins-bus {
  482. pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
  483. <PINMUX_GPIO28__FUNC_SDA7>;
  484. bias-disable;
  485. };
  486. };
  487. mmc0_pins_default: mmc0-default-pins {
  488. pins-cmd-dat {
  489. pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
  490. <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
  491. <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
  492. <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
  493. <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
  494. <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
  495. <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
  496. <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
  497. <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
  498. input-enable;
  499. drive-strength = <6>;
  500. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  501. };
  502. pins-clk {
  503. pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
  504. drive-strength = <6>;
  505. bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
  506. };
  507. pins-rst {
  508. pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
  509. drive-strength = <6>;
  510. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  511. };
  512. };
  513. mmc0_pins_uhs: mmc0-uhs-pins {
  514. pins-cmd-dat {
  515. pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
  516. <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
  517. <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
  518. <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
  519. <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
  520. <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
  521. <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
  522. <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
  523. <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
  524. input-enable;
  525. drive-strength = <8>;
  526. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  527. };
  528. pins-clk {
  529. pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
  530. drive-strength = <8>;
  531. bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
  532. };
  533. pins-ds {
  534. pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
  535. drive-strength = <8>;
  536. bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
  537. };
  538. pins-rst {
  539. pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
  540. drive-strength = <8>;
  541. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  542. };
  543. };
  544. mmc1_pins_detect: mmc1-detect-pins {
  545. pins-insert {
  546. pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
  547. bias-pull-up;
  548. };
  549. };
  550. mmc1_pins_default: mmc1-default-pins {
  551. pins-cmd-dat {
  552. pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
  553. <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
  554. <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
  555. <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
  556. <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
  557. input-enable;
  558. drive-strength = <8>;
  559. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  560. };
  561. pins-clk {
  562. pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
  563. drive-strength = <8>;
  564. bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
  565. };
  566. };
  567. nor_pins_default: nor-default-pins {
  568. pins-ck-io {
  569. pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
  570. <PINMUX_GPIO141__FUNC_SPINOR_CK>,
  571. <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
  572. drive-strength = <6>;
  573. bias-pull-down;
  574. };
  575. pins-cs {
  576. pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>;
  577. drive-strength = <6>;
  578. bias-pull-up;
  579. };
  580. };
  581. pio_default: pio-default-pins {
  582. pins-wifi-enable {
  583. pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
  584. output-high;
  585. drive-strength = <14>;
  586. };
  587. pins-low-power-pd {
  588. pinmux = <PINMUX_GPIO25__FUNC_GPIO25>,
  589. <PINMUX_GPIO26__FUNC_GPIO26>,
  590. <PINMUX_GPIO46__FUNC_GPIO46>,
  591. <PINMUX_GPIO47__FUNC_GPIO47>,
  592. <PINMUX_GPIO48__FUNC_GPIO48>,
  593. <PINMUX_GPIO65__FUNC_GPIO65>,
  594. <PINMUX_GPIO66__FUNC_GPIO66>,
  595. <PINMUX_GPIO67__FUNC_GPIO67>,
  596. <PINMUX_GPIO68__FUNC_GPIO68>,
  597. <PINMUX_GPIO128__FUNC_GPIO128>,
  598. <PINMUX_GPIO129__FUNC_GPIO129>;
  599. input-enable;
  600. bias-pull-down;
  601. };
  602. pins-low-power-pupd {
  603. pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
  604. <PINMUX_GPIO78__FUNC_GPIO78>,
  605. <PINMUX_GPIO79__FUNC_GPIO79>,
  606. <PINMUX_GPIO80__FUNC_GPIO80>,
  607. <PINMUX_GPIO83__FUNC_GPIO83>,
  608. <PINMUX_GPIO85__FUNC_GPIO85>,
  609. <PINMUX_GPIO90__FUNC_GPIO90>,
  610. <PINMUX_GPIO91__FUNC_GPIO91>,
  611. <PINMUX_GPIO93__FUNC_GPIO93>,
  612. <PINMUX_GPIO94__FUNC_GPIO94>,
  613. <PINMUX_GPIO95__FUNC_GPIO95>,
  614. <PINMUX_GPIO96__FUNC_GPIO96>,
  615. <PINMUX_GPIO104__FUNC_GPIO104>,
  616. <PINMUX_GPIO105__FUNC_GPIO105>,
  617. <PINMUX_GPIO107__FUNC_GPIO107>;
  618. input-enable;
  619. bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
  620. };
  621. };
  622. scp_pins: scp-default-pins {
  623. pins-vreq {
  624. pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
  625. bias-disable;
  626. input-enable;
  627. };
  628. };
  629. spi0_pins: spi0-default-pins {
  630. pins-cs-mosi-clk {
  631. pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
  632. <PINMUX_GPIO134__FUNC_SPIM0_MO>,
  633. <PINMUX_GPIO133__FUNC_SPIM0_CLK>;
  634. bias-disable;
  635. };
  636. pins-miso {
  637. pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
  638. bias-pull-down;
  639. };
  640. };
  641. subpmic_default: subpmic-default-pins {
  642. subpmic_pin_irq: pins-subpmic-int-n {
  643. pinmux = <PINMUX_GPIO130__FUNC_GPIO130>;
  644. input-enable;
  645. bias-pull-up;
  646. };
  647. };
  648. trackpad_pins: trackpad-default-pins {
  649. pins-int-n {
  650. pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
  651. input-enable;
  652. bias-pull-up;
  653. };
  654. };
  655. touchscreen_pins: touchscreen-default-pins {
  656. pins-int-n {
  657. pinmux = <PINMUX_GPIO92__FUNC_GPIO92>;
  658. input-enable;
  659. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  660. };
  661. pins-rst {
  662. pinmux = <PINMUX_GPIO56__FUNC_GPIO56>;
  663. output-high;
  664. };
  665. pins-report-sw {
  666. pinmux = <PINMUX_GPIO57__FUNC_GPIO57>;
  667. output-low;
  668. };
  669. };
  670. };
  671. &pmic {
  672. interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
  673. };
  674. &scp {
  675. status = "okay";
  676. firmware-name = "mediatek/mt8195/scp.img";
  677. memory-region = <&scp_mem>;
  678. pinctrl-names = "default";
  679. pinctrl-0 = <&scp_pins>;
  680. cros-ec-rpmsg {
  681. compatible = "google,cros-ec-rpmsg";
  682. mediatek,rpmsg-name = "cros-ec-rpmsg";
  683. };
  684. };
  685. &spi0 {
  686. status = "okay";
  687. pinctrl-names = "default";
  688. pinctrl-0 = <&spi0_pins>;
  689. mediatek,pad-select = <0>;
  690. cros_ec: ec@0 {
  691. #address-cells = <1>;
  692. #size-cells = <0>;
  693. compatible = "google,cros-ec-spi";
  694. reg = <0>;
  695. interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>;
  696. pinctrl-names = "default";
  697. pinctrl-0 = <&cros_ec_int>;
  698. spi-max-frequency = <3000000>;
  699. keyboard-backlight {
  700. compatible = "google,cros-kbd-led-backlight";
  701. };
  702. i2c_tunnel: i2c-tunnel {
  703. compatible = "google,cros-ec-i2c-tunnel";
  704. google,remote-bus = <0>;
  705. #address-cells = <1>;
  706. #size-cells = <0>;
  707. };
  708. mt_pmic_vmc_ldo_reg: regulator@0 {
  709. compatible = "google,cros-ec-regulator";
  710. reg = <0>;
  711. regulator-name = "mt_pmic_vmc_ldo";
  712. regulator-min-microvolt = <1200000>;
  713. regulator-max-microvolt = <3600000>;
  714. };
  715. mt_pmic_vmch_ldo_reg: regulator@1 {
  716. compatible = "google,cros-ec-regulator";
  717. reg = <1>;
  718. regulator-name = "mt_pmic_vmch_ldo";
  719. regulator-min-microvolt = <2700000>;
  720. regulator-max-microvolt = <3600000>;
  721. };
  722. typec {
  723. compatible = "google,cros-ec-typec";
  724. #address-cells = <1>;
  725. #size-cells = <0>;
  726. usb_c0: connector@0 {
  727. compatible = "usb-c-connector";
  728. reg = <0>;
  729. power-role = "dual";
  730. data-role = "host";
  731. try-power-role = "source";
  732. };
  733. usb_c1: connector@1 {
  734. compatible = "usb-c-connector";
  735. reg = <1>;
  736. power-role = "dual";
  737. data-role = "host";
  738. try-power-role = "source";
  739. };
  740. };
  741. };
  742. };
  743. &spmi {
  744. #address-cells = <2>;
  745. #size-cells = <0>;
  746. mt6315@6 {
  747. compatible = "mediatek,mt6315-regulator";
  748. reg = <0x6 SPMI_USID>;
  749. regulators {
  750. mt6315_6_vbuck1: vbuck1 {
  751. regulator-compatible = "vbuck1";
  752. regulator-name = "Vbcpu";
  753. regulator-min-microvolt = <300000>;
  754. regulator-max-microvolt = <1193750>;
  755. regulator-enable-ramp-delay = <256>;
  756. regulator-ramp-delay = <6250>;
  757. regulator-allowed-modes = <0 1 2>;
  758. regulator-always-on;
  759. };
  760. };
  761. };
  762. mt6315@7 {
  763. compatible = "mediatek,mt6315-regulator";
  764. reg = <0x7 SPMI_USID>;
  765. regulators {
  766. mt6315_7_vbuck1: vbuck1 {
  767. regulator-compatible = "vbuck1";
  768. regulator-name = "Vgpu";
  769. regulator-min-microvolt = <625000>;
  770. regulator-max-microvolt = <1193750>;
  771. regulator-enable-ramp-delay = <256>;
  772. regulator-ramp-delay = <6250>;
  773. regulator-allowed-modes = <0 1 2>;
  774. regulator-always-on;
  775. };
  776. };
  777. };
  778. };
  779. &u3phy0 {
  780. status = "okay";
  781. };
  782. &u3phy1 {
  783. status = "okay";
  784. };
  785. &u3phy2 {
  786. status = "okay";
  787. };
  788. &u3phy3 {
  789. status = "okay";
  790. };
  791. &uart0 {
  792. status = "okay";
  793. };
  794. &xhci0 {
  795. status = "okay";
  796. vusb33-supply = <&mt6359_vusb_ldo_reg>;
  797. vbus-supply = <&usb_vbus>;
  798. };
  799. &xhci1 {
  800. status = "okay";
  801. vusb33-supply = <&mt6359_vusb_ldo_reg>;
  802. vbus-supply = <&usb_vbus>;
  803. };
  804. &xhci2 {
  805. status = "okay";
  806. vusb33-supply = <&mt6359_vusb_ldo_reg>;
  807. vbus-supply = <&usb_vbus>;
  808. };
  809. &xhci3 {
  810. status = "okay";
  811. /* MT7921's USB Bluetooth has issues with USB2 LPM */
  812. usb2-lpm-disable;
  813. vusb33-supply = <&mt6359_vusb_ldo_reg>;
  814. vbus-supply = <&usb_vbus>;
  815. };
  816. #include <arm/cros-ec-keyboard.dtsi>
  817. #include <arm/cros-ec-sbs.dtsi>
  818. &keyboard_controller {
  819. function-row-physmap = <
  820. MATRIX_KEY(0x00, 0x02, 0) /* T1 */
  821. MATRIX_KEY(0x03, 0x02, 0) /* T2 */
  822. MATRIX_KEY(0x02, 0x02, 0) /* T3 */
  823. MATRIX_KEY(0x01, 0x02, 0) /* T4 */
  824. MATRIX_KEY(0x03, 0x04, 0) /* T5 */
  825. MATRIX_KEY(0x02, 0x04, 0) /* T6 */
  826. MATRIX_KEY(0x01, 0x04, 0) /* T7 */
  827. MATRIX_KEY(0x02, 0x09, 0) /* T8 */
  828. MATRIX_KEY(0x01, 0x09, 0) /* T9 */
  829. MATRIX_KEY(0x00, 0x04, 0) /* T10 */
  830. >;
  831. linux,keymap = <
  832. MATRIX_KEY(0x00, 0x02, KEY_BACK)
  833. MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
  834. MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
  835. MATRIX_KEY(0x01, 0x02, KEY_SCALE)
  836. MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
  837. MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
  838. MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
  839. MATRIX_KEY(0x02, 0x09, KEY_MUTE)
  840. MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
  841. MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
  842. CROS_STD_MAIN_KEYMAP
  843. >;
  844. };