mt8192-asurada.dtsi 19 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc.
  4. * Author: Seiya Wang <[email protected]>
  5. */
  6. /dts-v1/;
  7. #include "mt8192.dtsi"
  8. #include "mt6359.dtsi"
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/spmi/spmi.h>
  11. / {
  12. aliases {
  13. serial0 = &uart0;
  14. };
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. memory@40000000 {
  19. device_type = "memory";
  20. reg = <0 0x40000000 0 0x80000000>;
  21. };
  22. /* system wide LDO 1.8V power rail */
  23. pp1800_ldo_g: regulator-1v8-g {
  24. compatible = "regulator-fixed";
  25. regulator-name = "pp1800_ldo_g";
  26. regulator-always-on;
  27. regulator-boot-on;
  28. regulator-min-microvolt = <1800000>;
  29. regulator-max-microvolt = <1800000>;
  30. vin-supply = <&pp3300_g>;
  31. };
  32. /* system wide switching 3.3V power rail */
  33. pp3300_g: regulator-3v3-g {
  34. compatible = "regulator-fixed";
  35. regulator-name = "pp3300_g";
  36. regulator-always-on;
  37. regulator-boot-on;
  38. regulator-min-microvolt = <3300000>;
  39. regulator-max-microvolt = <3300000>;
  40. vin-supply = <&ppvar_sys>;
  41. };
  42. /* system wide LDO 3.3V power rail */
  43. pp3300_ldo_z: regulator-3v3-z {
  44. compatible = "regulator-fixed";
  45. regulator-name = "pp3300_ldo_z";
  46. regulator-always-on;
  47. regulator-boot-on;
  48. regulator-min-microvolt = <3300000>;
  49. regulator-max-microvolt = <3300000>;
  50. vin-supply = <&ppvar_sys>;
  51. };
  52. /* separately switched 3.3V power rail */
  53. pp3300_u: regulator-3v3-u {
  54. compatible = "regulator-fixed";
  55. regulator-name = "pp3300_u";
  56. regulator-always-on;
  57. regulator-boot-on;
  58. regulator-min-microvolt = <3300000>;
  59. regulator-max-microvolt = <3300000>;
  60. /* enable pin wired to GPIO controlled by EC */
  61. vin-supply = <&pp3300_g>;
  62. };
  63. pp3300_wlan: regulator-3v3-wlan {
  64. compatible = "regulator-fixed";
  65. regulator-name = "pp3300_wlan";
  66. regulator-always-on;
  67. regulator-boot-on;
  68. regulator-min-microvolt = <3300000>;
  69. regulator-max-microvolt = <3300000>;
  70. pinctrl-names = "default";
  71. pinctrl-0 = <&pp3300_wlan_pins>;
  72. enable-active-high;
  73. gpio = <&pio 143 GPIO_ACTIVE_HIGH>;
  74. };
  75. /* system wide switching 5.0V power rail */
  76. pp5000_a: regulator-5v0-a {
  77. compatible = "regulator-fixed";
  78. regulator-name = "pp5000_a";
  79. regulator-always-on;
  80. regulator-boot-on;
  81. regulator-min-microvolt = <5000000>;
  82. regulator-max-microvolt = <5000000>;
  83. vin-supply = <&ppvar_sys>;
  84. };
  85. /* system wide semi-regulated power rail from battery or USB */
  86. ppvar_sys: regulator-var-sys {
  87. compatible = "regulator-fixed";
  88. regulator-name = "ppvar_sys";
  89. regulator-always-on;
  90. regulator-boot-on;
  91. };
  92. reserved_memory: reserved-memory {
  93. #address-cells = <2>;
  94. #size-cells = <2>;
  95. ranges;
  96. scp_mem_reserved: scp@50000000 {
  97. compatible = "shared-dma-pool";
  98. reg = <0 0x50000000 0 0x2900000>;
  99. no-map;
  100. };
  101. wifi_restricted_dma_region: wifi@c0000000 {
  102. compatible = "restricted-dma-pool";
  103. reg = <0 0xc0000000 0 0x4000000>;
  104. };
  105. };
  106. };
  107. &i2c0 {
  108. status = "okay";
  109. clock-frequency = <400000>;
  110. pinctrl-names = "default";
  111. pinctrl-0 = <&i2c0_pins>;
  112. touchscreen: touchscreen@10 {
  113. reg = <0x10>;
  114. interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>;
  115. pinctrl-names = "default";
  116. pinctrl-0 = <&touchscreen_pins>;
  117. };
  118. };
  119. &i2c1 {
  120. status = "okay";
  121. clock-frequency = <400000>;
  122. pinctrl-names = "default";
  123. pinctrl-0 = <&i2c1_pins>;
  124. };
  125. &i2c2 {
  126. status = "okay";
  127. clock-frequency = <400000>;
  128. clock-stretch-ns = <12600>;
  129. pinctrl-names = "default";
  130. pinctrl-0 = <&i2c2_pins>;
  131. trackpad@15 {
  132. compatible = "elan,ekth3000";
  133. reg = <0x15>;
  134. interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
  135. pinctrl-names = "default";
  136. pinctrl-0 = <&trackpad_pins>;
  137. vcc-supply = <&pp3300_u>;
  138. wakeup-source;
  139. };
  140. };
  141. &i2c3 {
  142. status = "okay";
  143. clock-frequency = <400000>;
  144. pinctrl-names = "default";
  145. pinctrl-0 = <&i2c3_pins>;
  146. };
  147. &i2c7 {
  148. status = "okay";
  149. clock-frequency = <400000>;
  150. pinctrl-names = "default";
  151. pinctrl-0 = <&i2c7_pins>;
  152. };
  153. &mmc0 {
  154. status = "okay";
  155. pinctrl-names = "default", "state_uhs";
  156. pinctrl-0 = <&mmc0_default_pins>;
  157. pinctrl-1 = <&mmc0_uhs_pins>;
  158. bus-width = <8>;
  159. max-frequency = <200000000>;
  160. vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
  161. vqmmc-supply = <&mt6359_vufs_ldo_reg>;
  162. cap-mmc-highspeed;
  163. mmc-hs200-1_8v;
  164. mmc-hs400-1_8v;
  165. supports-cqe;
  166. cap-mmc-hw-reset;
  167. mmc-hs400-enhanced-strobe;
  168. hs400-ds-delay = <0x12814>;
  169. no-sdio;
  170. no-sd;
  171. non-removable;
  172. };
  173. &mmc1 {
  174. status = "okay";
  175. pinctrl-names = "default", "state_uhs";
  176. pinctrl-0 = <&mmc1_default_pins>;
  177. pinctrl-1 = <&mmc1_uhs_pins>;
  178. bus-width = <4>;
  179. max-frequency = <200000000>;
  180. cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>;
  181. vmmc-supply = <&mt6360_ldo5_reg>;
  182. vqmmc-supply = <&mt6360_ldo3_reg>;
  183. cap-sd-highspeed;
  184. sd-uhs-sdr50;
  185. sd-uhs-sdr104;
  186. no-sdio;
  187. no-mmc;
  188. };
  189. /* for CORE */
  190. &mt6359_vgpu11_buck_reg {
  191. regulator-always-on;
  192. };
  193. &mt6359_vgpu11_sshub_buck_reg {
  194. regulator-always-on;
  195. regulator-min-microvolt = <575000>;
  196. regulator-max-microvolt = <575000>;
  197. };
  198. &mt6359_vrf12_ldo_reg {
  199. regulator-always-on;
  200. };
  201. &mt6359_vufs_ldo_reg {
  202. regulator-always-on;
  203. };
  204. &mt6359codec {
  205. mediatek,dmic-mode = <1>; /* one-wire */
  206. mediatek,mic-type-0 = <2>; /* DMIC */
  207. mediatek,mic-type-2 = <2>; /* DMIC */
  208. };
  209. &nor_flash {
  210. status = "okay";
  211. pinctrl-names = "default";
  212. pinctrl-0 = <&nor_flash_pins>;
  213. assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
  214. assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>;
  215. flash@0 {
  216. compatible = "winbond,w25q64jwm", "jedec,spi-nor";
  217. reg = <0>;
  218. spi-max-frequency = <52000000>;
  219. spi-rx-bus-width = <2>;
  220. spi-tx-bus-width = <2>;
  221. };
  222. };
  223. &pcie {
  224. pinctrl-names = "default";
  225. pinctrl-0 = <&pcie_pins>;
  226. pcie0: pcie@0,0 {
  227. device_type = "pci";
  228. reg = <0x0000 0 0 0 0>;
  229. num-lanes = <1>;
  230. bus-range = <0x1 0x1>;
  231. #address-cells = <3>;
  232. #size-cells = <2>;
  233. ranges;
  234. wifi: wifi@0,0 {
  235. reg = <0x10000 0 0 0 0x100000>,
  236. <0x10000 0 0x100000 0 0x100000>;
  237. memory-region = <&wifi_restricted_dma_region>;
  238. };
  239. };
  240. };
  241. &pio {
  242. /* 220 lines */
  243. gpio-line-names = "I2S_DP_LRCK",
  244. "IS_DP_BCLK",
  245. "I2S_DP_MCLK",
  246. "I2S_DP_DATAOUT",
  247. "SAR0_INT_ODL",
  248. "EC_AP_INT_ODL",
  249. "EDPBRDG_INT_ODL",
  250. "DPBRDG_INT_ODL",
  251. "DPBRDG_PWREN",
  252. "DPBRDG_RST_ODL",
  253. "I2S_HP_MCLK",
  254. "I2S_HP_BCK",
  255. "I2S_HP_LRCK",
  256. "I2S_HP_DATAIN",
  257. /*
  258. * AP_FLASH_WP_L is crossystem ABI. Schematics
  259. * call it AP_FLASH_WP_ODL.
  260. */
  261. "AP_FLASH_WP_L",
  262. "TRACKPAD_INT_ODL",
  263. "EC_AP_HPD_OD",
  264. "SD_CD_ODL",
  265. "HP_INT_ODL_ALC",
  266. "EN_PP1000_DPBRDG",
  267. "AP_GPIO20",
  268. "TOUCH_INT_L_1V8",
  269. "UART_BT_WAKE_ODL",
  270. "AP_GPIO23",
  271. "AP_SPI_FLASH_CS_L",
  272. "AP_SPI_FLASH_CLK",
  273. "EN_PP3300_DPBRDG_DX",
  274. "AP_SPI_FLASH_MOSI",
  275. "AP_SPI_FLASH_MISO",
  276. "I2S_HP_DATAOUT",
  277. "AP_GPIO30",
  278. "I2S_SPKR_MCLK",
  279. "I2S_SPKR_BCLK",
  280. "I2S_SPKR_LRCK",
  281. "I2S_SPKR_DATAIN",
  282. "I2S_SPKR_DATAOUT",
  283. "AP_SPI_H1_TPM_CLK",
  284. "AP_SPI_H1_TPM_CS_L",
  285. "AP_SPI_H1_TPM_MISO",
  286. "AP_SPI_H1_TPM_MOSI",
  287. "BL_PWM",
  288. "EDPBRDG_PWREN",
  289. "EDPBRDG_RST_ODL",
  290. "EN_PP3300_HUB",
  291. "HUB_RST_L",
  292. "",
  293. "",
  294. "",
  295. "",
  296. "",
  297. "",
  298. "SD_CLK",
  299. "SD_CMD",
  300. "SD_DATA3",
  301. "SD_DATA0",
  302. "SD_DATA2",
  303. "SD_DATA1",
  304. "",
  305. "",
  306. "",
  307. "",
  308. "",
  309. "",
  310. "PCIE_WAKE_ODL",
  311. "PCIE_RST_L",
  312. "PCIE_CLKREQ_ODL",
  313. "",
  314. "",
  315. "",
  316. "",
  317. "",
  318. "",
  319. "",
  320. "",
  321. "",
  322. "",
  323. "",
  324. "",
  325. "",
  326. "",
  327. "",
  328. "",
  329. "",
  330. "",
  331. "",
  332. "",
  333. "",
  334. "",
  335. "",
  336. "SPMI_SCL",
  337. "SPMI_SDA",
  338. "AP_GOOD",
  339. "UART_DBG_TX_AP_RX",
  340. "UART_AP_TX_DBG_RX",
  341. "UART_AP_TX_BT_RX",
  342. "UART_BT_TX_AP_RX",
  343. "MIPI_DPI_D0_R",
  344. "MIPI_DPI_D1_R",
  345. "MIPI_DPI_D2_R",
  346. "MIPI_DPI_D3_R",
  347. "MIPI_DPI_D4_R",
  348. "MIPI_DPI_D5_R",
  349. "MIPI_DPI_D6_R",
  350. "MIPI_DPI_D7_R",
  351. "MIPI_DPI_D8_R",
  352. "MIPI_DPI_D9_R",
  353. "MIPI_DPI_D10_R",
  354. "",
  355. "",
  356. "MIPI_DPI_DE_R",
  357. "MIPI_DPI_D11_R",
  358. "MIPI_DPI_VSYNC_R",
  359. "MIPI_DPI_CLK_R",
  360. "MIPI_DPI_HSYNC_R",
  361. "PCM_BT_DATAIN",
  362. "PCM_BT_SYNC",
  363. "PCM_BT_DATAOUT",
  364. "PCM_BT_CLK",
  365. "AP_I2C_AUDIO_SCL",
  366. "AP_I2C_AUDIO_SDA",
  367. "SCP_I2C_SCL",
  368. "SCP_I2C_SDA",
  369. "AP_I2C_WLAN_SCL",
  370. "AP_I2C_WLAN_SDA",
  371. "AP_I2C_DPBRDG_SCL",
  372. "AP_I2C_DPBRDG_SDA",
  373. "EN_PP1800_DPBRDG_DX",
  374. "EN_PP3300_EDP_DX",
  375. "EN_PP1800_EDPBRDG_DX",
  376. "EN_PP1000_EDPBRDG",
  377. "SCP_JTAG0_TDO",
  378. "SCP_JTAG0_TDI",
  379. "SCP_JTAG0_TMS",
  380. "SCP_JTAG0_TCK",
  381. "SCP_JTAG0_TRSTN",
  382. "EN_PP3000_VMC_PMU",
  383. "EN_PP3300_DISPLAY_DX",
  384. "TOUCH_RST_L_1V8",
  385. "TOUCH_REPORT_DISABLE",
  386. "",
  387. "",
  388. "AP_I2C_TRACKPAD_SCL_1V8",
  389. "AP_I2C_TRACKPAD_SDA_1V8",
  390. "EN_PP3300_WLAN",
  391. "BT_KILL_L",
  392. "WIFI_KILL_L",
  393. "SET_VMC_VOLT_AT_1V8",
  394. "EN_SPK",
  395. "AP_WARM_RST_REQ",
  396. "",
  397. "",
  398. "EN_PP3000_SD_S3",
  399. "AP_EDP_BKLTEN",
  400. "",
  401. "",
  402. "",
  403. "AP_SPI_EC_CLK",
  404. "AP_SPI_EC_CS_L",
  405. "AP_SPI_EC_MISO",
  406. "AP_SPI_EC_MOSI",
  407. "AP_I2C_EDPBRDG_SCL",
  408. "AP_I2C_EDPBRDG_SDA",
  409. "MT6315_PROC_INT",
  410. "MT6315_GPU_INT",
  411. "UART_SERVO_TX_SCP_RX",
  412. "UART_SCP_TX_SERVO_RX",
  413. "BT_RTS_AP_CTS",
  414. "AP_RTS_BT_CTS",
  415. "UART_AP_WAKE_BT_ODL",
  416. "WLAN_ALERT_ODL",
  417. "EC_IN_RW_ODL",
  418. "H1_AP_INT_ODL",
  419. "",
  420. "",
  421. "",
  422. "",
  423. "",
  424. "",
  425. "",
  426. "",
  427. "",
  428. "",
  429. "",
  430. "MSDC0_CMD",
  431. "MSDC0_DAT0",
  432. "MSDC0_DAT2",
  433. "MSDC0_DAT4",
  434. "MSDC0_DAT6",
  435. "MSDC0_DAT1",
  436. "MSDC0_DAT5",
  437. "MSDC0_DAT7",
  438. "MSDC0_DSL",
  439. "MSDC0_CLK",
  440. "MSDC0_DAT3",
  441. "MSDC0_RST_L",
  442. "SCP_VREQ_VAO",
  443. "AUD_DAT_MOSI2",
  444. "AUD_NLE_MOSI1",
  445. "AUD_NLE_MOSI0",
  446. "AUD_DAT_MISO2",
  447. "AP_I2C_SAR_SDA",
  448. "AP_I2C_SAR_SCL",
  449. "AP_I2C_PWR_SCL",
  450. "AP_I2C_PWR_SDA",
  451. "AP_I2C_TS_SCL_1V8",
  452. "AP_I2C_TS_SDA_1V8",
  453. "SRCLKENA0",
  454. "SRCLKENA1",
  455. "AP_EC_WATCHDOG_L",
  456. "PWRAP_SPI0_MI",
  457. "PWRAP_SPI0_CSN",
  458. "PWRAP_SPI0_MO",
  459. "PWRAP_SPI0_CK",
  460. "AP_RTC_CLK32K",
  461. "AUD_CLK_MOSI",
  462. "AUD_SYNC_MOSI",
  463. "AUD_DAT_MOSI0",
  464. "AUD_DAT_MOSI1",
  465. "AUD_DAT_MISO0",
  466. "AUD_DAT_MISO1";
  467. cr50_int: cr50-irq-default-pins {
  468. pins-gsc-ap-int-odl {
  469. pinmux = <PINMUX_GPIO171__FUNC_GPIO171>;
  470. input-enable;
  471. };
  472. };
  473. cros_ec_int: cros-ec-irq-default-pins {
  474. pins-ec-ap-int-odl {
  475. pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
  476. input-enable;
  477. bias-pull-up;
  478. };
  479. };
  480. i2c0_pins: i2c0-default-pins {
  481. pins-bus {
  482. pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
  483. <PINMUX_GPIO205__FUNC_SDA0>;
  484. bias-pull-up = <MTK_PULL_SET_RSEL_011>;
  485. drive-strength-microamp = <1000>;
  486. };
  487. };
  488. i2c1_pins: i2c1-default-pins {
  489. pins-bus {
  490. pinmux = <PINMUX_GPIO118__FUNC_SCL1>,
  491. <PINMUX_GPIO119__FUNC_SDA1>;
  492. bias-pull-up = <MTK_PULL_SET_RSEL_011>;
  493. drive-strength-microamp = <1000>;
  494. };
  495. };
  496. i2c2_pins: i2c2-default-pins {
  497. pins-bus {
  498. pinmux = <PINMUX_GPIO141__FUNC_SCL2>,
  499. <PINMUX_GPIO142__FUNC_SDA2>;
  500. bias-pull-up = <MTK_PULL_SET_RSEL_011>;
  501. };
  502. };
  503. i2c3_pins: i2c3-default-pins {
  504. pins-bus {
  505. pinmux = <PINMUX_GPIO160__FUNC_SCL3>,
  506. <PINMUX_GPIO161__FUNC_SDA3>;
  507. bias-disable;
  508. drive-strength-microamp = <1000>;
  509. };
  510. };
  511. i2c7_pins: i2c7-default-pins {
  512. pins-bus {
  513. pinmux = <PINMUX_GPIO124__FUNC_SCL7>,
  514. <PINMUX_GPIO125__FUNC_SDA7>;
  515. bias-disable;
  516. drive-strength-microamp = <1000>;
  517. };
  518. };
  519. mmc0_default_pins: mmc0-default-pins {
  520. pins-cmd-dat {
  521. pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
  522. <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
  523. <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
  524. <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
  525. <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
  526. <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
  527. <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
  528. <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
  529. <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
  530. input-enable;
  531. drive-strength = <8>;
  532. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  533. };
  534. pins-clk {
  535. pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
  536. drive-strength = <8>;
  537. bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
  538. };
  539. pins-rst {
  540. pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
  541. drive-strength = <8>;
  542. bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
  543. };
  544. };
  545. mmc0_uhs_pins: mmc0-uhs-pins {
  546. pins-cmd-dat {
  547. pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
  548. <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
  549. <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
  550. <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
  551. <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
  552. <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
  553. <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
  554. <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
  555. <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
  556. input-enable;
  557. drive-strength = <10>;
  558. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  559. };
  560. pins-clk {
  561. pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
  562. drive-strength = <10>;
  563. bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
  564. };
  565. pins-rst {
  566. pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
  567. drive-strength = <8>;
  568. bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
  569. };
  570. pins-ds {
  571. pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>;
  572. drive-strength = <10>;
  573. bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
  574. };
  575. };
  576. mmc1_default_pins: mmc1-default-pins {
  577. pins-cmd-dat {
  578. pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
  579. <PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
  580. <PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
  581. <PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
  582. <PINMUX_GPIO52__FUNC_MSDC1_CMD>;
  583. input-enable;
  584. drive-strength = <8>;
  585. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  586. };
  587. pins-clk {
  588. pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
  589. drive-strength = <8>;
  590. bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
  591. };
  592. pins-insert {
  593. pinmux = <PINMUX_GPIO17__FUNC_GPIO17>;
  594. input-enable;
  595. bias-pull-up;
  596. };
  597. };
  598. mmc1_uhs_pins: mmc1-uhs-pins {
  599. pins-cmd-dat {
  600. pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
  601. <PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
  602. <PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
  603. <PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
  604. <PINMUX_GPIO52__FUNC_MSDC1_CMD>;
  605. input-enable;
  606. drive-strength = <8>;
  607. bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
  608. };
  609. pins-clk {
  610. pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
  611. input-enable;
  612. drive-strength = <8>;
  613. bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
  614. };
  615. };
  616. nor_flash_pins: nor-flash-default-pins {
  617. pins-cs-io1 {
  618. pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>,
  619. <PINMUX_GPIO28__FUNC_SPINOR_IO1>;
  620. input-enable;
  621. bias-pull-up;
  622. drive-strength = <10>;
  623. };
  624. pins-io0 {
  625. pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>;
  626. bias-pull-up;
  627. drive-strength = <10>;
  628. };
  629. pins-clk {
  630. pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>;
  631. input-enable;
  632. bias-pull-up;
  633. drive-strength = <10>;
  634. };
  635. };
  636. pcie_pins: pcie-default-pins {
  637. pins-pcie-wake {
  638. pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
  639. bias-pull-up;
  640. };
  641. pins-pcie-pereset {
  642. pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>;
  643. };
  644. pins-pcie-clkreq {
  645. pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>;
  646. bias-pull-up;
  647. };
  648. pins-wifi-kill {
  649. pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */
  650. output-high;
  651. };
  652. };
  653. pp3300_wlan_pins: pp3300-wlan-pins {
  654. pins-pcie-en-pp3300-wlan {
  655. pinmux = <PINMUX_GPIO143__FUNC_GPIO143>;
  656. output-high;
  657. };
  658. };
  659. scp_pins: scp-pins {
  660. pins-vreq-vao {
  661. pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>;
  662. };
  663. };
  664. spi1_pins: spi1-default-pins {
  665. pins-cs-mosi-clk {
  666. pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
  667. <PINMUX_GPIO159__FUNC_SPI1_A_MO>,
  668. <PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
  669. bias-disable;
  670. };
  671. pins-miso {
  672. pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
  673. bias-pull-down;
  674. };
  675. };
  676. spi5_pins: spi5-default-pins {
  677. pins-bus {
  678. pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>,
  679. <PINMUX_GPIO37__FUNC_GPIO37>,
  680. <PINMUX_GPIO39__FUNC_SPI5_A_MO>,
  681. <PINMUX_GPIO36__FUNC_SPI5_A_CLK>;
  682. bias-disable;
  683. };
  684. };
  685. trackpad_pins: trackpad-default-pins {
  686. pins-int-n {
  687. pinmux = <PINMUX_GPIO15__FUNC_GPIO15>;
  688. input-enable;
  689. bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
  690. };
  691. };
  692. touchscreen_pins: touchscreen-default-pins {
  693. pins-irq {
  694. pinmux = <PINMUX_GPIO21__FUNC_GPIO21>;
  695. input-enable;
  696. bias-pull-up;
  697. };
  698. pins-reset {
  699. pinmux = <PINMUX_GPIO137__FUNC_GPIO137>;
  700. output-high;
  701. };
  702. pins-report-sw {
  703. pinmux = <PINMUX_GPIO138__FUNC_GPIO138>;
  704. output-low;
  705. };
  706. };
  707. };
  708. &pmic {
  709. interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>;
  710. };
  711. &scp {
  712. status = "okay";
  713. firmware-name = "mediatek/mt8192/scp.img";
  714. memory-region = <&scp_mem_reserved>;
  715. pinctrl-names = "default";
  716. pinctrl-0 = <&scp_pins>;
  717. cros-ec {
  718. compatible = "google,cros-ec-rpmsg";
  719. mediatek,rpmsg-name = "cros-ec-rpmsg";
  720. };
  721. };
  722. &spi1 {
  723. status = "okay";
  724. mediatek,pad-select = <0>;
  725. pinctrl-names = "default";
  726. pinctrl-0 = <&spi1_pins>;
  727. cros_ec: ec@0 {
  728. compatible = "google,cros-ec-spi";
  729. reg = <0>;
  730. interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>;
  731. spi-max-frequency = <3000000>;
  732. pinctrl-names = "default";
  733. pinctrl-0 = <&cros_ec_int>;
  734. #address-cells = <1>;
  735. #size-cells = <0>;
  736. base_detection: cbas {
  737. compatible = "google,cros-cbas";
  738. };
  739. cros_ec_pwm: pwm {
  740. compatible = "google,cros-ec-pwm";
  741. #pwm-cells = <1>;
  742. status = "disabled";
  743. };
  744. i2c_tunnel: i2c-tunnel {
  745. compatible = "google,cros-ec-i2c-tunnel";
  746. google,remote-bus = <0>;
  747. #address-cells = <1>;
  748. #size-cells = <0>;
  749. };
  750. mt6360_ldo3_reg: regulator@0 {
  751. compatible = "google,cros-ec-regulator";
  752. reg = <0>;
  753. regulator-min-microvolt = <1800000>;
  754. regulator-max-microvolt = <3300000>;
  755. };
  756. mt6360_ldo5_reg: regulator@1 {
  757. compatible = "google,cros-ec-regulator";
  758. reg = <1>;
  759. regulator-min-microvolt = <3300000>;
  760. regulator-max-microvolt = <3300000>;
  761. };
  762. typec {
  763. compatible = "google,cros-ec-typec";
  764. #address-cells = <1>;
  765. #size-cells = <0>;
  766. usb_c0: connector@0 {
  767. compatible = "usb-c-connector";
  768. reg = <0>;
  769. label = "left";
  770. power-role = "dual";
  771. data-role = "host";
  772. try-power-role = "source";
  773. };
  774. usb_c1: connector@1 {
  775. compatible = "usb-c-connector";
  776. reg = <1>;
  777. label = "right";
  778. power-role = "dual";
  779. data-role = "host";
  780. try-power-role = "source";
  781. };
  782. };
  783. };
  784. };
  785. &spi5 {
  786. status = "okay";
  787. cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>;
  788. mediatek,pad-select = <0>;
  789. pinctrl-names = "default";
  790. pinctrl-0 = <&spi5_pins>;
  791. cr50@0 {
  792. compatible = "google,cr50";
  793. reg = <0>;
  794. interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>;
  795. spi-max-frequency = <1000000>;
  796. pinctrl-names = "default";
  797. pinctrl-0 = <&cr50_int>;
  798. };
  799. };
  800. &spmi {
  801. #address-cells = <2>;
  802. #size-cells = <0>;
  803. mt6315_6: pmic@6 {
  804. compatible = "mediatek,mt6315-regulator";
  805. reg = <0x6 SPMI_USID>;
  806. regulators {
  807. mt6315_6_vbuck1: vbuck1 {
  808. regulator-compatible = "vbuck1";
  809. regulator-name = "Vbcpu";
  810. regulator-min-microvolt = <300000>;
  811. regulator-max-microvolt = <1193750>;
  812. regulator-enable-ramp-delay = <256>;
  813. regulator-allowed-modes = <0 1 2>;
  814. regulator-always-on;
  815. };
  816. mt6315_6_vbuck3: vbuck3 {
  817. regulator-compatible = "vbuck3";
  818. regulator-name = "Vlcpu";
  819. regulator-min-microvolt = <300000>;
  820. regulator-max-microvolt = <1193750>;
  821. regulator-enable-ramp-delay = <256>;
  822. regulator-allowed-modes = <0 1 2>;
  823. regulator-always-on;
  824. };
  825. };
  826. };
  827. mt6315_7: pmic@7 {
  828. compatible = "mediatek,mt6315-regulator";
  829. reg = <0x7 SPMI_USID>;
  830. regulators {
  831. mt6315_7_vbuck1: vbuck1 {
  832. regulator-compatible = "vbuck1";
  833. regulator-name = "Vgpu";
  834. regulator-min-microvolt = <606250>;
  835. regulator-max-microvolt = <800000>;
  836. regulator-enable-ramp-delay = <256>;
  837. regulator-allowed-modes = <0 1 2>;
  838. };
  839. };
  840. };
  841. };
  842. &uart0 {
  843. status = "okay";
  844. };
  845. &xhci {
  846. status = "okay";
  847. wakeup-source;
  848. vusb33-supply = <&pp3300_g>;
  849. vbus-supply = <&pp5000_a>;
  850. };
  851. #include <arm/cros-ec-keyboard.dtsi>
  852. #include <arm/cros-ec-sbs.dtsi>