mt8183-pumpkin.dts 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2021 BayLibre, SAS.
  4. * Author: Fabien Parent <[email protected]>
  5. */
  6. /dts-v1/;
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/input/input.h>
  9. #include "mt8183.dtsi"
  10. #include "mt6358.dtsi"
  11. / {
  12. model = "Pumpkin MT8183";
  13. compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183";
  14. aliases {
  15. serial0 = &uart0;
  16. };
  17. memory@40000000 {
  18. device_type = "memory";
  19. reg = <0 0x40000000 0 0x80000000>;
  20. };
  21. chosen {
  22. stdout-path = "serial0:921600n8";
  23. };
  24. reserved-memory {
  25. #address-cells = <2>;
  26. #size-cells = <2>;
  27. ranges;
  28. scp_mem_reserved: scp_mem_region@50000000 {
  29. compatible = "shared-dma-pool";
  30. reg = <0 0x50000000 0 0x2900000>;
  31. no-map;
  32. };
  33. };
  34. leds {
  35. compatible = "gpio-leds";
  36. led-red {
  37. label = "red";
  38. gpios = <&pio 155 GPIO_ACTIVE_HIGH>;
  39. default-state = "off";
  40. };
  41. led-green {
  42. label = "green";
  43. gpios = <&pio 156 GPIO_ACTIVE_HIGH>;
  44. default-state = "off";
  45. };
  46. };
  47. thermistor {
  48. compatible = "murata,ncp03wf104";
  49. pullup-uv = <1800000>;
  50. pullup-ohm = <390000>;
  51. pulldown-ohm = <0>;
  52. io-channels = <&auxadc 0>;
  53. };
  54. };
  55. &auxadc {
  56. status = "okay";
  57. };
  58. &gpu {
  59. mali-supply = <&mt6358_vgpu_reg>;
  60. sram-supply = <&mt6358_vsram_gpu_reg>;
  61. };
  62. &i2c0 {
  63. pinctrl-names = "default";
  64. pinctrl-0 = <&i2c_pins_0>;
  65. status = "okay";
  66. clock-frequency = <100000>;
  67. };
  68. &i2c1 {
  69. pinctrl-names = "default";
  70. pinctrl-0 = <&i2c_pins_1>;
  71. status = "okay";
  72. clock-frequency = <100000>;
  73. };
  74. &i2c2 {
  75. pinctrl-names = "default";
  76. pinctrl-0 = <&i2c_pins_2>;
  77. status = "okay";
  78. clock-frequency = <100000>;
  79. };
  80. &i2c3 {
  81. pinctrl-names = "default";
  82. pinctrl-0 = <&i2c_pins_3>;
  83. status = "okay";
  84. clock-frequency = <100000>;
  85. };
  86. &i2c4 {
  87. pinctrl-names = "default";
  88. pinctrl-0 = <&i2c_pins_4>;
  89. status = "okay";
  90. clock-frequency = <100000>;
  91. };
  92. &i2c5 {
  93. pinctrl-names = "default";
  94. pinctrl-0 = <&i2c_pins_5>;
  95. status = "okay";
  96. clock-frequency = <100000>;
  97. };
  98. &i2c6 {
  99. pinctrl-names = "default";
  100. pinctrl-0 = <&i2c6_pins>;
  101. status = "okay";
  102. clock-frequency = <100000>;
  103. };
  104. &keyboard {
  105. pinctrl-names = "default";
  106. pinctrl-0 = <&keyboard_pins>;
  107. status = "okay";
  108. linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_VOLUMEDOWN)
  109. MATRIX_KEY(0x01, 0x00, KEY_VOLUMEUP)>;
  110. keypad,num-rows = <2>;
  111. keypad,num-columns = <1>;
  112. debounce-delay-ms = <32>;
  113. mediatek,keys-per-group = <2>;
  114. };
  115. &mmc0 {
  116. status = "okay";
  117. pinctrl-names = "default", "state_uhs";
  118. pinctrl-0 = <&mmc0_pins_default>;
  119. pinctrl-1 = <&mmc0_pins_uhs>;
  120. bus-width = <8>;
  121. max-frequency = <200000000>;
  122. cap-mmc-highspeed;
  123. mmc-hs200-1_8v;
  124. mmc-hs400-1_8v;
  125. cap-mmc-hw-reset;
  126. no-sdio;
  127. no-sd;
  128. hs400-ds-delay = <0x12814>;
  129. vmmc-supply = <&mt6358_vemc_reg>;
  130. vqmmc-supply = <&mt6358_vio18_reg>;
  131. assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
  132. assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
  133. non-removable;
  134. };
  135. &mmc1 {
  136. status = "okay";
  137. pinctrl-names = "default", "state_uhs";
  138. pinctrl-0 = <&mmc1_pins_default>;
  139. pinctrl-1 = <&mmc1_pins_uhs>;
  140. bus-width = <4>;
  141. max-frequency = <200000000>;
  142. cap-sd-highspeed;
  143. sd-uhs-sdr50;
  144. sd-uhs-sdr104;
  145. cap-sdio-irq;
  146. no-mmc;
  147. no-sd;
  148. vmmc-supply = <&mt6358_vmch_reg>;
  149. vqmmc-supply = <&mt6358_vmc_reg>;
  150. keep-power-in-suspend;
  151. wakeup-source;
  152. non-removable;
  153. };
  154. &pio {
  155. i2c_pins_0: i2c0 {
  156. pins_i2c {
  157. pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
  158. <PINMUX_GPIO83__FUNC_SCL0>;
  159. mediatek,pull-up-adv = <3>;
  160. mediatek,drive-strength-adv = <00>;
  161. };
  162. };
  163. i2c_pins_1: i2c1 {
  164. pins_i2c {
  165. pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
  166. <PINMUX_GPIO84__FUNC_SCL1>;
  167. mediatek,pull-up-adv = <3>;
  168. mediatek,drive-strength-adv = <00>;
  169. };
  170. };
  171. i2c_pins_2: i2c2 {
  172. pins_i2c {
  173. pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
  174. <PINMUX_GPIO104__FUNC_SDA2>;
  175. mediatek,pull-up-adv = <3>;
  176. mediatek,drive-strength-adv = <00>;
  177. };
  178. };
  179. i2c_pins_3: i2c3 {
  180. pins_i2c {
  181. pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
  182. <PINMUX_GPIO51__FUNC_SDA3>;
  183. mediatek,pull-up-adv = <3>;
  184. mediatek,drive-strength-adv = <00>;
  185. };
  186. };
  187. i2c_pins_4: i2c4 {
  188. pins_i2c {
  189. pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
  190. <PINMUX_GPIO106__FUNC_SDA4>;
  191. mediatek,pull-up-adv = <3>;
  192. mediatek,drive-strength-adv = <00>;
  193. };
  194. };
  195. i2c_pins_5: i2c5 {
  196. pins_i2c {
  197. pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
  198. <PINMUX_GPIO49__FUNC_SDA5>;
  199. mediatek,pull-up-adv = <3>;
  200. mediatek,drive-strength-adv = <00>;
  201. };
  202. };
  203. i2c6_pins: i2c6 {
  204. pins_cmd_dat {
  205. pinmux = <PINMUX_GPIO113__FUNC_SCL6>,
  206. <PINMUX_GPIO114__FUNC_SDA6>;
  207. mediatek,pull-up-adv = <3>;
  208. };
  209. };
  210. keyboard_pins: keyboard {
  211. pins_keyboard {
  212. pinmux = <PINMUX_GPIO91__FUNC_KPROW1>,
  213. <PINMUX_GPIO92__FUNC_KPROW0>,
  214. <PINMUX_GPIO93__FUNC_KPCOL0>;
  215. };
  216. };
  217. mmc0_pins_default: mmc0-pins-default {
  218. pins_cmd_dat {
  219. pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
  220. <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
  221. <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
  222. <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
  223. <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
  224. <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
  225. <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
  226. <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
  227. <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
  228. input-enable;
  229. drive-strength = <MTK_DRIVE_14mA>;
  230. mediatek,pull-up-adv = <01>;
  231. };
  232. pins_clk {
  233. pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
  234. drive-strength = <MTK_DRIVE_14mA>;
  235. mediatek,pull-down-adv = <10>;
  236. };
  237. pins_rst {
  238. pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
  239. drive-strength = <MTK_DRIVE_14mA>;
  240. mediatek,pull-down-adv = <01>;
  241. };
  242. };
  243. mmc0_pins_uhs: mmc0-pins-uhs {
  244. pins_cmd_dat {
  245. pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
  246. <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
  247. <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
  248. <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
  249. <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
  250. <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
  251. <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
  252. <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
  253. <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
  254. input-enable;
  255. drive-strength = <MTK_DRIVE_14mA>;
  256. mediatek,pull-up-adv = <01>;
  257. };
  258. pins_clk {
  259. pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
  260. drive-strength = <MTK_DRIVE_14mA>;
  261. mediatek,pull-down-adv = <10>;
  262. };
  263. pins_ds {
  264. pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
  265. drive-strength = <MTK_DRIVE_14mA>;
  266. mediatek,pull-down-adv = <10>;
  267. };
  268. pins_rst {
  269. pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
  270. drive-strength = <MTK_DRIVE_14mA>;
  271. mediatek,pull-up-adv = <01>;
  272. };
  273. };
  274. mmc1_pins_default: mmc1-pins-default {
  275. pins_cmd_dat {
  276. pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
  277. <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
  278. <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
  279. <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
  280. <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
  281. input-enable;
  282. mediatek,pull-up-adv = <10>;
  283. };
  284. pins_clk {
  285. pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
  286. input-enable;
  287. mediatek,pull-down-adv = <10>;
  288. };
  289. pins_pmu {
  290. pinmux = <PINMUX_GPIO178__FUNC_GPIO178>;
  291. output-high;
  292. };
  293. };
  294. mmc1_pins_uhs: mmc1-pins-uhs {
  295. pins_cmd_dat {
  296. pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
  297. <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
  298. <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
  299. <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
  300. <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
  301. drive-strength = <MTK_DRIVE_6mA>;
  302. input-enable;
  303. mediatek,pull-up-adv = <10>;
  304. };
  305. pins_clk {
  306. pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
  307. drive-strength = <MTK_DRIVE_8mA>;
  308. mediatek,pull-down-adv = <10>;
  309. input-enable;
  310. };
  311. };
  312. };
  313. &mfg {
  314. domain-supply = <&mt6358_vgpu_reg>;
  315. };
  316. &cpu0 {
  317. proc-supply = <&mt6358_vproc12_reg>;
  318. };
  319. &cpu1 {
  320. proc-supply = <&mt6358_vproc12_reg>;
  321. };
  322. &cpu2 {
  323. proc-supply = <&mt6358_vproc12_reg>;
  324. };
  325. &cpu3 {
  326. proc-supply = <&mt6358_vproc12_reg>;
  327. };
  328. &cpu4 {
  329. proc-supply = <&mt6358_vproc11_reg>;
  330. };
  331. &cpu5 {
  332. proc-supply = <&mt6358_vproc11_reg>;
  333. };
  334. &cpu6 {
  335. proc-supply = <&mt6358_vproc11_reg>;
  336. };
  337. &cpu7 {
  338. proc-supply = <&mt6358_vproc11_reg>;
  339. };
  340. &uart0 {
  341. status = "okay";
  342. };
  343. &scp {
  344. status = "okay";
  345. };
  346. &dsi0 {
  347. status = "disabled";
  348. };