mt8183-kukui.dtsi 20 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright (c) 2018 MediaTek Inc.
  4. * Author: Ben Ho <[email protected]>
  5. * Erin Lo <[email protected]>
  6. */
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/input/input.h>
  9. #include "mt8183.dtsi"
  10. #include "mt6358.dtsi"
  11. / {
  12. aliases {
  13. serial0 = &uart0;
  14. mmc0 = &mmc0;
  15. mmc1 = &mmc1;
  16. };
  17. chosen {
  18. stdout-path = "serial0:115200n8";
  19. };
  20. backlight_lcd0: backlight_lcd0 {
  21. compatible = "pwm-backlight";
  22. pwms = <&pwm0 0 500000>;
  23. power-supply = <&bl_pp5000>;
  24. enable-gpios = <&pio 176 0>;
  25. brightness-levels = <0 1023>;
  26. num-interpolated-steps = <1023>;
  27. default-brightness-level = <576>;
  28. status = "okay";
  29. };
  30. memory@40000000 {
  31. device_type = "memory";
  32. reg = <0 0x40000000 0 0x80000000>;
  33. };
  34. clk32k: oscillator1 {
  35. compatible = "fixed-clock";
  36. #clock-cells = <0>;
  37. clock-frequency = <32768>;
  38. clock-output-names = "clk32k";
  39. };
  40. it6505_pp18_reg: regulator0 {
  41. compatible = "regulator-fixed";
  42. regulator-name = "it6505_pp18";
  43. regulator-min-microvolt = <1800000>;
  44. regulator-max-microvolt = <1800000>;
  45. gpio = <&pio 178 0>;
  46. enable-active-high;
  47. };
  48. lcd_pp3300: regulator1 {
  49. compatible = "regulator-fixed";
  50. regulator-name = "lcd_pp3300";
  51. regulator-min-microvolt = <3300000>;
  52. regulator-max-microvolt = <3300000>;
  53. regulator-always-on;
  54. regulator-boot-on;
  55. };
  56. bl_pp5000: regulator2 {
  57. compatible = "regulator-fixed";
  58. regulator-name = "bl_pp5000";
  59. regulator-min-microvolt = <5000000>;
  60. regulator-max-microvolt = <5000000>;
  61. regulator-always-on;
  62. regulator-boot-on;
  63. };
  64. mmc1_fixed_power: regulator3 {
  65. compatible = "regulator-fixed";
  66. regulator-name = "mmc1_power";
  67. regulator-min-microvolt = <3300000>;
  68. regulator-max-microvolt = <3300000>;
  69. };
  70. mmc1_fixed_io: regulator4 {
  71. compatible = "regulator-fixed";
  72. regulator-name = "mmc1_io";
  73. regulator-min-microvolt = <1800000>;
  74. regulator-max-microvolt = <1800000>;
  75. };
  76. pp1800_alw: regulator5 {
  77. compatible = "regulator-fixed";
  78. regulator-name = "pp1800_alw";
  79. regulator-always-on;
  80. regulator-boot-on;
  81. regulator-min-microvolt = <1800000>;
  82. regulator-max-microvolt = <1800000>;
  83. };
  84. pp3300_alw: regulator6 {
  85. compatible = "regulator-fixed";
  86. regulator-name = "pp3300_alw";
  87. regulator-always-on;
  88. regulator-boot-on;
  89. regulator-min-microvolt = <3300000>;
  90. regulator-max-microvolt = <3300000>;
  91. };
  92. reserved_memory: reserved-memory {
  93. #address-cells = <2>;
  94. #size-cells = <2>;
  95. ranges;
  96. scp_mem_reserved: memory@50000000 {
  97. compatible = "shared-dma-pool";
  98. reg = <0 0x50000000 0 0x2900000>;
  99. no-map;
  100. };
  101. };
  102. sound: mt8183-sound {
  103. mediatek,platform = <&afe>;
  104. pinctrl-names = "default",
  105. "aud_tdm_out_on",
  106. "aud_tdm_out_off";
  107. pinctrl-0 = <&aud_pins_default>;
  108. pinctrl-1 = <&aud_pins_tdm_out_on>;
  109. pinctrl-2 = <&aud_pins_tdm_out_off>;
  110. status = "okay";
  111. };
  112. btsco: bt-sco {
  113. compatible = "linux,bt-sco";
  114. };
  115. wifi_pwrseq: wifi-pwrseq {
  116. compatible = "mmc-pwrseq-simple";
  117. pinctrl-names = "default";
  118. pinctrl-0 = <&wifi_pins_pwrseq>;
  119. /* Toggle WIFI_ENABLE to reset the chip. */
  120. reset-gpios = <&pio 119 1>;
  121. };
  122. wifi_wakeup: wifi-wakeup {
  123. compatible = "gpio-keys";
  124. pinctrl-names = "default";
  125. pinctrl-0 = <&wifi_pins_wakeup>;
  126. button-wowlan {
  127. label = "Wake on WiFi";
  128. gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
  129. linux,code = <KEY_WAKEUP>;
  130. wakeup-source;
  131. };
  132. };
  133. tboard_thermistor1: thermal-sensor1 {
  134. compatible = "generic-adc-thermal";
  135. #thermal-sensor-cells = <0>;
  136. io-channels = <&auxadc 0>;
  137. io-channel-names = "sensor-channel";
  138. temperature-lookup-table = < (-5000) 1553
  139. 0 1488
  140. 5000 1412
  141. 10000 1326
  142. 15000 1232
  143. 20000 1132
  144. 25000 1029
  145. 30000 925
  146. 35000 823
  147. 40000 726
  148. 45000 635
  149. 50000 552
  150. 55000 478
  151. 60000 411
  152. 65000 353
  153. 70000 303
  154. 75000 260
  155. 80000 222
  156. 85000 190
  157. 90000 163
  158. 95000 140
  159. 100000 121
  160. 105000 104
  161. 110000 90
  162. 115000 78
  163. 120000 67
  164. 125000 59>;
  165. };
  166. tboard_thermistor2: thermal-sensor2 {
  167. compatible = "generic-adc-thermal";
  168. #thermal-sensor-cells = <0>;
  169. io-channels = <&auxadc 1>;
  170. io-channel-names = "sensor-channel";
  171. temperature-lookup-table = < (-5000) 1553
  172. 0 1488
  173. 5000 1412
  174. 10000 1326
  175. 15000 1232
  176. 20000 1132
  177. 25000 1029
  178. 30000 925
  179. 35000 823
  180. 40000 726
  181. 45000 635
  182. 50000 552
  183. 55000 478
  184. 60000 411
  185. 65000 353
  186. 70000 303
  187. 75000 260
  188. 80000 222
  189. 85000 190
  190. 90000 163
  191. 95000 140
  192. 100000 121
  193. 105000 104
  194. 110000 90
  195. 115000 78
  196. 120000 67
  197. 125000 59>;
  198. };
  199. };
  200. &afe {
  201. i2s3-share = "I2S2";
  202. i2s0-share = "I2S5";
  203. };
  204. &auxadc {
  205. status = "okay";
  206. };
  207. &cci {
  208. proc-supply = <&mt6358_vproc12_reg>;
  209. };
  210. &cpu0 {
  211. proc-supply = <&mt6358_vproc12_reg>;
  212. };
  213. &cpu1 {
  214. proc-supply = <&mt6358_vproc12_reg>;
  215. };
  216. &cpu2 {
  217. proc-supply = <&mt6358_vproc12_reg>;
  218. };
  219. &cpu3 {
  220. proc-supply = <&mt6358_vproc12_reg>;
  221. };
  222. &cpu4 {
  223. proc-supply = <&mt6358_vproc11_reg>;
  224. };
  225. &cpu5 {
  226. proc-supply = <&mt6358_vproc11_reg>;
  227. };
  228. &cpu6 {
  229. proc-supply = <&mt6358_vproc11_reg>;
  230. };
  231. &cpu7 {
  232. proc-supply = <&mt6358_vproc11_reg>;
  233. };
  234. &dsi0 {
  235. status = "okay";
  236. #address-cells = <1>;
  237. #size-cells = <0>;
  238. panel: panel@0 {
  239. /* compatible will be set in board dts */
  240. reg = <0>;
  241. enable-gpios = <&pio 45 0>;
  242. pinctrl-names = "default";
  243. pinctrl-0 = <&panel_pins_default>;
  244. avdd-supply = <&ppvarn_lcd>;
  245. avee-supply = <&ppvarp_lcd>;
  246. pp1800-supply = <&pp1800_lcd>;
  247. backlight = <&backlight_lcd0>;
  248. rotation = <270>;
  249. port {
  250. panel_in: endpoint {
  251. remote-endpoint = <&dsi_out>;
  252. };
  253. };
  254. };
  255. ports {
  256. port {
  257. dsi_out: endpoint {
  258. remote-endpoint = <&panel_in>;
  259. };
  260. };
  261. };
  262. };
  263. &gic {
  264. mediatek,broken-save-restore-fw;
  265. };
  266. &gpu {
  267. mali-supply = <&mt6358_vgpu_reg>;
  268. sram-supply = <&mt6358_vsram_gpu_reg>;
  269. };
  270. &i2c0 {
  271. pinctrl-names = "default";
  272. pinctrl-0 = <&i2c0_pins>;
  273. status = "okay";
  274. clock-frequency = <400000>;
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. };
  278. &i2c1 {
  279. pinctrl-names = "default";
  280. pinctrl-0 = <&i2c1_pins>;
  281. status = "okay";
  282. clock-frequency = <100000>;
  283. };
  284. &i2c3 {
  285. pinctrl-names = "default";
  286. pinctrl-0 = <&i2c3_pins>;
  287. status = "okay";
  288. clock-frequency = <100000>;
  289. #address-cells = <1>;
  290. #size-cells = <0>;
  291. };
  292. &i2c5 {
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&i2c5_pins>;
  295. status = "okay";
  296. clock-frequency = <100000>;
  297. #address-cells = <1>;
  298. #size-cells = <0>;
  299. };
  300. &i2c6 {
  301. pinctrl-names = "default";
  302. pinctrl-0 = <&i2c6_pins>;
  303. status = "okay";
  304. clock-frequency = <100000>;
  305. };
  306. &mipi_tx0 {
  307. status = "okay";
  308. };
  309. &mmc0 {
  310. status = "okay";
  311. pinctrl-names = "default", "state_uhs";
  312. pinctrl-0 = <&mmc0_pins_default>;
  313. pinctrl-1 = <&mmc0_pins_uhs>;
  314. bus-width = <8>;
  315. max-frequency = <200000000>;
  316. cap-mmc-highspeed;
  317. mmc-hs200-1_8v;
  318. mmc-hs400-1_8v;
  319. cap-mmc-hw-reset;
  320. no-sdio;
  321. no-sd;
  322. hs400-ds-delay = <0x12814>;
  323. vmmc-supply = <&mt6358_vemc_reg>;
  324. vqmmc-supply = <&mt6358_vio18_reg>;
  325. assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
  326. assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
  327. non-removable;
  328. };
  329. &mmc1 {
  330. status = "okay";
  331. pinctrl-names = "default", "state_uhs";
  332. pinctrl-0 = <&mmc1_pins_default>;
  333. pinctrl-1 = <&mmc1_pins_uhs>;
  334. vmmc-supply = <&mmc1_fixed_power>;
  335. vqmmc-supply = <&mmc1_fixed_io>;
  336. mmc-pwrseq = <&wifi_pwrseq>;
  337. bus-width = <4>;
  338. max-frequency = <200000000>;
  339. drv-type = <2>;
  340. cap-sd-highspeed;
  341. sd-uhs-sdr50;
  342. sd-uhs-sdr104;
  343. keep-power-in-suspend;
  344. wakeup-source;
  345. cap-sdio-irq;
  346. non-removable;
  347. no-mmc;
  348. no-sd;
  349. assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
  350. assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
  351. #address-cells = <1>;
  352. #size-cells = <0>;
  353. qca_wifi: qca-wifi@1 {
  354. compatible = "qcom,ath10k";
  355. reg = <1>;
  356. };
  357. };
  358. &mt6358_vdram2_reg {
  359. regulator-always-on;
  360. };
  361. &mt6358codec {
  362. Avdd-supply = <&mt6358_vaud28_reg>;
  363. };
  364. &mt6358_vsim1_reg {
  365. regulator-min-microvolt = <2700000>;
  366. regulator-max-microvolt = <2700000>;
  367. };
  368. &mt6358_vsim2_reg {
  369. regulator-min-microvolt = <2700000>;
  370. regulator-max-microvolt = <2700000>;
  371. };
  372. &pio {
  373. aud_pins_default: audiopins {
  374. pins-bus {
  375. pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
  376. <PINMUX_GPIO98__FUNC_I2S2_BCK>,
  377. <PINMUX_GPIO101__FUNC_I2S2_LRCK>,
  378. <PINMUX_GPIO102__FUNC_I2S2_DI>,
  379. <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/
  380. <PINMUX_GPIO89__FUNC_I2S5_BCK>,
  381. <PINMUX_GPIO90__FUNC_I2S5_LRCK>,
  382. <PINMUX_GPIO91__FUNC_I2S5_DO>,
  383. <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/
  384. <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>,
  385. <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>,
  386. <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>,
  387. <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>,
  388. <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>,
  389. <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>,
  390. <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>,
  391. <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/
  392. };
  393. };
  394. aud_pins_tdm_out_on: audiotdmouton {
  395. pins-bus {
  396. pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
  397. <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
  398. <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
  399. <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>,
  400. <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>,
  401. <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/
  402. drive-strength = <MTK_DRIVE_6mA>;
  403. };
  404. };
  405. aud_pins_tdm_out_off: audiotdmoutoff {
  406. pins-bus {
  407. pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
  408. <PINMUX_GPIO170__FUNC_GPIO170>,
  409. <PINMUX_GPIO171__FUNC_GPIO171>,
  410. <PINMUX_GPIO172__FUNC_GPIO172>,
  411. <PINMUX_GPIO173__FUNC_GPIO173>,
  412. <PINMUX_GPIO10__FUNC_GPIO10>;
  413. input-enable;
  414. bias-pull-down;
  415. drive-strength = <MTK_DRIVE_2mA>;
  416. };
  417. };
  418. bt_pins: bt-pins {
  419. pins-bt-en {
  420. pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
  421. output-low;
  422. };
  423. };
  424. ec_ap_int_odl: ec-ap-int-odl {
  425. pins1 {
  426. pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
  427. input-enable;
  428. bias-pull-up;
  429. };
  430. };
  431. h1_int_od_l: h1-int-od-l {
  432. pins1 {
  433. pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
  434. input-enable;
  435. };
  436. };
  437. i2c0_pins: i2c0 {
  438. pins-bus {
  439. pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
  440. <PINMUX_GPIO83__FUNC_SCL0>;
  441. mediatek,pull-up-adv = <3>;
  442. mediatek,drive-strength-adv = <00>;
  443. };
  444. };
  445. i2c1_pins: i2c1 {
  446. pins-bus {
  447. pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
  448. <PINMUX_GPIO84__FUNC_SCL1>;
  449. mediatek,pull-up-adv = <3>;
  450. mediatek,drive-strength-adv = <00>;
  451. };
  452. };
  453. i2c2_pins: i2c2 {
  454. pins-bus {
  455. pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
  456. <PINMUX_GPIO104__FUNC_SDA2>;
  457. bias-disable;
  458. mediatek,drive-strength-adv = <00>;
  459. };
  460. };
  461. i2c3_pins: i2c3 {
  462. pins-bus {
  463. pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
  464. <PINMUX_GPIO51__FUNC_SDA3>;
  465. mediatek,pull-up-adv = <3>;
  466. mediatek,drive-strength-adv = <00>;
  467. };
  468. };
  469. i2c4_pins: i2c4 {
  470. pins-bus {
  471. pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
  472. <PINMUX_GPIO106__FUNC_SDA4>;
  473. bias-disable;
  474. mediatek,drive-strength-adv = <00>;
  475. };
  476. };
  477. i2c5_pins: i2c5 {
  478. pins-bus {
  479. pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
  480. <PINMUX_GPIO49__FUNC_SDA5>;
  481. mediatek,pull-up-adv = <3>;
  482. mediatek,drive-strength-adv = <00>;
  483. };
  484. };
  485. i2c6_pins: i2c6 {
  486. pins-bus {
  487. pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
  488. <PINMUX_GPIO12__FUNC_SDA6>;
  489. bias-disable;
  490. };
  491. };
  492. mmc0_pins_default: mmc0-pins-default {
  493. pins-cmd-dat {
  494. pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
  495. <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
  496. <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
  497. <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
  498. <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
  499. <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
  500. <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
  501. <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
  502. <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
  503. input-enable;
  504. drive-strength = <MTK_DRIVE_14mA>;
  505. mediatek,pull-up-adv = <01>;
  506. };
  507. pins-clk {
  508. pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
  509. drive-strength = <MTK_DRIVE_14mA>;
  510. mediatek,pull-down-adv = <10>;
  511. };
  512. pins-rst {
  513. pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
  514. drive-strength = <MTK_DRIVE_14mA>;
  515. mediatek,pull-down-adv = <01>;
  516. };
  517. };
  518. mmc0_pins_uhs: mmc0-pins-uhs {
  519. pins-cmd-dat {
  520. pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
  521. <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
  522. <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
  523. <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
  524. <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
  525. <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
  526. <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
  527. <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
  528. <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
  529. input-enable;
  530. drive-strength = <MTK_DRIVE_14mA>;
  531. mediatek,pull-up-adv = <01>;
  532. };
  533. pins-clk {
  534. pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
  535. drive-strength = <MTK_DRIVE_14mA>;
  536. mediatek,pull-down-adv = <10>;
  537. };
  538. pins-ds {
  539. pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
  540. drive-strength = <MTK_DRIVE_14mA>;
  541. mediatek,pull-down-adv = <10>;
  542. };
  543. pins-rst {
  544. pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
  545. drive-strength = <MTK_DRIVE_14mA>;
  546. mediatek,pull-up-adv = <01>;
  547. };
  548. };
  549. mmc1_pins_default: mmc1-pins-default {
  550. pins-cmd-dat {
  551. pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
  552. <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
  553. <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
  554. <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
  555. <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
  556. input-enable;
  557. mediatek,pull-up-adv = <10>;
  558. };
  559. pins-clk {
  560. pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
  561. input-enable;
  562. mediatek,pull-down-adv = <10>;
  563. };
  564. };
  565. mmc1_pins_uhs: mmc1-pins-uhs {
  566. pins-cmd-dat {
  567. pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
  568. <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
  569. <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
  570. <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
  571. <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
  572. drive-strength = <MTK_DRIVE_6mA>;
  573. input-enable;
  574. mediatek,pull-up-adv = <10>;
  575. };
  576. pins-clk {
  577. pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
  578. drive-strength = <MTK_DRIVE_8mA>;
  579. mediatek,pull-down-adv = <10>;
  580. input-enable;
  581. };
  582. };
  583. panel_pins_default: panel-pins-default {
  584. panel-reset {
  585. pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
  586. output-low;
  587. bias-pull-up;
  588. };
  589. };
  590. pwm0_pin_default: pwm0-pin-default {
  591. pins1 {
  592. pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
  593. output-high;
  594. bias-pull-up;
  595. };
  596. pins2 {
  597. pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>;
  598. };
  599. };
  600. scp_pins: scp {
  601. pins-scp-uart {
  602. pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
  603. <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
  604. };
  605. };
  606. spi0_pins: spi0 {
  607. pins-spi {
  608. pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
  609. <PINMUX_GPIO86__FUNC_GPIO86>,
  610. <PINMUX_GPIO87__FUNC_SPI0_MO>,
  611. <PINMUX_GPIO88__FUNC_SPI0_CLK>;
  612. bias-disable;
  613. };
  614. };
  615. spi1_pins: spi1 {
  616. pins-spi {
  617. pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
  618. <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
  619. <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
  620. <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
  621. bias-disable;
  622. };
  623. };
  624. spi2_pins: spi2 {
  625. pins-spi {
  626. pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
  627. <PINMUX_GPIO1__FUNC_SPI2_MO>,
  628. <PINMUX_GPIO2__FUNC_SPI2_CLK>;
  629. bias-disable;
  630. };
  631. pins-spi-mi {
  632. pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
  633. mediatek,pull-down-adv = <00>;
  634. };
  635. };
  636. spi3_pins: spi3 {
  637. pins-spi {
  638. pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
  639. <PINMUX_GPIO22__FUNC_SPI3_CSB>,
  640. <PINMUX_GPIO23__FUNC_SPI3_MO>,
  641. <PINMUX_GPIO24__FUNC_SPI3_CLK>;
  642. bias-disable;
  643. };
  644. };
  645. spi4_pins: spi4 {
  646. pins-spi {
  647. pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
  648. <PINMUX_GPIO18__FUNC_SPI4_CSB>,
  649. <PINMUX_GPIO19__FUNC_SPI4_MO>,
  650. <PINMUX_GPIO20__FUNC_SPI4_CLK>;
  651. bias-disable;
  652. };
  653. };
  654. spi5_pins: spi5 {
  655. pins-spi {
  656. pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
  657. <PINMUX_GPIO14__FUNC_SPI5_CSB>,
  658. <PINMUX_GPIO15__FUNC_SPI5_MO>,
  659. <PINMUX_GPIO16__FUNC_SPI5_CLK>;
  660. bias-disable;
  661. };
  662. };
  663. uart0_pins_default: uart0-pins-default {
  664. pins-rx {
  665. pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
  666. input-enable;
  667. bias-pull-up;
  668. };
  669. pins-tx {
  670. pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
  671. };
  672. };
  673. uart1_pins_default: uart1-pins-default {
  674. pins-rx {
  675. pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
  676. input-enable;
  677. bias-pull-up;
  678. };
  679. pins-tx {
  680. pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
  681. };
  682. pins-rts {
  683. pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
  684. output-enable;
  685. };
  686. pins-cts {
  687. pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
  688. input-enable;
  689. };
  690. };
  691. uart1_pins_sleep: uart1-pins-sleep {
  692. pins-rx {
  693. pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
  694. input-enable;
  695. bias-pull-up;
  696. };
  697. pins-tx {
  698. pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
  699. };
  700. pins-rts {
  701. pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
  702. output-enable;
  703. };
  704. pins-cts {
  705. pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
  706. input-enable;
  707. };
  708. };
  709. wifi_pins_pwrseq: wifi-pins-pwrseq {
  710. pins-wifi-enable {
  711. pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
  712. output-low;
  713. };
  714. };
  715. wifi_pins_wakeup: wifi-pins-wakeup {
  716. pins-wifi-wakeup {
  717. pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
  718. input-enable;
  719. };
  720. };
  721. };
  722. &pwm0 {
  723. status = "okay";
  724. pinctrl-names = "default";
  725. pinctrl-0 = <&pwm0_pin_default>;
  726. };
  727. &scp {
  728. status = "okay";
  729. pinctrl-names = "default";
  730. pinctrl-0 = <&scp_pins>;
  731. cros_ec {
  732. compatible = "google,cros-ec-rpmsg";
  733. mediatek,rpmsg-name = "cros-ec-rpmsg";
  734. };
  735. };
  736. &mfg_async {
  737. domain-supply = <&mt6358_vsram_gpu_reg>;
  738. };
  739. &mfg {
  740. domain-supply = <&mt6358_vgpu_reg>;
  741. };
  742. &soc_data {
  743. status = "okay";
  744. };
  745. &spi0 {
  746. pinctrl-names = "default";
  747. pinctrl-0 = <&spi0_pins>;
  748. mediatek,pad-select = <0>;
  749. status = "okay";
  750. cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
  751. cr50@0 {
  752. compatible = "google,cr50";
  753. reg = <0>;
  754. spi-max-frequency = <1000000>;
  755. pinctrl-names = "default";
  756. pinctrl-0 = <&h1_int_od_l>;
  757. interrupt-parent = <&pio>;
  758. interrupts = <153 IRQ_TYPE_EDGE_RISING>;
  759. };
  760. };
  761. &spi1 {
  762. pinctrl-names = "default";
  763. pinctrl-0 = <&spi1_pins>;
  764. mediatek,pad-select = <0>;
  765. status = "okay";
  766. w25q64dw: flash@0 {
  767. compatible = "winbond,w25q64dw", "jedec,spi-nor";
  768. reg = <0>;
  769. spi-max-frequency = <25000000>;
  770. };
  771. };
  772. &spi2 {
  773. pinctrl-names = "default";
  774. pinctrl-0 = <&spi2_pins>;
  775. mediatek,pad-select = <0>;
  776. status = "okay";
  777. cros_ec: cros-ec@0 {
  778. compatible = "google,cros-ec-spi";
  779. reg = <0>;
  780. spi-max-frequency = <3000000>;
  781. interrupt-parent = <&pio>;
  782. interrupts = <151 IRQ_TYPE_LEVEL_LOW>;
  783. pinctrl-names = "default";
  784. pinctrl-0 = <&ec_ap_int_odl>;
  785. i2c_tunnel: i2c-tunnel {
  786. compatible = "google,cros-ec-i2c-tunnel";
  787. google,remote-bus = <1>;
  788. #address-cells = <1>;
  789. #size-cells = <0>;
  790. };
  791. usbc_extcon: extcon0 {
  792. compatible = "google,extcon-usbc-cros-ec";
  793. google,usb-port-id = <0>;
  794. };
  795. cbas {
  796. compatible = "google,cros-cbas";
  797. };
  798. typec {
  799. compatible = "google,cros-ec-typec";
  800. #address-cells = <1>;
  801. #size-cells = <0>;
  802. usb_c0: connector@0 {
  803. compatible = "usb-c-connector";
  804. reg = <0>;
  805. power-role = "dual";
  806. data-role = "host";
  807. try-power-role = "sink";
  808. };
  809. };
  810. };
  811. };
  812. &spi3 {
  813. pinctrl-names = "default";
  814. pinctrl-0 = <&spi3_pins>;
  815. mediatek,pad-select = <0>;
  816. status = "disabled";
  817. };
  818. &spi4 {
  819. pinctrl-names = "default";
  820. pinctrl-0 = <&spi4_pins>;
  821. mediatek,pad-select = <0>;
  822. status = "disabled";
  823. };
  824. &spi5 {
  825. pinctrl-names = "default";
  826. pinctrl-0 = <&spi5_pins>;
  827. mediatek,pad-select = <0>;
  828. status = "disabled";
  829. };
  830. &ssusb {
  831. dr_mode = "host";
  832. wakeup-source;
  833. vusb33-supply = <&mt6358_vusb_reg>;
  834. status = "okay";
  835. };
  836. &thermal_zones {
  837. tboard1 {
  838. polling-delay = <1000>; /* milliseconds */
  839. polling-delay-passive = <0>; /* milliseconds */
  840. thermal-sensors = <&tboard_thermistor1>;
  841. };
  842. tboard2 {
  843. polling-delay = <1000>; /* milliseconds */
  844. polling-delay-passive = <0>; /* milliseconds */
  845. thermal-sensors = <&tboard_thermistor2>;
  846. };
  847. };
  848. &u3phy {
  849. status = "okay";
  850. };
  851. &uart0 {
  852. pinctrl-names = "default";
  853. pinctrl-0 = <&uart0_pins_default>;
  854. status = "okay";
  855. };
  856. &uart1 {
  857. pinctrl-names = "default", "sleep";
  858. pinctrl-0 = <&uart1_pins_default>;
  859. pinctrl-1 = <&uart1_pins_sleep>;
  860. status = "okay";
  861. interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
  862. <&pio 121 IRQ_TYPE_EDGE_FALLING>;
  863. bluetooth: bluetooth {
  864. pinctrl-names = "default";
  865. pinctrl-0 = <&bt_pins>;
  866. status = "okay";
  867. compatible = "qcom,qca6174-bt";
  868. enable-gpios = <&pio 120 0>;
  869. clocks = <&clk32k>;
  870. firmware-name = "nvm_00440302_i2s.bin";
  871. };
  872. };
  873. &usb_host {
  874. #address-cells = <1>;
  875. #size-cells = <0>;
  876. vusb33-supply = <&mt6358_vusb_reg>;
  877. status = "okay";
  878. hub@1 {
  879. compatible = "usb5e3,610";
  880. reg = <1>;
  881. };
  882. };
  883. #include <arm/cros-ec-keyboard.dtsi>
  884. #include <arm/cros-ec-sbs.dtsi>