mt7986a-rfb.dts 2.6 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright (C) 2021 MediaTek Inc.
  4. * Author: Sam.Shih <[email protected]>
  5. */
  6. /dts-v1/;
  7. #include "mt7986a.dtsi"
  8. / {
  9. model = "MediaTek MT7986a RFB";
  10. compatible = "mediatek,mt7986a-rfb";
  11. aliases {
  12. serial0 = &uart0;
  13. };
  14. chosen {
  15. stdout-path = "serial0:115200n8";
  16. };
  17. memory@40000000 {
  18. device_type = "memory";
  19. reg = <0 0x40000000 0 0x40000000>;
  20. };
  21. };
  22. &eth {
  23. status = "okay";
  24. gmac0: mac@0 {
  25. compatible = "mediatek,eth-mac";
  26. reg = <0>;
  27. phy-mode = "2500base-x";
  28. fixed-link {
  29. speed = <2500>;
  30. full-duplex;
  31. pause;
  32. };
  33. };
  34. mdio: mdio-bus {
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. };
  38. };
  39. &mdio {
  40. switch: switch@0 {
  41. compatible = "mediatek,mt7531";
  42. reg = <31>;
  43. reset-gpios = <&pio 5 0>;
  44. };
  45. };
  46. &switch {
  47. ports {
  48. #address-cells = <1>;
  49. #size-cells = <0>;
  50. port@0 {
  51. reg = <0>;
  52. label = "lan0";
  53. };
  54. port@1 {
  55. reg = <1>;
  56. label = "lan1";
  57. };
  58. port@2 {
  59. reg = <2>;
  60. label = "lan2";
  61. };
  62. port@3 {
  63. reg = <3>;
  64. label = "lan3";
  65. };
  66. port@4 {
  67. reg = <4>;
  68. label = "lan4";
  69. };
  70. port@6 {
  71. reg = <6>;
  72. label = "cpu";
  73. ethernet = <&gmac0>;
  74. phy-mode = "2500base-x";
  75. fixed-link {
  76. speed = <2500>;
  77. full-duplex;
  78. pause;
  79. };
  80. };
  81. };
  82. };
  83. &uart0 {
  84. status = "okay";
  85. };
  86. &uart1 {
  87. pinctrl-names = "default";
  88. pinctrl-0 = <&uart1_pins>;
  89. status = "okay";
  90. };
  91. &uart2 {
  92. pinctrl-names = "default";
  93. pinctrl-0 = <&uart2_pins>;
  94. status = "okay";
  95. };
  96. &wifi {
  97. status = "okay";
  98. pinctrl-names = "default", "dbdc";
  99. pinctrl-0 = <&wf_2g_5g_pins>;
  100. pinctrl-1 = <&wf_dbdc_pins>;
  101. };
  102. &pio {
  103. uart1_pins: uart1-pins {
  104. mux {
  105. function = "uart";
  106. groups = "uart1";
  107. };
  108. };
  109. uart2_pins: uart2-pins {
  110. mux {
  111. function = "uart";
  112. groups = "uart2";
  113. };
  114. };
  115. wf_2g_5g_pins: wf-2g-5g-pins {
  116. mux {
  117. function = "wifi";
  118. groups = "wf_2g", "wf_5g";
  119. };
  120. conf {
  121. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  122. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  123. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  124. "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  125. "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  126. "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  127. "WF1_TOP_CLK", "WF1_TOP_DATA";
  128. drive-strength = <4>;
  129. };
  130. };
  131. wf_dbdc_pins: wf-dbdc-pins {
  132. mux {
  133. function = "wifi";
  134. groups = "wf_dbdc";
  135. };
  136. conf {
  137. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  138. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  139. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  140. "WF0_TOP_CLK", "WF0_TOP_DATA";
  141. drive-strength = <4>;
  142. };
  143. };
  144. };