cn9130.dtsi 1.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (C) 2019 Marvell International Ltd.
  4. *
  5. * Device tree for the CN9130 SoC.
  6. */
  7. #include "armada-ap807-quad.dtsi"
  8. / {
  9. model = "Marvell Armada CN9130 SoC";
  10. compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
  11. "marvell,armada-ap807";
  12. aliases {
  13. gpio1 = &cp0_gpio1;
  14. gpio2 = &cp0_gpio2;
  15. spi1 = &cp0_spi0;
  16. spi2 = &cp0_spi1;
  17. };
  18. };
  19. /*
  20. * Instantiate the internal CP115
  21. */
  22. #define CP11X_NAME cp0
  23. #define CP11X_BASE f2000000
  24. #define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
  25. 0xe0000000 + ((iface - 1) * 0x1000000))
  26. #define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
  27. #define CP11X_PCIE0_BASE f2600000
  28. #define CP11X_PCIE1_BASE f2620000
  29. #define CP11X_PCIE2_BASE f2640000
  30. #include "armada-cp115.dtsi"
  31. #undef CP11X_NAME
  32. #undef CP11X_BASE
  33. #undef CP11X_PCIEx_MEM_BASE
  34. #undef CP11X_PCIEx_MEM_SIZE
  35. #undef CP11X_PCIE0_BASE
  36. #undef CP11X_PCIE1_BASE
  37. #undef CP11X_PCIE2_BASE
  38. &cp0_gpio1 {
  39. status = "okay";
  40. };
  41. &cp0_gpio2 {
  42. status = "okay";
  43. };