armada-ap806-dual.dtsi 1.3 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061
  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (C) 2016 Marvell Technology Group Ltd.
  4. *
  5. * Device Tree file for Marvell Armada AP806.
  6. */
  7. #include "armada-ap806.dtsi"
  8. / {
  9. model = "Marvell Armada AP806 Dual";
  10. compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
  11. cpus {
  12. #address-cells = <1>;
  13. #size-cells = <0>;
  14. cpu0: cpu@0 {
  15. device_type = "cpu";
  16. compatible = "arm,cortex-a72";
  17. reg = <0x000>;
  18. enable-method = "psci";
  19. #cooling-cells = <2>;
  20. clocks = <&cpu_clk 0>;
  21. i-cache-size = <0xc000>;
  22. i-cache-line-size = <64>;
  23. i-cache-sets = <256>;
  24. d-cache-size = <0x8000>;
  25. d-cache-line-size = <64>;
  26. d-cache-sets = <256>;
  27. next-level-cache = <&l2>;
  28. };
  29. cpu1: cpu@1 {
  30. device_type = "cpu";
  31. compatible = "arm,cortex-a72";
  32. reg = <0x001>;
  33. enable-method = "psci";
  34. #cooling-cells = <2>;
  35. clocks = <&cpu_clk 0>;
  36. i-cache-size = <0xc000>;
  37. i-cache-line-size = <64>;
  38. i-cache-sets = <256>;
  39. d-cache-size = <0x8000>;
  40. d-cache-line-size = <64>;
  41. d-cache-sets = <256>;
  42. next-level-cache = <&l2>;
  43. };
  44. l2: l2-cache {
  45. compatible = "cache";
  46. cache-size = <0x80000>;
  47. cache-line-size = <64>;
  48. cache-sets = <512>;
  49. };
  50. };
  51. thermal-zones {
  52. /delete-node/ ap-thermal-cpu2;
  53. /delete-node/ ap-thermal-cpu3;
  54. };
  55. };