armada-8040-clearfog-gt-8k.dts 12 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (C) 2018 SolidRun ltd.
  4. * Based on Marvell MACCHIATOBin board
  5. *
  6. * Device Tree file for SolidRun's ClearFog GT 8K
  7. */
  8. #include "armada-8040.dtsi"
  9. #include <dt-bindings/input/input.h>
  10. #include <dt-bindings/gpio/gpio.h>
  11. / {
  12. model = "SolidRun ClearFog GT 8K";
  13. compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
  14. "marvell,armada-ap806-quad", "marvell,armada-ap806";
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. memory@0 {
  19. device_type = "memory";
  20. reg = <0x0 0x0 0x0 0x80000000>;
  21. };
  22. aliases {
  23. ethernet0 = &cp1_eth1;
  24. ethernet1 = &cp0_eth0;
  25. ethernet2 = &cp1_eth2;
  26. };
  27. fan: pwm {
  28. compatible = "pwm-fan";
  29. /* 20% steps */
  30. cooling-levels = <0 51 102 153 204 255>;
  31. #cooling-cells = <2>;
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&cp0_fan_pwm_pins>;
  34. pwms = <&cp0_gpio2 16 40000>;
  35. };
  36. v_3_3: regulator-3-3v {
  37. compatible = "regulator-fixed";
  38. regulator-name = "v_3_3";
  39. regulator-min-microvolt = <3300000>;
  40. regulator-max-microvolt = <3300000>;
  41. regulator-always-on;
  42. status = "okay";
  43. };
  44. v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
  45. compatible = "regulator-fixed";
  46. gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>;
  47. pinctrl-names = "default";
  48. pinctrl-0 = <&cp0_xhci_vbus_pins>;
  49. regulator-name = "v_5v0_usb3_hst_vbus";
  50. regulator-min-microvolt = <5000000>;
  51. regulator-max-microvolt = <5000000>;
  52. status = "okay";
  53. };
  54. sfp_cp0_eth0: sfp-cp0-eth0 {
  55. compatible = "sff,sfp";
  56. i2c-bus = <&cp0_i2c1>;
  57. mod-def0-gpios = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
  58. tx-disable-gpios = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
  59. pinctrl-names = "default";
  60. pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>;
  61. maximum-power-milliwatt = <2000>;
  62. };
  63. leds {
  64. compatible = "gpio-leds";
  65. pinctrl-0 = <&cp0_led0_pins
  66. &cp0_led1_pins>;
  67. pinctrl-names = "default";
  68. /* No designated function for these LEDs at the moment */
  69. led0 {
  70. label = "clearfog-gt-8k:green:led0";
  71. gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>;
  72. default-state = "on";
  73. };
  74. led1 {
  75. label = "clearfog-gt-8k:green:led1";
  76. gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>;
  77. default-state = "on";
  78. };
  79. };
  80. keys {
  81. compatible = "gpio-keys";
  82. pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>;
  83. pinctrl-names = "default";
  84. button-0 {
  85. /* The rear button */
  86. label = "Rear Button";
  87. gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>;
  88. linux,can-disable;
  89. linux,code = <BTN_0>;
  90. };
  91. button-1 {
  92. /* The wps button */
  93. label = "WPS Button";
  94. gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>;
  95. linux,can-disable;
  96. linux,code = <KEY_WPS_BUTTON>;
  97. };
  98. };
  99. };
  100. &ap_thermal_ic {
  101. polling-delay = <1000>; /* milliseconds */
  102. trips {
  103. ap_active: trip-active {
  104. temperature = <40000>; /* millicelsius */
  105. hysteresis = <4000>; /* millicelsius */
  106. type = "active";
  107. };
  108. };
  109. cooling-maps {
  110. map0 {
  111. trip = <&ap_active>;
  112. cooling-device = <&fan THERMAL_NO_LIMIT 4>;
  113. };
  114. map1 {
  115. trip = <&ap_crit>;
  116. cooling-device = <&fan 4 5>;
  117. };
  118. };
  119. };
  120. &cp0_thermal_ic {
  121. polling-delay = <1000>; /* milliseconds */
  122. trips {
  123. cp0_active0: trip-active0 {
  124. temperature = <40000>; /* millicelsius */
  125. hysteresis = <2500>; /* millicelsius */
  126. type = "active";
  127. };
  128. cp0_active1: trip-active1 {
  129. temperature = <45000>; /* millicelsius */
  130. hysteresis = <2500>; /* millicelsius */
  131. type = "active";
  132. };
  133. cp0_active2: trip-active2 {
  134. temperature = <50000>; /* millicelsius */
  135. hysteresis = <2500>; /* millicelsius */
  136. type = "active";
  137. };
  138. cp0_active3: trip-active3 {
  139. temperature = <60000>; /* millicelsius */
  140. hysteresis = <2500>; /* millicelsius */
  141. type = "active";
  142. };
  143. };
  144. cooling-maps {
  145. map0 {
  146. trip = <&cp0_active0>;
  147. cooling-device = <&fan 0 1>;
  148. };
  149. map1 {
  150. trip = <&cp0_active1>;
  151. cooling-device = <&fan 1 2>;
  152. };
  153. map2 {
  154. trip = <&cp0_active2>;
  155. cooling-device = <&fan 2 3>;
  156. };
  157. map3 {
  158. trip = <&cp0_active3>;
  159. cooling-device = <&fan 3 4>;
  160. };
  161. map4 {
  162. trip = <&cp0_crit>;
  163. cooling-device = <&fan 4 5>;
  164. };
  165. };
  166. };
  167. &cp1_thermal_ic {
  168. polling-delay = <1000>; /* milliseconds */
  169. trips {
  170. cp1_active0: trip-active0 {
  171. temperature = <40000>; /* millicelsius */
  172. hysteresis = <2500>; /* millicelsius */
  173. type = "active";
  174. };
  175. cp1_active1: trip-active1 {
  176. temperature = <45000>; /* millicelsius */
  177. hysteresis = <2500>; /* millicelsius */
  178. type = "active";
  179. };
  180. cp1_active2: trip-active2 {
  181. temperature = <50000>; /* millicelsius */
  182. hysteresis = <2500>; /* millicelsius */
  183. type = "active";
  184. };
  185. cp1_active3: trip-active3 {
  186. temperature = <60000>; /* millicelsius */
  187. hysteresis = <2500>; /* millicelsius */
  188. type = "active";
  189. };
  190. };
  191. cooling-maps {
  192. map0 {
  193. trip = <&cp1_active0>;
  194. cooling-device = <&fan 0 1>;
  195. };
  196. map1 {
  197. trip = <&cp1_active1>;
  198. cooling-device = <&fan 1 2>;
  199. };
  200. map2 {
  201. trip = <&cp1_active2>;
  202. cooling-device = <&fan 2 3>;
  203. };
  204. map3 {
  205. trip = <&cp1_active3>;
  206. cooling-device = <&fan 3 4>;
  207. };
  208. map4 {
  209. trip = <&cp1_crit>;
  210. cooling-device = <&fan 4 5>;
  211. };
  212. };
  213. };
  214. &uart0 {
  215. status = "okay";
  216. pinctrl-0 = <&uart0_pins>;
  217. pinctrl-names = "default";
  218. };
  219. &ap_sdhci0 {
  220. bus-width = <8>;
  221. no-1-8-v;
  222. no-sd;
  223. no-sdio;
  224. non-removable;
  225. status = "okay";
  226. vqmmc-supply = <&v_3_3>;
  227. };
  228. &cp0_i2c0 {
  229. clock-frequency = <100000>;
  230. pinctrl-names = "default";
  231. pinctrl-0 = <&cp0_i2c0_pins>;
  232. status = "okay";
  233. };
  234. &cp0_i2c1 {
  235. clock-frequency = <100000>;
  236. pinctrl-names = "default";
  237. pinctrl-0 = <&cp0_i2c1_pins>;
  238. status = "okay";
  239. };
  240. &cp0_pinctrl {
  241. /*
  242. * MPP Bus:
  243. * [0-31] = 0xff: Keep default CP0_shared_pins:
  244. * [11] CLKOUT_MPP_11 (out)
  245. * [23] LINK_RD_IN_CP2CP (in)
  246. * [25] CLKOUT_MPP_25 (out)
  247. * [29] AVS_FB_IN_CP2CP (in)
  248. * [32, 33, 34] pci0/1/2 reset
  249. * [35-38] CP0 I2C1 and I2C0
  250. * [39] GPIO reset button
  251. * [40,41] LED0 and LED1
  252. * [43] 1512 phy reset
  253. * [47] USB VBUS EN (active low)
  254. * [48] FAN PWM
  255. * [49] SFP+ present signal
  256. * [50] TPM interrupt
  257. * [51] WLAN0 disable
  258. * [52] WLAN1 disable
  259. * [53] LTE disable
  260. * [54] NFC reset
  261. * [55] Micro SD card detect
  262. * [56-61] Micro SD
  263. */
  264. cp0_pci0_reset_pins: pci0-reset-pins {
  265. marvell,pins = "mpp32";
  266. marvell,function = "gpio";
  267. };
  268. cp0_pci1_reset_pins: pci1-reset-pins {
  269. marvell,pins = "mpp33";
  270. marvell,function = "gpio";
  271. };
  272. cp0_pci2_reset_pins: pci2-reset-pins {
  273. marvell,pins = "mpp34";
  274. marvell,function = "gpio";
  275. };
  276. cp0_i2c1_pins: i2c1-pins {
  277. marvell,pins = "mpp35", "mpp36";
  278. marvell,function = "i2c1";
  279. };
  280. cp0_i2c0_pins: i2c0-pins {
  281. marvell,pins = "mpp37", "mpp38";
  282. marvell,function = "i2c0";
  283. };
  284. cp0_gpio_reset_pins: gpio-reset-pins {
  285. marvell,pins = "mpp39";
  286. marvell,function = "gpio";
  287. };
  288. cp0_led0_pins: led0-pins {
  289. marvell,pins = "mpp40";
  290. marvell,function = "gpio";
  291. };
  292. cp0_led1_pins: led1-pins {
  293. marvell,pins = "mpp41";
  294. marvell,function = "gpio";
  295. };
  296. cp0_copper_eth_phy_reset: copper-eth-phy-reset {
  297. marvell,pins = "mpp43";
  298. marvell,function = "gpio";
  299. };
  300. cp0_xhci_vbus_pins: xhci0-vbus-pins {
  301. marvell,pins = "mpp47";
  302. marvell,function = "gpio";
  303. };
  304. cp0_fan_pwm_pins: fan-pwm-pins {
  305. marvell,pins = "mpp48";
  306. marvell,function = "gpio";
  307. };
  308. cp0_sfp_present_pins: sfp-present-pins {
  309. marvell,pins = "mpp49";
  310. marvell,function = "gpio";
  311. };
  312. cp0_tpm_irq_pins: tpm-irq-pins {
  313. marvell,pins = "mpp50";
  314. marvell,function = "gpio";
  315. };
  316. cp0_wlan_disable_pins: wlan-disable-pins {
  317. marvell,pins = "mpp51";
  318. marvell,function = "gpio";
  319. };
  320. cp0_sdhci_pins: sdhci-pins {
  321. marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
  322. "mpp60", "mpp61";
  323. marvell,function = "sdio";
  324. };
  325. };
  326. &cp0_pcie0 {
  327. pinctrl-names = "default";
  328. pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;
  329. reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
  330. phys = <&cp0_comphy0 0>;
  331. phy-names = "cp0-pcie0-x1-phy";
  332. status = "okay";
  333. };
  334. &cp0_gpio2 {
  335. sata_reset {
  336. gpio-hog;
  337. gpios = <1 GPIO_ACTIVE_HIGH>;
  338. output-high;
  339. };
  340. lte_reset {
  341. gpio-hog;
  342. gpios = <2 GPIO_ACTIVE_LOW>;
  343. output-low;
  344. };
  345. wlan_disable {
  346. gpio-hog;
  347. gpios = <19 GPIO_ACTIVE_LOW>;
  348. output-low;
  349. };
  350. lte_disable {
  351. gpio-hog;
  352. gpios = <21 GPIO_ACTIVE_LOW>;
  353. output-low;
  354. };
  355. };
  356. &cp0_ethernet {
  357. status = "okay";
  358. };
  359. /* SFP */
  360. &cp0_eth0 {
  361. status = "okay";
  362. phy-mode = "10gbase-r";
  363. managed = "in-band-status";
  364. phys = <&cp0_comphy2 0>;
  365. sfp = <&sfp_cp0_eth0>;
  366. };
  367. &cp0_sdhci0 {
  368. broken-cd;
  369. bus-width = <4>;
  370. pinctrl-names = "default";
  371. pinctrl-0 = <&cp0_sdhci_pins>;
  372. status = "okay";
  373. vqmmc-supply = <&v_3_3>;
  374. };
  375. &cp0_usb3_1 {
  376. status = "okay";
  377. };
  378. &cp1_pinctrl {
  379. /*
  380. * MPP Bus:
  381. * [0-5] TDM
  382. * [6] VHV Enable
  383. * [7] CP1 SPI0 CSn1 (FXS)
  384. * [8] CP1 SPI0 CSn0 (TPM)
  385. * [9.11]CP1 SPI0 MOSI/MISO/CLK
  386. * [13] CP1 SPI1 MISO (TDM and SPI ROM shared)
  387. * [14] CP1 SPI1 CS0n (64Mb SPI ROM)
  388. * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared)
  389. * [16] CP1 SPI1 CLK (TDM and SPI ROM shared)
  390. * [24] Topaz switch reset
  391. * [26] Buzzer
  392. * [27] CP1 SMI MDIO
  393. * [28] CP1 SMI MDC
  394. * [29] CP0 10G SFP TX Disable
  395. * [30] WPS button
  396. * [31] Front panel button
  397. */
  398. cp1_spi1_pins: spi1-pins {
  399. marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
  400. marvell,function = "spi1";
  401. };
  402. cp1_switch_reset_pins: switch-reset-pins {
  403. marvell,pins = "mpp24";
  404. marvell,function = "gpio";
  405. };
  406. cp1_ge_mdio_pins: ge-mdio-pins {
  407. marvell,pins = "mpp27", "mpp28";
  408. marvell,function = "ge";
  409. };
  410. cp1_sfp_tx_disable_pins: sfp-tx-disable-pins {
  411. marvell,pins = "mpp29";
  412. marvell,function = "gpio";
  413. };
  414. cp1_wps_button_pins: wps-button-pins {
  415. marvell,pins = "mpp30";
  416. marvell,function = "gpio";
  417. };
  418. };
  419. &cp1_sata0 {
  420. pinctrl-0 = <&cp0_pci1_reset_pins>;
  421. status = "okay";
  422. sata-port@1 {
  423. phys = <&cp1_comphy0 1>;
  424. phy-names = "cp1-sata0-1-phy";
  425. };
  426. };
  427. &cp1_mdio {
  428. pinctrl-names = "default";
  429. pinctrl-0 = <&cp1_ge_mdio_pins>;
  430. status = "okay";
  431. ge_phy: ethernet-phy@0 {
  432. /* LED0 - GB link
  433. * LED1 - on: link, blink: activity
  434. */
  435. marvell,reg-init = <3 16 0 0x1017>;
  436. reg = <0>;
  437. pinctrl-names = "default";
  438. pinctrl-0 = <&cp0_copper_eth_phy_reset>;
  439. reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
  440. reset-assert-us = <10000>;
  441. reset-deassert-us = <10000>;
  442. };
  443. switch0: switch0@4 {
  444. compatible = "marvell,mv88e6085";
  445. reg = <4>;
  446. pinctrl-names = "default";
  447. pinctrl-0 = <&cp1_switch_reset_pins>;
  448. reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
  449. ports {
  450. #address-cells = <1>;
  451. #size-cells = <0>;
  452. port@1 {
  453. reg = <1>;
  454. label = "lan2";
  455. phy-handle = <&switch0phy0>;
  456. };
  457. port@2 {
  458. reg = <2>;
  459. label = "lan1";
  460. phy-handle = <&switch0phy1>;
  461. };
  462. port@3 {
  463. reg = <3>;
  464. label = "lan4";
  465. phy-handle = <&switch0phy2>;
  466. };
  467. port@4 {
  468. reg = <4>;
  469. label = "lan3";
  470. phy-handle = <&switch0phy3>;
  471. };
  472. port@5 {
  473. reg = <5>;
  474. label = "cpu";
  475. ethernet = <&cp1_eth2>;
  476. phy-mode = "2500base-x";
  477. managed = "in-band-status";
  478. };
  479. };
  480. mdio {
  481. #address-cells = <1>;
  482. #size-cells = <0>;
  483. switch0phy0: switch0phy0@11 {
  484. reg = <0x11>;
  485. };
  486. switch0phy1: switch0phy1@12 {
  487. reg = <0x12>;
  488. };
  489. switch0phy2: switch0phy2@13 {
  490. reg = <0x13>;
  491. };
  492. switch0phy3: switch0phy3@14 {
  493. reg = <0x14>;
  494. };
  495. };
  496. };
  497. };
  498. &cp1_ethernet {
  499. status = "okay";
  500. };
  501. /* 1G copper */
  502. &cp1_eth1 {
  503. status = "okay";
  504. phy-mode = "sgmii";
  505. phy = <&ge_phy>;
  506. phys = <&cp1_comphy3 1>;
  507. };
  508. /* Switch uplink */
  509. &cp1_eth2 {
  510. status = "okay";
  511. phy-mode = "2500base-x";
  512. phys = <&cp1_comphy5 2>;
  513. managed = "in-band-status";
  514. };
  515. &cp1_spi1 {
  516. pinctrl-names = "default";
  517. pinctrl-0 = <&cp1_spi1_pins>;
  518. status = "okay";
  519. flash@0 {
  520. compatible = "st,w25q32";
  521. spi-max-frequency = <50000000>;
  522. reg = <0>;
  523. };
  524. };
  525. &cp1_comphy2 {
  526. cp1_usbh0_con: connector {
  527. compatible = "usb-a-connector";
  528. phy-supply = <&v_5v0_usb3_hst_vbus>;
  529. };
  530. };
  531. &cp1_usb3_0 {
  532. phys = <&cp1_comphy2 0>;
  533. phy-names = "cp1-usb3h0-comphy";
  534. status = "okay";
  535. };