armada-7040-mochabin.dts 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /*
  3. * Device Tree file for Globalscale MOCHAbin
  4. * Copyright (C) 2019 Globalscale technologies, Inc.
  5. * Copyright (C) 2021 Sartura Ltd.
  6. *
  7. */
  8. /dts-v1/;
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include "armada-7040.dtsi"
  11. / {
  12. model = "Globalscale MOCHAbin";
  13. compatible = "globalscale,mochabin", "marvell,armada7040",
  14. "marvell,armada-ap806-quad", "marvell,armada-ap806";
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. aliases {
  19. ethernet0 = &cp0_eth0;
  20. ethernet1 = &cp0_eth1;
  21. ethernet2 = &cp0_eth2;
  22. ethernet3 = &swport1;
  23. ethernet4 = &swport2;
  24. ethernet5 = &swport3;
  25. ethernet6 = &swport4;
  26. };
  27. /* SFP+ 10G */
  28. sfp_eth0: sfp-eth0 {
  29. compatible = "sff,sfp";
  30. i2c-bus = <&cp0_i2c1>;
  31. los-gpios = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
  32. mod-def0-gpios = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
  33. tx-disable-gpios = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
  34. tx-fault-gpios = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
  35. };
  36. /* SFP 1G */
  37. sfp_eth2: sfp-eth2 {
  38. compatible = "sff,sfp";
  39. i2c-bus = <&cp0_i2c0>;
  40. los-gpios = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
  41. mod-def0-gpios = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
  42. tx-disable-gpios = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
  43. tx-fault-gpios = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
  44. };
  45. };
  46. /* microUSB UART console */
  47. &uart0 {
  48. status = "okay";
  49. pinctrl-0 = <&uart0_pins>;
  50. pinctrl-names = "default";
  51. };
  52. /* eMMC */
  53. &ap_sdhci0 {
  54. status = "okay";
  55. bus-width = <4>;
  56. non-removable;
  57. /delete-property/ marvell,xenon-phy-slow-mode;
  58. no-1-8-v;
  59. };
  60. &cp0_pinctrl {
  61. cp0_uart0_pins: cp0-uart0-pins {
  62. marvell,pins = "mpp6", "mpp7";
  63. marvell,function = "uart0";
  64. };
  65. cp0_spi0_pins: cp0-spi0-pins {
  66. marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
  67. marvell,function = "spi0";
  68. };
  69. cp0_spi1_pins: cp0-spi1-pins {
  70. marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
  71. marvell,function = "spi1";
  72. };
  73. cp0_i2c0_pins: cp0-i2c0-pins {
  74. marvell,pins = "mpp37", "mpp38";
  75. marvell,function = "i2c0";
  76. };
  77. cp0_i2c1_pins: cp0-i2c1-pins {
  78. marvell,pins = "mpp2", "mpp3";
  79. marvell,function = "i2c1";
  80. };
  81. pca9554_int_pins: pca9554-int-pins {
  82. marvell,pins = "mpp27";
  83. marvell,function = "gpio";
  84. };
  85. cp0_rgmii1_pins: cp0-rgmii1-pins {
  86. marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
  87. "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
  88. marvell,function = "ge1";
  89. };
  90. is31_sdb_pins: is31-sdb-pins {
  91. marvell,pins = "mpp30";
  92. marvell,function = "gpio";
  93. };
  94. cp0_pcie_reset_pins: cp0-pcie-reset-pins {
  95. marvell,pins = "mpp9";
  96. marvell,function = "gpio";
  97. };
  98. cp0_pcie_clkreq_pins: cp0-pcie-clkreq-pins {
  99. marvell,pins = "mpp5";
  100. marvell,function = "pcie1";
  101. };
  102. cp0_switch_pins: cp0-switch-pins {
  103. marvell,pins = "mpp0", "mpp1";
  104. marvell,function = "gpio";
  105. };
  106. cp0_phy_pins: cp0-phy-pins {
  107. marvell,pins = "mpp12";
  108. marvell,function = "gpio";
  109. };
  110. };
  111. /* mikroBUS UART */
  112. &cp0_uart0 {
  113. status = "okay";
  114. pinctrl-names = "default";
  115. pinctrl-0 = <&cp0_uart0_pins>;
  116. };
  117. /* mikroBUS SPI */
  118. &cp0_spi0 {
  119. status = "okay";
  120. pinctrl-names = "default";
  121. pinctrl-0 = <&cp0_spi0_pins>;
  122. };
  123. /* SPI-NOR */
  124. &cp0_spi1{
  125. status = "okay";
  126. pinctrl-names = "default";
  127. pinctrl-0 = <&cp0_spi1_pins>;
  128. flash@0 {
  129. #address-cells = <1>;
  130. #size-cells = <1>;
  131. compatible = "jedec,spi-nor";
  132. reg = <0>;
  133. spi-max-frequency = <20000000>;
  134. partitions {
  135. compatible = "fixed-partitions";
  136. #address-cells = <1>;
  137. #size-cells = <1>;
  138. partition@0 {
  139. label = "firmware";
  140. reg = <0x0 0x3e0000>;
  141. read-only;
  142. };
  143. partition@3e0000 {
  144. label = "hw-info";
  145. reg = <0x3e0000 0x10000>;
  146. read-only;
  147. };
  148. partition@3f0000 {
  149. label = "u-boot-env";
  150. reg = <0x3f0000 0x10000>;
  151. };
  152. };
  153. };
  154. };
  155. /* mikroBUS, 1G SFP and GPIO expander */
  156. &cp0_i2c0 {
  157. status = "okay";
  158. pinctrl-names = "default";
  159. pinctrl-0 = <&cp0_i2c0_pins>;
  160. clock-frequency = <100000>;
  161. sfp_gpio: pca9554@39 {
  162. compatible = "nxp,pca9554";
  163. pinctrl-names = "default";
  164. pinctrl-0 = <&pca9554_int_pins>;
  165. reg = <0x39>;
  166. interrupt-parent = <&cp0_gpio1>;
  167. interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
  168. interrupt-controller;
  169. #interrupt-cells = <2>;
  170. gpio-controller;
  171. #gpio-cells = <2>;
  172. /*
  173. * IO0_0: SFP+_TX_FAULT
  174. * IO0_1: SFP+_TX_DISABLE
  175. * IO0_2: SFP+_PRSNT
  176. * IO0_3: SFP+_LOSS
  177. * IO0_4: SFP_TX_FAULT
  178. * IO0_5: SFP_TX_DISABLE
  179. * IO0_6: SFP_PRSNT
  180. * IO0_7: SFP_LOSS
  181. */
  182. };
  183. };
  184. /* IS31FL3199, mini-PCIe and 10G SFP+ */
  185. &cp0_i2c1 {
  186. status = "okay";
  187. pinctrl-names = "default";
  188. pinctrl-0 = <&cp0_i2c1_pins>;
  189. clock-frequency = <100000>;
  190. leds@64 {
  191. compatible = "issi,is31fl3199";
  192. #address-cells = <1>;
  193. #size-cells = <0>;
  194. pinctrl-names = "default";
  195. pinctrl-0 = <&is31_sdb_pins>;
  196. shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
  197. reg = <0x64>;
  198. led1_red: led@1 {
  199. label = "red:led1";
  200. reg = <1>;
  201. led-max-microamp = <20000>;
  202. };
  203. led1_green: led@2 {
  204. label = "green:led1";
  205. reg = <2>;
  206. };
  207. led1_blue: led@3 {
  208. label = "blue:led1";
  209. reg = <3>;
  210. };
  211. led2_red: led@4 {
  212. label = "red:led2";
  213. reg = <4>;
  214. };
  215. led2_green: led@5 {
  216. label = "green:led2";
  217. reg = <5>;
  218. };
  219. led2_blue: led@6 {
  220. label = "blue:led2";
  221. reg = <6>;
  222. };
  223. led3_red: led@7 {
  224. label = "red:led3";
  225. reg = <7>;
  226. };
  227. led3_green: led@8 {
  228. label = "green:led3";
  229. reg = <8>;
  230. };
  231. led3_blue: led@9 {
  232. label = "blue:led3";
  233. reg = <9>;
  234. };
  235. };
  236. };
  237. &cp0_mdio {
  238. status = "okay";
  239. /* 88E1512 PHY */
  240. eth2phy: ethernet-phy@1 {
  241. reg = <1>;
  242. sfp = <&sfp_eth2>;
  243. pinctrl-names = "default";
  244. pinctrl-0 = <&cp0_phy_pins>;
  245. reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
  246. };
  247. /* 88E6141 Topaz switch */
  248. switch: switch@3 {
  249. compatible = "marvell,mv88e6085";
  250. #address-cells = <1>;
  251. #size-cells = <0>;
  252. reg = <3>;
  253. pinctrl-names = "default";
  254. pinctrl-0 = <&cp0_switch_pins>;
  255. reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
  256. interrupt-parent = <&cp0_gpio1>;
  257. interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
  258. ports {
  259. #address-cells = <1>;
  260. #size-cells = <0>;
  261. swport1: port@1 {
  262. reg = <1>;
  263. label = "lan0";
  264. phy-handle = <&swphy1>;
  265. };
  266. swport2: port@2 {
  267. reg = <2>;
  268. label = "lan1";
  269. phy-handle = <&swphy2>;
  270. };
  271. swport3: port@3 {
  272. reg = <3>;
  273. label = "lan2";
  274. phy-handle = <&swphy3>;
  275. };
  276. swport4: port@4 {
  277. reg = <4>;
  278. label = "lan3";
  279. phy-handle = <&swphy4>;
  280. };
  281. port@5 {
  282. reg = <5>;
  283. label = "cpu";
  284. ethernet = <&cp0_eth1>;
  285. phy-mode = "2500base-x";
  286. managed = "in-band-status";
  287. };
  288. };
  289. mdio {
  290. #address-cells = <1>;
  291. #size-cells = <0>;
  292. swphy1: swphy1@17 {
  293. reg = <17>;
  294. };
  295. swphy2: swphy2@18 {
  296. reg = <18>;
  297. };
  298. swphy3: swphy3@19 {
  299. reg = <19>;
  300. };
  301. swphy4: swphy4@20 {
  302. reg = <20>;
  303. };
  304. };
  305. };
  306. };
  307. &cp0_ethernet {
  308. status = "okay";
  309. };
  310. /* 10G SFP+ */
  311. &cp0_eth0 {
  312. status = "okay";
  313. phy-mode = "10gbase-r";
  314. phys = <&cp0_comphy4 0>;
  315. managed = "in-band-status";
  316. sfp = <&sfp_eth0>;
  317. };
  318. /* Topaz switch uplink */
  319. &cp0_eth1 {
  320. status = "okay";
  321. phy-mode = "2500base-x";
  322. phys = <&cp0_comphy0 1>;
  323. fixed-link {
  324. speed = <2500>;
  325. full-duplex;
  326. };
  327. };
  328. /* 1G SFP or 1G RJ45 */
  329. &cp0_eth2 {
  330. status = "okay";
  331. pinctrl-names = "default";
  332. pinctrl-0 = <&cp0_rgmii1_pins>;
  333. phy = <&eth2phy>;
  334. phy-mode = "rgmii-id";
  335. };
  336. &cp0_utmi {
  337. status = "okay";
  338. };
  339. /* SMSC USB5434B hub */
  340. &cp0_usb3_0 {
  341. status = "okay";
  342. phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
  343. phy-names = "cp0-usb3h0-comphy", "utmi";
  344. };
  345. /* miniPCI-E USB */
  346. &cp0_usb3_1 {
  347. status = "okay";
  348. };
  349. &cp0_sata0 {
  350. status = "okay";
  351. /* 7 + 12 SATA connector (J24) */
  352. sata-port@0 {
  353. phys = <&cp0_comphy2 0>;
  354. phy-names = "cp0-sata0-0-phy";
  355. };
  356. /* M.2-2250 B-key (J39) */
  357. sata-port@1 {
  358. phys = <&cp0_comphy3 1>;
  359. phy-names = "cp0-sata0-1-phy";
  360. };
  361. };
  362. /* miniPCI-E (J5) */
  363. &cp0_pcie2 {
  364. status = "okay";
  365. pinctrl-names = "default", "clkreq";
  366. pinctrl-0 = <&cp0_pcie_reset_pins>;
  367. pinctrl-1 = <&cp0_pcie_clkreq_pins>;
  368. phys = <&cp0_comphy5 2>;
  369. phy-names = "cp0-pcie2-x1-phy";
  370. reset-gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
  371. };