imx93-11x11-evk.dts 2.5 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright 2022 NXP
  4. */
  5. /dts-v1/;
  6. #include "imx93.dtsi"
  7. / {
  8. model = "NXP i.MX93 11X11 EVK board";
  9. compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
  10. chosen {
  11. stdout-path = &lpuart1;
  12. };
  13. reg_usdhc2_vmmc: regulator-usdhc2 {
  14. compatible = "regulator-fixed";
  15. pinctrl-names = "default";
  16. pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  17. regulator-name = "VSD_3V3";
  18. regulator-min-microvolt = <3300000>;
  19. regulator-max-microvolt = <3300000>;
  20. gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
  21. enable-active-high;
  22. };
  23. };
  24. &mu1 {
  25. status = "okay";
  26. };
  27. &mu2 {
  28. status = "okay";
  29. };
  30. &lpuart1 { /* console */
  31. pinctrl-names = "default";
  32. pinctrl-0 = <&pinctrl_uart1>;
  33. status = "okay";
  34. };
  35. &usdhc1 {
  36. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  37. pinctrl-0 = <&pinctrl_usdhc1>;
  38. pinctrl-1 = <&pinctrl_usdhc1>;
  39. pinctrl-2 = <&pinctrl_usdhc1>;
  40. bus-width = <8>;
  41. non-removable;
  42. status = "okay";
  43. };
  44. &usdhc2 {
  45. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  46. pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  47. pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  48. pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  49. cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
  50. vmmc-supply = <&reg_usdhc2_vmmc>;
  51. bus-width = <4>;
  52. status = "okay";
  53. no-sdio;
  54. no-mmc;
  55. };
  56. &iomuxc {
  57. pinctrl_uart1: uart1grp {
  58. fsl,pins = <
  59. MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
  60. MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
  61. >;
  62. };
  63. pinctrl_usdhc1: usdhc1grp {
  64. fsl,pins = <
  65. MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
  66. MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
  67. MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
  68. MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
  69. MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
  70. MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
  71. MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
  72. MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
  73. MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
  74. MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
  75. MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
  76. >;
  77. };
  78. pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
  79. fsl,pins = <
  80. MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
  81. >;
  82. };
  83. pinctrl_usdhc2_gpio: usdhc2gpiogrp {
  84. fsl,pins = <
  85. MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
  86. >;
  87. };
  88. pinctrl_usdhc2: usdhc2grp {
  89. fsl,pins = <
  90. MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
  91. MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
  92. MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
  93. MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
  94. MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
  95. MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
  96. MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
  97. >;
  98. };
  99. };