imx8mq-pico-pi.dts 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 Wandboard, Org.
  4. * Copyright 2017 NXP
  5. *
  6. * Author: Richard Hu <[email protected]>
  7. */
  8. /dts-v1/;
  9. #include "imx8mq.dtsi"
  10. #include <dt-bindings/interrupt-controller/irq.h>
  11. / {
  12. model = "TechNexion PICO-PI-8M";
  13. compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
  14. chosen {
  15. stdout-path = &uart1;
  16. };
  17. pmic_osc: clock-pmic {
  18. compatible = "fixed-clock";
  19. #clock-cells = <0>;
  20. clock-frequency = <32768>;
  21. clock-output-names = "pmic_osc";
  22. };
  23. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  24. pinctrl-names = "default";
  25. pinctrl-0 = <&pinctrl_otg_vbus>;
  26. compatible = "regulator-fixed";
  27. regulator-name = "usb_otg_vbus";
  28. regulator-min-microvolt = <5000000>;
  29. regulator-max-microvolt = <5000000>;
  30. gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
  31. };
  32. };
  33. &fec1 {
  34. pinctrl-names = "default";
  35. pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
  36. phy-mode = "rgmii-id";
  37. phy-handle = <&ethphy0>;
  38. fsl,magic-packet;
  39. status = "okay";
  40. mdio {
  41. #address-cells = <1>;
  42. #size-cells = <0>;
  43. ethphy0: ethernet-phy@1 {
  44. compatible = "ethernet-phy-ieee802.3-c22";
  45. reg = <1>;
  46. };
  47. };
  48. };
  49. &i2c1 {
  50. clock-frequency = <100000>;
  51. pinctrl-names = "default";
  52. pinctrl-0 = <&pinctrl_i2c1>;
  53. status = "okay";
  54. pmic: pmic@4b {
  55. reg = <0x4b>;
  56. compatible = "rohm,bd71837";
  57. pinctrl-names = "default";
  58. pinctrl-0 = <&pinctrl_pmic>;
  59. clocks = <&pmic_osc>;
  60. clock-names = "osc";
  61. clock-output-names = "pmic_clk";
  62. interrupt-parent = <&gpio1>;
  63. interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
  64. interrupt-names = "irq";
  65. regulators {
  66. buck1: BUCK1 {
  67. regulator-name = "buck1";
  68. regulator-min-microvolt = <700000>;
  69. regulator-max-microvolt = <1300000>;
  70. regulator-boot-on;
  71. regulator-ramp-delay = <1250>;
  72. rohm,dvs-run-voltage = <900000>;
  73. rohm,dvs-idle-voltage = <850000>;
  74. rohm,dvs-suspend-voltage = <800000>;
  75. };
  76. buck2: BUCK2 {
  77. regulator-name = "buck2";
  78. regulator-min-microvolt = <700000>;
  79. regulator-max-microvolt = <1300000>;
  80. regulator-boot-on;
  81. regulator-ramp-delay = <1250>;
  82. rohm,dvs-run-voltage = <1000000>;
  83. rohm,dvs-idle-voltage = <900000>;
  84. };
  85. buck3: BUCK3 {
  86. regulator-name = "buck3";
  87. regulator-min-microvolt = <700000>;
  88. regulator-max-microvolt = <1300000>;
  89. regulator-boot-on;
  90. rohm,dvs-run-voltage = <1000000>;
  91. };
  92. buck4: BUCK4 {
  93. regulator-name = "buck4";
  94. regulator-min-microvolt = <700000>;
  95. regulator-max-microvolt = <1300000>;
  96. regulator-boot-on;
  97. rohm,dvs-run-voltage = <1000000>;
  98. };
  99. buck5: BUCK5 {
  100. regulator-name = "buck5";
  101. regulator-min-microvolt = <700000>;
  102. regulator-max-microvolt = <1350000>;
  103. regulator-boot-on;
  104. };
  105. buck6: BUCK6 {
  106. regulator-name = "buck6";
  107. regulator-min-microvolt = <3000000>;
  108. regulator-max-microvolt = <3300000>;
  109. regulator-boot-on;
  110. };
  111. buck7: BUCK7 {
  112. regulator-name = "buck7";
  113. regulator-min-microvolt = <1605000>;
  114. regulator-max-microvolt = <1995000>;
  115. regulator-boot-on;
  116. };
  117. buck8: BUCK8 {
  118. regulator-name = "buck8";
  119. regulator-min-microvolt = <800000>;
  120. regulator-max-microvolt = <1400000>;
  121. regulator-boot-on;
  122. };
  123. ldo1: LDO1 {
  124. regulator-name = "ldo1";
  125. regulator-min-microvolt = <3000000>;
  126. regulator-max-microvolt = <3300000>;
  127. regulator-boot-on;
  128. regulator-always-on;
  129. };
  130. ldo2: LDO2 {
  131. regulator-name = "ldo2";
  132. regulator-min-microvolt = <900000>;
  133. regulator-max-microvolt = <900000>;
  134. regulator-boot-on;
  135. regulator-always-on;
  136. };
  137. ldo3: LDO3 {
  138. regulator-name = "ldo3";
  139. regulator-min-microvolt = <1800000>;
  140. regulator-max-microvolt = <3300000>;
  141. regulator-boot-on;
  142. };
  143. ldo4: LDO4 {
  144. regulator-name = "ldo4";
  145. regulator-min-microvolt = <900000>;
  146. regulator-max-microvolt = <1800000>;
  147. regulator-boot-on;
  148. };
  149. ldo5: LDO5 {
  150. regulator-name = "ldo5";
  151. regulator-min-microvolt = <1800000>;
  152. regulator-max-microvolt = <3300000>;
  153. regulator-boot-on;
  154. };
  155. ldo6: LDO6 {
  156. regulator-name = "ldo6";
  157. regulator-min-microvolt = <900000>;
  158. regulator-max-microvolt = <1800000>;
  159. regulator-boot-on;
  160. };
  161. ldo7: LDO7 {
  162. regulator-name = "ldo7";
  163. regulator-min-microvolt = <1800000>;
  164. regulator-max-microvolt = <3300000>;
  165. regulator-boot-on;
  166. };
  167. };
  168. };
  169. };
  170. &i2c2 {
  171. clock-frequency = <100000>;
  172. pinctrl-names = "default";
  173. pinctrl-0 = <&pinctrl_i2c2>;
  174. status = "okay";
  175. };
  176. &uart1 { /* console */
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&pinctrl_uart1>;
  179. status = "okay";
  180. };
  181. &usdhc1 {
  182. assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
  183. assigned-clock-rates = <400000000>;
  184. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  185. pinctrl-0 = <&pinctrl_usdhc1>;
  186. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  187. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  188. bus-width = <8>;
  189. non-removable;
  190. status = "okay";
  191. };
  192. &usdhc2 {
  193. assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
  194. assigned-clock-rates = <200000000>;
  195. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  196. pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  197. pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  198. pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  199. bus-width = <4>;
  200. cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
  201. status = "okay";
  202. };
  203. &usb3_phy0 {
  204. status = "okay";
  205. };
  206. &usb3_phy1 {
  207. status = "okay";
  208. };
  209. &usb_dwc3_1 {
  210. dr_mode = "host";
  211. status = "okay";
  212. };
  213. &wdog1 {
  214. pinctrl-names = "default";
  215. pinctrl-0 = <&pinctrl_wdog>;
  216. fsl,ext-reset-output;
  217. status = "okay";
  218. };
  219. &iomuxc {
  220. pinctrl_enet_3v3: enet3v3grp {
  221. fsl,pins = <
  222. MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
  223. >;
  224. };
  225. pinctrl_fec1: fec1grp {
  226. fsl,pins = <
  227. MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
  228. MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
  229. MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
  230. MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
  231. MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
  232. MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
  233. MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
  234. MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
  235. MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
  236. MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
  237. MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
  238. MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
  239. MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
  240. MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
  241. MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
  242. >;
  243. };
  244. pinctrl_i2c1: i2c1grp {
  245. fsl,pins = <
  246. MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
  247. MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
  248. >;
  249. };
  250. pinctrl_i2c2: i2c2grp {
  251. fsl,pins = <
  252. MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
  253. MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
  254. >;
  255. };
  256. pinctrl_otg_vbus: otgvbusgrp {
  257. fsl,pins = <
  258. MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */
  259. >;
  260. };
  261. pinctrl_pmic: pmicirqgrp {
  262. fsl,pins = <
  263. MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
  264. >;
  265. };
  266. pinctrl_uart1: uart1grp {
  267. fsl,pins = <
  268. MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
  269. MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
  270. >;
  271. };
  272. pinctrl_uart2: uart2grp {
  273. fsl,pins = <
  274. MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
  275. MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
  276. MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
  277. MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
  278. >;
  279. };
  280. pinctrl_usdhc1: usdhc1grp {
  281. fsl,pins = <
  282. MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
  283. MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
  284. MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
  285. MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
  286. MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
  287. MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
  288. MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
  289. MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
  290. MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
  291. MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
  292. MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
  293. >;
  294. };
  295. pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
  296. fsl,pins = <
  297. MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
  298. MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
  299. MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
  300. MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
  301. MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
  302. MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
  303. MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
  304. MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
  305. MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
  306. MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
  307. MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
  308. >;
  309. };
  310. pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
  311. fsl,pins = <
  312. MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
  313. MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
  314. MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
  315. MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
  316. MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
  317. MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
  318. MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
  319. MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
  320. MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
  321. MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
  322. MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
  323. >;
  324. };
  325. pinctrl_usdhc2_gpio: usdhc2gpiogrp {
  326. fsl,pins = <
  327. MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
  328. >;
  329. };
  330. pinctrl_usdhc2: usdhc2grp {
  331. fsl,pins = <
  332. MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
  333. MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
  334. MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
  335. MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
  336. MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
  337. MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
  338. MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
  339. >;
  340. };
  341. pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
  342. fsl,pins = <
  343. MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
  344. MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
  345. MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
  346. MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
  347. MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
  348. MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
  349. MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
  350. >;
  351. };
  352. pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
  353. fsl,pins = <
  354. MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
  355. MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
  356. MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
  357. MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
  358. MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
  359. MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
  360. MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
  361. >;
  362. };
  363. pinctrl_wdog: wdoggrp {
  364. fsl,pins = <
  365. MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
  366. >;
  367. };
  368. };