imx8mq-phanbell.dts 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481
  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright 2017-2019 NXP
  4. */
  5. /dts-v1/;
  6. #include "imx8mq.dtsi"
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. model = "Google i.MX8MQ Phanbell";
  10. compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
  11. chosen {
  12. stdout-path = &uart1;
  13. };
  14. memory@40000000 {
  15. device_type = "memory";
  16. reg = <0x00000000 0x40000000 0 0x40000000>;
  17. };
  18. pmic_osc: clock-pmic {
  19. compatible = "fixed-clock";
  20. #clock-cells = <0>;
  21. clock-frequency = <32768>;
  22. clock-output-names = "pmic_osc";
  23. };
  24. reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
  25. compatible = "regulator-fixed";
  26. regulator-name = "VSD_3V3";
  27. regulator-min-microvolt = <3300000>;
  28. regulator-max-microvolt = <3300000>;
  29. gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  30. enable-active-high;
  31. };
  32. fan: gpio-fan {
  33. compatible = "gpio-fan";
  34. gpio-fan,speed-map = <0 0 8600 1>;
  35. gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
  36. #cooling-cells = <2>;
  37. pinctrl-names = "default";
  38. pinctrl-0 = <&pinctrl_gpio_fan>;
  39. status = "okay";
  40. };
  41. };
  42. &A53_0 {
  43. cpu-supply = <&buck2>;
  44. };
  45. &A53_1 {
  46. cpu-supply = <&buck2>;
  47. };
  48. &A53_2 {
  49. cpu-supply = <&buck2>;
  50. };
  51. &A53_3 {
  52. cpu-supply = <&buck2>;
  53. };
  54. &cpu_thermal {
  55. trips {
  56. cpu_alert0: trip0 {
  57. temperature = <75000>;
  58. hysteresis = <2000>;
  59. type = "passive";
  60. };
  61. cpu_alert1: trip1 {
  62. temperature = <80000>;
  63. hysteresis = <2000>;
  64. type = "passive";
  65. };
  66. cpu_crit0: trip3 {
  67. temperature = <90000>;
  68. hysteresis = <2000>;
  69. type = "critical";
  70. };
  71. fan_toggle0: trip4 {
  72. temperature = <65000>;
  73. hysteresis = <10000>;
  74. type = "active";
  75. };
  76. };
  77. cooling-maps {
  78. map0 {
  79. trip = <&cpu_alert0>;
  80. cooling-device =
  81. <&A53_0 0 1>; /* Exclude highest OPP */
  82. };
  83. map1 {
  84. trip = <&cpu_alert1>;
  85. cooling-device =
  86. <&A53_0 0 2>; /* Exclude two highest OPPs */
  87. };
  88. map4 {
  89. trip = <&fan_toggle0>;
  90. cooling-device = <&fan 0 1>;
  91. };
  92. };
  93. };
  94. &i2c1 {
  95. clock-frequency = <400000>;
  96. pinctrl-names = "default";
  97. pinctrl-0 = <&pinctrl_i2c1>;
  98. status = "okay";
  99. pmic: pmic@4b {
  100. compatible = "rohm,bd71837";
  101. reg = <0x4b>;
  102. pinctrl-names = "default";
  103. pinctrl-0 = <&pinctrl_pmic>;
  104. #clock-cells = <0>;
  105. clocks = <&pmic_osc>;
  106. clock-output-names = "pmic_clk";
  107. interrupt-parent = <&gpio1>;
  108. interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
  109. regulators {
  110. buck1: BUCK1 {
  111. regulator-name = "buck1";
  112. regulator-min-microvolt = <700000>;
  113. regulator-max-microvolt = <1300000>;
  114. regulator-boot-on;
  115. regulator-always-on;
  116. regulator-ramp-delay = <1250>;
  117. rohm,dvs-run-voltage = <900000>;
  118. rohm,dvs-idle-voltage = <900000>;
  119. rohm,dvs-suspend-voltage = <800000>;
  120. };
  121. buck2: BUCK2 {
  122. regulator-name = "buck2";
  123. regulator-min-microvolt = <850000>;
  124. regulator-max-microvolt = <1000000>;
  125. regulator-boot-on;
  126. regulator-always-on;
  127. rohm,dvs-run-voltage = <1000000>;
  128. rohm,dvs-idle-voltage = <900000>;
  129. };
  130. buck3: BUCK3 {
  131. regulator-name = "buck3";
  132. regulator-min-microvolt = <700000>;
  133. regulator-max-microvolt = <1300000>;
  134. regulator-boot-on;
  135. rohm,dvs-run-voltage = <900000>;
  136. };
  137. buck4: BUCK4 {
  138. regulator-name = "buck4";
  139. regulator-min-microvolt = <700000>;
  140. regulator-max-microvolt = <1300000>;
  141. regulator-boot-on;
  142. regulator-always-on;
  143. rohm,dvs-run-voltage = <900000>;
  144. };
  145. buck5: BUCK5 {
  146. regulator-name = "buck5";
  147. regulator-min-microvolt = <700000>;
  148. regulator-max-microvolt = <1350000>;
  149. regulator-boot-on;
  150. regulator-always-on;
  151. };
  152. buck6: BUCK6 {
  153. regulator-name = "buck6";
  154. regulator-min-microvolt = <3000000>;
  155. regulator-max-microvolt = <3300000>;
  156. regulator-boot-on;
  157. regulator-always-on;
  158. };
  159. buck7: BUCK7 {
  160. regulator-name = "buck7";
  161. regulator-min-microvolt = <1605000>;
  162. regulator-max-microvolt = <1995000>;
  163. regulator-boot-on;
  164. regulator-always-on;
  165. };
  166. buck8: BUCK8 {
  167. regulator-name = "buck8";
  168. regulator-min-microvolt = <800000>;
  169. regulator-max-microvolt = <1400000>;
  170. regulator-boot-on;
  171. regulator-always-on;
  172. };
  173. ldo1: LDO1 {
  174. regulator-name = "ldo1";
  175. regulator-min-microvolt = <3000000>;
  176. regulator-max-microvolt = <3300000>;
  177. regulator-boot-on;
  178. regulator-always-on;
  179. };
  180. ldo2: LDO2 {
  181. regulator-name = "ldo2";
  182. regulator-min-microvolt = <900000>;
  183. regulator-max-microvolt = <900000>;
  184. regulator-boot-on;
  185. regulator-always-on;
  186. };
  187. ldo3: LDO3 {
  188. regulator-name = "ldo3";
  189. regulator-min-microvolt = <1800000>;
  190. regulator-max-microvolt = <3300000>;
  191. regulator-boot-on;
  192. regulator-always-on;
  193. };
  194. ldo4: LDO4 {
  195. regulator-name = "ldo4";
  196. regulator-min-microvolt = <900000>;
  197. regulator-max-microvolt = <1800000>;
  198. regulator-boot-on;
  199. regulator-always-on;
  200. };
  201. ldo5: LDO5 {
  202. regulator-name = "ldo5";
  203. regulator-min-microvolt = <1800000>;
  204. regulator-max-microvolt = <3300000>;
  205. regulator-boot-on;
  206. regulator-always-on;
  207. };
  208. ldo6: LDO6 {
  209. regulator-name = "ldo6";
  210. regulator-min-microvolt = <900000>;
  211. regulator-max-microvolt = <1800000>;
  212. regulator-boot-on;
  213. regulator-always-on;
  214. };
  215. ldo7: LDO7 {
  216. regulator-name = "ldo7";
  217. regulator-min-microvolt = <1800000>;
  218. regulator-max-microvolt = <3300000>;
  219. regulator-boot-on;
  220. regulator-always-on;
  221. };
  222. };
  223. };
  224. };
  225. &fec1 {
  226. pinctrl-names = "default";
  227. pinctrl-0 = <&pinctrl_fec1>;
  228. phy-mode = "rgmii-id";
  229. phy-handle = <&ethphy0>;
  230. fsl,magic-packet;
  231. status = "okay";
  232. mdio {
  233. #address-cells = <1>;
  234. #size-cells = <0>;
  235. ethphy0: ethernet-phy@0 {
  236. compatible = "ethernet-phy-ieee802.3-c22";
  237. reg = <0>;
  238. reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
  239. reset-assert-us = <10000>;
  240. reset-deassert-us = <50000>;
  241. };
  242. };
  243. };
  244. &uart1 {
  245. pinctrl-names = "default";
  246. pinctrl-0 = <&pinctrl_uart1>;
  247. status = "okay";
  248. };
  249. &usdhc1 {
  250. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  251. pinctrl-0 = <&pinctrl_usdhc1>;
  252. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  253. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  254. bus-width = <8>;
  255. non-removable;
  256. status = "okay";
  257. };
  258. &usdhc2 {
  259. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  260. pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  261. pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  262. pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  263. bus-width = <4>;
  264. cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
  265. vmmc-supply = <&reg_usdhc2_vmmc>;
  266. status = "okay";
  267. };
  268. &usb3_phy0 {
  269. status = "okay";
  270. };
  271. &usb_dwc3_0 {
  272. dr_mode = "otg";
  273. status = "okay";
  274. };
  275. &usb3_phy1 {
  276. status = "okay";
  277. };
  278. &usb_dwc3_1 {
  279. dr_mode = "host";
  280. status = "okay";
  281. };
  282. &wdog1 {
  283. pinctrl-names = "default";
  284. pinctrl-0 = <&pinctrl_wdog>;
  285. fsl,ext-reset-output;
  286. status = "okay";
  287. };
  288. &iomuxc {
  289. pinctrl_fec1: fec1grp {
  290. fsl,pins = <
  291. MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
  292. MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
  293. MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
  294. MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
  295. MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
  296. MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
  297. MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
  298. MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
  299. MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
  300. MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
  301. MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
  302. MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
  303. MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
  304. MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
  305. MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
  306. >;
  307. };
  308. pinctrl_gpio_fan: gpiofangrp {
  309. fsl,pins = <
  310. MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
  311. >;
  312. };
  313. pinctrl_i2c1: i2c1grp {
  314. fsl,pins = <
  315. MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
  316. MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
  317. >;
  318. };
  319. pinctrl_pmic: pmicirqgrp {
  320. fsl,pins = <
  321. MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
  322. >;
  323. };
  324. pinctrl_uart1: uart1grp {
  325. fsl,pins = <
  326. MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
  327. MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
  328. >;
  329. };
  330. pinctrl_usdhc1: usdhc1grp {
  331. fsl,pins = <
  332. MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
  333. MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
  334. MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
  335. MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
  336. MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
  337. MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
  338. MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
  339. MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
  340. MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
  341. MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
  342. MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
  343. MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
  344. >;
  345. };
  346. pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
  347. fsl,pins = <
  348. MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
  349. MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
  350. MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
  351. MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
  352. MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
  353. MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
  354. MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
  355. MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
  356. MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
  357. MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
  358. MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
  359. MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
  360. >;
  361. };
  362. pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
  363. fsl,pins = <
  364. MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
  365. MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
  366. MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
  367. MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
  368. MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
  369. MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
  370. MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
  371. MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
  372. MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
  373. MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
  374. MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
  375. MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
  376. >;
  377. };
  378. pinctrl_usdhc2_gpio: usdhc2gpiogrp {
  379. fsl,pins = <
  380. MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
  381. MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
  382. >;
  383. };
  384. pinctrl_usdhc2: usdhc2grp {
  385. fsl,pins = <
  386. MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
  387. MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
  388. MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
  389. MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
  390. MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
  391. MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
  392. MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
  393. >;
  394. };
  395. pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
  396. fsl,pins = <
  397. MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
  398. MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
  399. MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
  400. MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
  401. MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
  402. MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
  403. MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
  404. >;
  405. };
  406. pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
  407. fsl,pins = <
  408. MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
  409. MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
  410. MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
  411. MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
  412. MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
  413. MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
  414. MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
  415. >;
  416. };
  417. pinctrl_wdog: wdoggrp {
  418. fsl,pins = <
  419. MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
  420. >;
  421. };
  422. };