imx8mn-bsh-smm-s2-common.dtsi 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2021 Collabora Ltd.
  4. * Copyright 2021 BSH Hausgeraete GmbH
  5. */
  6. /dts-v1/;
  7. #include "imx8mn.dtsi"
  8. / {
  9. chosen {
  10. stdout-path = &uart4;
  11. };
  12. fec_supply: fec-supply-en {
  13. compatible = "regulator-fixed";
  14. vin-supply = <&buck4_reg>;
  15. regulator-name = "tja1101_en";
  16. regulator-min-microvolt = <3300000>;
  17. regulator-max-microvolt = <3300000>;
  18. gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  19. enable-active-high;
  20. };
  21. usdhc2_pwrseq: usdhc2-pwrseq {
  22. compatible = "mmc-pwrseq-simple";
  23. pinctrl-names = "default";
  24. pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
  25. reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
  26. };
  27. };
  28. &A53_0 {
  29. cpu-supply = <&buck2_reg>;
  30. };
  31. &A53_1 {
  32. cpu-supply = <&buck2_reg>;
  33. };
  34. &A53_2 {
  35. cpu-supply = <&buck2_reg>;
  36. };
  37. &A53_3 {
  38. cpu-supply = <&buck2_reg>;
  39. };
  40. &ecspi2 {
  41. pinctrl-names = "default";
  42. pinctrl-0 = <&pinctrl_espi2>;
  43. status = "okay";
  44. };
  45. &fec1 {
  46. pinctrl-names = "default";
  47. pinctrl-0 = <&pinctrl_fec1>;
  48. phy-mode = "rmii";
  49. phy-handle = <&ethphy0>;
  50. phy-supply = <&fec_supply>;
  51. fsl,magic-packet;
  52. status = "okay";
  53. mdio {
  54. #address-cells = <1>;
  55. #size-cells = <0>;
  56. ethphy0: ethernet-phy@0 {
  57. compatible = "ethernet-phy-ieee802.3-c22";
  58. reg = <0>;
  59. reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
  60. reset-assert-us = <20>;
  61. reset-deassert-us = <2000>;
  62. };
  63. };
  64. };
  65. &i2c1 {
  66. clock-frequency = <400000>;
  67. pinctrl-names = "default";
  68. pinctrl-0 = <&pinctrl_i2c1>;
  69. status = "okay";
  70. bd71847: pmic@4b {
  71. compatible = "rohm,bd71847";
  72. reg = <0x4b>;
  73. pinctrl-names = "default";
  74. pinctrl-0 = <&pinctrl_pmic>;
  75. interrupt-parent = <&gpio1>;
  76. interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
  77. rohm,reset-snvs-powered;
  78. #clock-cells = <0>;
  79. clocks = <&osc_32k 0>;
  80. clock-output-names = "clk-32k-out";
  81. regulators {
  82. buck1_reg: BUCK1 {
  83. /* PMIC_BUCK1 - VDD_SOC */
  84. regulator-name = "buck1";
  85. regulator-min-microvolt = <700000>;
  86. regulator-max-microvolt = <1300000>;
  87. regulator-boot-on;
  88. regulator-always-on;
  89. regulator-ramp-delay = <1250>;
  90. };
  91. buck2_reg: BUCK2 {
  92. /* PMIC_BUCK2 - VDD_ARM */
  93. regulator-name = "buck2";
  94. regulator-min-microvolt = <700000>;
  95. regulator-max-microvolt = <1300000>;
  96. regulator-boot-on;
  97. regulator-always-on;
  98. regulator-ramp-delay = <1250>;
  99. };
  100. buck3_reg: BUCK3 {
  101. /* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */
  102. regulator-name = "buck3";
  103. regulator-min-microvolt = <700000>;
  104. regulator-max-microvolt = <1350000>;
  105. regulator-boot-on;
  106. regulator-always-on;
  107. };
  108. buck4_reg: BUCK4 {
  109. /* PMIC_BUCK6 - VDD_3V3 */
  110. regulator-name = "buck4";
  111. regulator-min-microvolt = <3000000>;
  112. regulator-max-microvolt = <3300000>;
  113. regulator-boot-on;
  114. regulator-always-on;
  115. };
  116. buck5_reg: BUCK5 {
  117. /* PMIC_BUCK7 - VDD_1V8 */
  118. regulator-name = "buck5";
  119. regulator-min-microvolt = <1605000>;
  120. regulator-max-microvolt = <1995000>;
  121. regulator-boot-on;
  122. regulator-always-on;
  123. };
  124. buck6_reg: BUCK6 {
  125. /* PMIC_BUCK8 - NVCC_DRAM */
  126. regulator-name = "buck6";
  127. regulator-min-microvolt = <800000>;
  128. regulator-max-microvolt = <1400000>;
  129. regulator-boot-on;
  130. regulator-always-on;
  131. };
  132. ldo1_reg: LDO1 {
  133. /* PMIC_LDO1 - NVCC_SNVS_1V8 */
  134. regulator-name = "ldo1";
  135. regulator-min-microvolt = <1600000>;
  136. regulator-max-microvolt = <1900000>;
  137. regulator-boot-on;
  138. regulator-always-on;
  139. };
  140. ldo2_reg: LDO2 {
  141. /* PMIC_LDO2 - VDD_SNVS_0V8 */
  142. regulator-name = "ldo2";
  143. regulator-min-microvolt = <800000>;
  144. regulator-max-microvolt = <900000>;
  145. regulator-boot-on;
  146. regulator-always-on;
  147. };
  148. ldo3_reg: LDO3 {
  149. /* PMIC_LDO3 - VDDA_1V8 */
  150. regulator-name = "ldo3";
  151. regulator-min-microvolt = <1800000>;
  152. regulator-max-microvolt = <3300000>;
  153. regulator-boot-on;
  154. regulator-always-on;
  155. };
  156. ldo4_reg: LDO4 {
  157. /* PMIC_LDO4 - VDD_MIPI_0V9 */
  158. regulator-name = "ldo4";
  159. regulator-min-microvolt = <900000>;
  160. regulator-max-microvolt = <1800000>;
  161. regulator-boot-on;
  162. regulator-always-on;
  163. };
  164. ldo6_reg: LDO6 {
  165. /* PMIC_LDO6 - VDD_MIPI_1V2 */
  166. regulator-name = "ldo6";
  167. regulator-min-microvolt = <900000>;
  168. regulator-max-microvolt = <1800000>;
  169. regulator-boot-on;
  170. regulator-always-on;
  171. };
  172. };
  173. };
  174. };
  175. &i2c3 {
  176. clock-frequency = <400000>;
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&pinctrl_i2c3>;
  179. status = "okay";
  180. };
  181. &i2c4 {
  182. clock-frequency = <400000>;
  183. pinctrl-names = "default";
  184. pinctrl-0 = <&pinctrl_i2c4>;
  185. status = "okay";
  186. };
  187. &uart2 {
  188. pinctrl-names = "default";
  189. pinctrl-0 = <&pinctrl_uart2>;
  190. status = "okay";
  191. };
  192. &uart3 {
  193. pinctrl-names = "default";
  194. pinctrl-0 = <&pinctrl_uart3>;
  195. assigned-clocks = <&clk IMX8MN_CLK_UART3>;
  196. assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
  197. uart-has-rtscts;
  198. status = "okay";
  199. bluetooth {
  200. compatible = "brcm,bcm43438-bt";
  201. pinctrl-names = "default";
  202. pinctrl-0 = <&pinctrl_bluetooth>;
  203. shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
  204. device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
  205. host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  206. max-speed = <3000000>;
  207. };
  208. };
  209. /* Console */
  210. &uart4 {
  211. pinctrl-names = "default";
  212. pinctrl-0 = <&pinctrl_uart4>;
  213. status = "okay";
  214. };
  215. &usbotg1 {
  216. dr_mode = "peripheral";
  217. disable-over-current;
  218. status = "okay";
  219. };
  220. &usdhc2 {
  221. #address-cells = <1>;
  222. #size-cells = <0>;
  223. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  224. pinctrl-0 = <&pinctrl_usdhc2>;
  225. pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
  226. pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
  227. mmc-pwrseq = <&usdhc2_pwrseq>;
  228. bus-width = <4>;
  229. non-removable;
  230. status = "okay";
  231. brcmf: bcrmf@1 {
  232. compatible = "brcm,bcm4329-fmac";
  233. reg = <1>;
  234. pinctrl-names = "default";
  235. pinctrl-0 = <&pinctrl_wlan>;
  236. interrupt-parent = <&gpio1>;
  237. interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
  238. interrupt-names = "host-wake";
  239. };
  240. };
  241. &wdog1 {
  242. pinctrl-names = "default";
  243. pinctrl-0 = <&pinctrl_wdog>;
  244. fsl,ext-reset-output;
  245. status = "okay";
  246. };
  247. &iomuxc {
  248. pinctrl_bluetooth: bluetoothgrp {
  249. fsl,pins = <
  250. MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */
  251. MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */
  252. MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */
  253. >;
  254. };
  255. pinctrl_espi2: espi2grp {
  256. fsl,pins = <
  257. MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
  258. MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
  259. MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
  260. MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
  261. >;
  262. };
  263. pinctrl_fec1: fec1grp {
  264. fsl,pins = <
  265. MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002
  266. MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002
  267. MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090
  268. MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090
  269. MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090
  270. MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016
  271. MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016
  272. MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016
  273. MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016
  274. MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090
  275. MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016
  276. MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */
  277. MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */
  278. MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */
  279. MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */
  280. >;
  281. };
  282. pinctrl_i2c1: i2c1grp {
  283. fsl,pins = <
  284. MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2
  285. MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2
  286. >;
  287. };
  288. pinctrl_i2c3: i2c3grp {
  289. fsl,pins = <
  290. MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2
  291. MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2
  292. >;
  293. };
  294. pinctrl_i2c4: i2c4grp {
  295. fsl,pins = <
  296. MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2
  297. MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2
  298. >;
  299. };
  300. pinctrl_pmic: pmicirq {
  301. fsl,pins = <
  302. MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040
  303. >;
  304. };
  305. pinctrl_uart2: uart2grp {
  306. fsl,pins = <
  307. MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040
  308. MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040
  309. >;
  310. };
  311. pinctrl_uart3: uart3grp {
  312. fsl,pins = <
  313. MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040
  314. MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040
  315. MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040
  316. MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040
  317. >;
  318. };
  319. pinctrl_uart4: uart4grp {
  320. fsl,pins = <
  321. MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040
  322. MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040
  323. >;
  324. };
  325. pinctrl_usdhc2: usdhc2grp {
  326. fsl,pins = <
  327. MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090
  328. MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0
  329. MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0
  330. MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0
  331. MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0
  332. MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0
  333. >;
  334. };
  335. pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  336. fsl,pins = <
  337. MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094
  338. MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4
  339. MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4
  340. MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4
  341. MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4
  342. MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4
  343. >;
  344. };
  345. pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  346. fsl,pins = <
  347. MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096
  348. MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6
  349. MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6
  350. MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6
  351. MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6
  352. MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6
  353. >;
  354. };
  355. pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {
  356. fsl,pins = <
  357. MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */
  358. >;
  359. };
  360. pinctrl_wdog: wdoggrp {
  361. fsl,pins = <
  362. MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046
  363. >;
  364. };
  365. pinctrl_wlan: wlangrp {
  366. fsl,pins = <
  367. MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */
  368. MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */
  369. MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */
  370. MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */
  371. >;
  372. };
  373. };