imx8mm-prt8mm.dts 6.7 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright 2020 Protonic Holland
  4. * Copyright 2019 NXP
  5. */
  6. /dts-v1/;
  7. #include <dt-bindings/usb/pd.h>
  8. #include "imx8mm.dtsi"
  9. / {
  10. model = "Protonic PRT8MM";
  11. compatible = "prt,prt8mm", "fsl,imx8mm";
  12. chosen {
  13. stdout-path = &uart4;
  14. };
  15. memory@40000000 {
  16. device_type = "memory";
  17. reg = <0x0 0x40000000 0 0x40000000>;
  18. };
  19. leds {
  20. compatible = "gpio-leds";
  21. pinctrl-names = "default";
  22. pinctrl-0 = <&pinctrl_gpio_leds>;
  23. debug-led0 {
  24. label = "DEBUG_LED0";
  25. gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
  26. linux,default-trigger = "heartbeat";
  27. };
  28. debug-led1 {
  29. label = "DEBUG_LED1";
  30. gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
  31. linux,default-trigger = "cpu";
  32. };
  33. };
  34. sound-ssm2518 {
  35. compatible = "simple-audio-card";
  36. simple-audio-card,name = "ssm2518-audio";
  37. simple-audio-card,format = "i2s";
  38. simple-audio-card,frame-master = <&cpudai>;
  39. simple-audio-card,bitclock-master = <&cpudai>;
  40. cpudai: simple-audio-card,cpu {
  41. sound-dai = <&sai3>;
  42. };
  43. simple-audio-card,codec {
  44. sound-dai = <&ssm2518>;
  45. clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
  46. };
  47. };
  48. };
  49. &i2c1 {
  50. clock-frequency = <400000>;
  51. pinctrl-names = "default";
  52. pinctrl-0 = <&pinctrl_i2c1>;
  53. status = "okay";
  54. ssm2518: audio-codec@34 {
  55. compatible = "adi,ssm2518";
  56. reg = <0x34>;
  57. #sound-dai-cells = <0>;
  58. };
  59. };
  60. &i2c2 {
  61. clock-frequency = <400000>;
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&pinctrl_i2c2>;
  64. status = "okay";
  65. regulator@60 {
  66. compatible = "fcs,fan53555";
  67. reg = <0x60>;
  68. regulator-name = "0V9_CORE";
  69. regulator-min-microvolt = <900000>;
  70. regulator-max-microvolt = <980000>;
  71. regulator-boot-on;
  72. regulator-always-on;
  73. };
  74. };
  75. &i2c3 {
  76. clock-frequency = <400000>;
  77. pinctrl-names = "default";
  78. pinctrl-0 = <&pinctrl_i2c3>;
  79. status = "okay";
  80. rtc@51 {
  81. compatible = "nxp,pcf85363";
  82. reg = <0x51>;
  83. };
  84. touchscreeen@5d {
  85. compatible = "goodix,gt911";
  86. reg = <0x5d>;
  87. pinctrl-names = "default";
  88. pinctrl-0 = <&pinctrl_touchscreen>;
  89. interrupt-parent = <&gpio1>;
  90. interrupts = <8 IRQ_TYPE_NONE>;
  91. irq-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  92. reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  93. };
  94. temp-sense@70 {
  95. compatible = "ti,tmp103";
  96. reg = <0x70>;
  97. };
  98. };
  99. &sai3 {
  100. pinctrl-names = "default";
  101. pinctrl-0 = <&pinctrl_sai3>;
  102. assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
  103. assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  104. assigned-clock-rates = <12288000>;
  105. fsl,sai-mclk-direction-output;
  106. fsl,sai-asynchronous;
  107. status = "okay";
  108. };
  109. &snvs_pwrkey {
  110. status = "okay";
  111. };
  112. &uart4 {
  113. pinctrl-names = "default";
  114. pinctrl-0 = <&pinctrl_uart4>;
  115. status = "okay";
  116. };
  117. &usbotg1 {
  118. pinctrl-names = "default";
  119. pinctrl-0 = <&pinctrl_usbotg1>;
  120. dr_mode = "host";
  121. disable-over-current;
  122. power-active-high;
  123. status = "okay";
  124. };
  125. &usdhc2 {
  126. pinctrl-names = "default";
  127. pinctrl-0 = <&pinctrl_usdhc2>;
  128. assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
  129. assigned-clock-rates = <100000000>;
  130. cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
  131. bus-width = <4>;
  132. status = "okay";
  133. };
  134. &usdhc3 {
  135. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  136. pinctrl-0 = <&pinctrl_usdhc3>;
  137. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  138. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  139. assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
  140. assigned-clock-rates = <400000000>;
  141. bus-width = <8>;
  142. non-removable;
  143. no-sdio;
  144. no-sd;
  145. status = "okay";
  146. };
  147. &wdog1 {
  148. pinctrl-names = "default";
  149. pinctrl-0 = <&pinctrl_wdog>;
  150. fsl,ext-reset-output;
  151. status = "okay";
  152. };
  153. &iomuxc {
  154. pinctrl_gpio_leds: ledsgrp {
  155. fsl,pins = <
  156. MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x00
  157. MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x00
  158. >;
  159. };
  160. pinctrl_i2c1: i2c1grp {
  161. fsl,pins = <
  162. MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c3
  163. MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c3
  164. >;
  165. };
  166. pinctrl_i2c2: i2c2grp {
  167. fsl,pins = <
  168. MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3
  169. MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3
  170. >;
  171. };
  172. pinctrl_i2c3: i2c3grp {
  173. fsl,pins = <
  174. MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c3
  175. MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c3
  176. >;
  177. };
  178. pinctrl_sai3: sai3grp {
  179. fsl,pins = <
  180. MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
  181. MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
  182. MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
  183. MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
  184. >;
  185. };
  186. pinctrl_touchscreen: tsgrp {
  187. fsl,pins = <
  188. MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x80
  189. MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80
  190. >;
  191. };
  192. pinctrl_uart4: uart4grp {
  193. fsl,pins = <
  194. MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040
  195. MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040
  196. >;
  197. };
  198. pinctrl_usbotg1: usbotg1grp {
  199. fsl,pins = <
  200. MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x000
  201. MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x000
  202. >;
  203. };
  204. pinctrl_usdhc2: usdhc2grp {
  205. fsl,pins = <
  206. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
  207. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
  208. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
  209. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
  210. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
  211. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
  212. MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0d4
  213. >;
  214. };
  215. pinctrl_usdhc3: usdhc3grp {
  216. fsl,pins = <
  217. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
  218. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
  219. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
  220. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
  221. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
  222. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
  223. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
  224. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
  225. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
  226. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
  227. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
  228. >;
  229. };
  230. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  231. fsl,pins = <
  232. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
  233. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
  234. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
  235. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
  236. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
  237. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
  238. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
  239. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
  240. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
  241. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
  242. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
  243. >;
  244. };
  245. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  246. fsl,pins = <
  247. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
  248. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
  249. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
  250. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
  251. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
  252. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
  253. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
  254. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
  255. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
  256. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
  257. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
  258. >;
  259. };
  260. pinctrl_wdog: wdoggrp {
  261. fsl,pins = <
  262. MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
  263. >;
  264. };
  265. };