imx8mm-mx8menlo.dts 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR MIT
  2. /*
  3. * Copyright 2021-2022 Marek Vasut <[email protected]>
  4. */
  5. /dts-v1/;
  6. #include "imx8mm-verdin.dtsi"
  7. / {
  8. model = "MENLO MX8MM EMBEDDED DEVICE";
  9. compatible = "menlo,mx8menlo",
  10. "toradex,verdin-imx8mm",
  11. "fsl,imx8mm";
  12. /delete-node/ gpio-keys;
  13. leds {
  14. compatible = "gpio-leds";
  15. pinctrl-names = "default";
  16. pinctrl-0 = <&pinctrl_led>;
  17. led-1 {
  18. label = "TestLed601";
  19. gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
  20. linux,default-trigger = "mmc0";
  21. };
  22. led-2 {
  23. label = "TestLed602";
  24. gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
  25. linux,default-trigger = "heartbeat";
  26. };
  27. };
  28. beeper {
  29. compatible = "gpio-beeper";
  30. pinctrl-names = "default";
  31. pinctrl-0 = <&pinctrl_beeper>;
  32. gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
  33. };
  34. /* Fixed clock dedicated to SPI CAN on carrier board */
  35. clk_xtal20: clk-xtal20 {
  36. compatible = "fixed-clock";
  37. #clock-cells = <0>;
  38. clock-frequency = <20000000>;
  39. };
  40. };
  41. &ecspi1 {
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. pinctrl-names = "default";
  45. pinctrl-0 = <&pinctrl_ecspi1>;
  46. cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
  47. status = "okay";
  48. /* CAN controller on the baseboard */
  49. canfd: can@0 {
  50. compatible = "microchip,mcp2518fd";
  51. clocks = <&clk_xtal20>;
  52. interrupt-parent = <&gpio1>;
  53. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  54. reg = <0>;
  55. spi-max-frequency = <2000000>;
  56. };
  57. };
  58. &ecspi2 {
  59. pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
  60. cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
  61. status = "okay";
  62. spidev@0 {
  63. compatible = "menlo,m53cpld";
  64. reg = <0>;
  65. spi-max-frequency = <25000000>;
  66. };
  67. spidev@1 {
  68. compatible = "menlo,m53cpld";
  69. reg = <1>;
  70. spi-max-frequency = <25000000>;
  71. };
  72. };
  73. &ethphy0 {
  74. max-speed = <100>;
  75. };
  76. &fec1 {
  77. status = "okay";
  78. };
  79. &flexspi {
  80. status = "okay";
  81. flash@0 {
  82. reg = <0>;
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. compatible = "jedec,spi-nor";
  86. spi-max-frequency = <66000000>;
  87. spi-rx-bus-width = <4>;
  88. spi-tx-bus-width = <4>;
  89. };
  90. };
  91. &gpio1 {
  92. gpio-line-names =
  93. "", "", "", "",
  94. "", "", "", "",
  95. "", "", "", "",
  96. "", "", "", "",
  97. "", "", "", "",
  98. "", "", "", "",
  99. "", "", "", "",
  100. "", "", "", "";
  101. };
  102. &gpio2 {
  103. gpio-line-names =
  104. "", "", "", "",
  105. "", "", "", "",
  106. "", "", "", "",
  107. "", "", "", "",
  108. "", "", "", "",
  109. "", "", "", "",
  110. "", "", "", "",
  111. "", "", "", "";
  112. };
  113. &gpio3 {
  114. gpio-line-names =
  115. "", "", "", "",
  116. "", "", "", "",
  117. "", "", "", "",
  118. "", "", "", "",
  119. "", "", "", "",
  120. "", "", "DISP_reset", "KBD_intI",
  121. "", "", "", "",
  122. "", "", "", "";
  123. };
  124. &gpio4 {
  125. /*
  126. * CPLD_D[n] is ARM_CPLD[n] in schematic
  127. * CPLD_int is SA_INTERRUPT in schematic
  128. * CPLD_reset is RESET_SOFT in schematic
  129. */
  130. gpio-line-names =
  131. "CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
  132. "", "CPLD_D[7]", "", "",
  133. "", "", "", "CPLD_D[5]",
  134. "CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
  135. "CPLD_D[0]", "", "", "",
  136. "", "", "", "",
  137. "", "", "", "KBD_intK",
  138. "", "", "", "";
  139. };
  140. &gpio5 {
  141. gpio-line-names =
  142. "", "", "", "",
  143. "", "", "", "",
  144. "", "", "", "",
  145. "", "", "", "",
  146. "", "", "", "",
  147. "", "", "", "",
  148. "", "", "", "",
  149. "", "", "", "";
  150. };
  151. &gpio_expander_21 {
  152. status = "okay";
  153. };
  154. &hwmon {
  155. status = "okay";
  156. };
  157. &i2c3 {
  158. status = "okay";
  159. };
  160. &i2c4 {
  161. /* None of this is present on the SoM. */
  162. /delete-node/ bridge@2c;
  163. /delete-node/ hdmi@48;
  164. /delete-node/ touch@4a;
  165. /delete-node/ sensor@4f;
  166. /delete-node/ eeprom@50;
  167. /delete-node/ eeprom@57;
  168. };
  169. &iomuxc {
  170. pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
  171. <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
  172. pinctrl_beeper: beepergrp {
  173. fsl,pins = <
  174. MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4
  175. >;
  176. };
  177. pinctrl_ecspi1: ecspi1grp {
  178. fsl,pins = <
  179. MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4
  180. MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4
  181. MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4
  182. MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4
  183. >;
  184. };
  185. pinctrl_led: ledgrp {
  186. fsl,pins = <
  187. MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4
  188. MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4
  189. >;
  190. };
  191. pinctrl_uart4_rts: uart4rtsgrp {
  192. fsl,pins = <
  193. /* SODIMM 222 */
  194. MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
  195. >;
  196. };
  197. };
  198. &pinctrl_gpio1 {
  199. fsl,pins = <
  200. /* SODIMM 206 */
  201. MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4
  202. >;
  203. };
  204. &pinctrl_gpio_hog1 {
  205. fsl,pins = <
  206. /* SODIMM 88 */
  207. MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4
  208. /* CPLD_int */
  209. MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4
  210. /* CPLD_reset */
  211. MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4
  212. /* SODIMM 94 */
  213. MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4
  214. /* SODIMM 96 */
  215. MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
  216. /* CPLD_D[7] */
  217. MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x184
  218. /* CPLD_D[6] */
  219. MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x184
  220. /* CPLD_D[5] */
  221. MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x184
  222. /* CPLD_D[4] */
  223. MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x184
  224. /* CPLD_D[3] */
  225. MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x184
  226. /* CPLD_D[2] */
  227. MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x184
  228. /* CPLD_D[1] */
  229. MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x184
  230. /* CPLD_D[0] */
  231. MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x184
  232. /* KBD_intK */
  233. MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
  234. /* DISP_reset */
  235. MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4
  236. /* KBD_intI */
  237. MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4
  238. /* SODIMM 46 */
  239. MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4
  240. >;
  241. };
  242. &pinctrl_uart1 {
  243. fsl,pins = <
  244. /* SODIMM 149 */
  245. MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4
  246. /* SODIMM 147 */
  247. MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4
  248. /* SODIMM 210 */
  249. MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4
  250. /* SODIMM 212 */
  251. MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4
  252. >;
  253. };
  254. &reg_usb_otg1_vbus {
  255. /delete-property/ enable-active-high;
  256. gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
  257. };
  258. &reg_usb_otg2_vbus {
  259. /delete-property/ enable-active-high;
  260. gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
  261. };
  262. &sai2 {
  263. status = "disabled";
  264. };
  265. &uart1 {
  266. uart-has-rtscts;
  267. status = "okay";
  268. };
  269. &uart2 {
  270. status = "okay";
  271. };
  272. &uart4 {
  273. pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
  274. linux,rs485-enabled-at-boot-time;
  275. rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  276. status = "okay";
  277. };
  278. &usbotg1 {
  279. dr_mode = "peripheral";
  280. status = "okay";
  281. };
  282. &usbotg2 {
  283. dr_mode = "host";
  284. status = "okay";
  285. };
  286. &usdhc2 {
  287. status = "okay";
  288. };