imx8mm-evk.dtsi 14 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright 2020 NXP
  4. */
  5. /dts-v1/;
  6. #include <dt-bindings/phy/phy-imx8-pcie.h>
  7. #include <dt-bindings/usb/pd.h>
  8. #include "imx8mm.dtsi"
  9. / {
  10. chosen {
  11. stdout-path = &uart2;
  12. };
  13. memory@40000000 {
  14. device_type = "memory";
  15. reg = <0x0 0x40000000 0 0x80000000>;
  16. };
  17. leds {
  18. compatible = "gpio-leds";
  19. pinctrl-names = "default";
  20. pinctrl-0 = <&pinctrl_gpio_led>;
  21. status {
  22. label = "status";
  23. gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  24. default-state = "on";
  25. };
  26. };
  27. pcie0_refclk: pcie0-refclk {
  28. compatible = "fixed-clock";
  29. #clock-cells = <0>;
  30. clock-frequency = <100000000>;
  31. };
  32. reg_pcie0: regulator-pcie {
  33. compatible = "regulator-fixed";
  34. pinctrl-names = "default";
  35. pinctrl-0 = <&pinctrl_pcie0_reg>;
  36. regulator-name = "MPCIE_3V3";
  37. regulator-min-microvolt = <3300000>;
  38. regulator-max-microvolt = <3300000>;
  39. gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  40. enable-active-high;
  41. };
  42. reg_usdhc2_vmmc: regulator-usdhc2 {
  43. compatible = "regulator-fixed";
  44. pinctrl-names = "default";
  45. pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  46. regulator-name = "VSD_3V3";
  47. regulator-min-microvolt = <3300000>;
  48. regulator-max-microvolt = <3300000>;
  49. gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  50. enable-active-high;
  51. };
  52. backlight: backlight {
  53. compatible = "pwm-backlight";
  54. pwms = <&pwm1 0 5000000 0>;
  55. brightness-levels = <0 255>;
  56. num-interpolated-steps = <255>;
  57. default-brightness-level = <250>;
  58. };
  59. ir-receiver {
  60. compatible = "gpio-ir-receiver";
  61. gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&pinctrl_ir>;
  64. linux,autosuspend-period = <125>;
  65. };
  66. audio_codec_bt_sco: audio-codec-bt-sco {
  67. compatible = "linux,bt-sco";
  68. #sound-dai-cells = <1>;
  69. };
  70. wm8524: audio-codec {
  71. #sound-dai-cells = <0>;
  72. compatible = "wlf,wm8524";
  73. pinctrl-names = "default";
  74. pinctrl-0 = <&pinctrl_gpio_wlf>;
  75. wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
  76. };
  77. sound-bt-sco {
  78. compatible = "simple-audio-card";
  79. simple-audio-card,name = "bt-sco-audio";
  80. simple-audio-card,format = "dsp_a";
  81. simple-audio-card,bitclock-inversion;
  82. simple-audio-card,frame-master = <&btcpu>;
  83. simple-audio-card,bitclock-master = <&btcpu>;
  84. btcpu: simple-audio-card,cpu {
  85. sound-dai = <&sai2>;
  86. dai-tdm-slot-num = <2>;
  87. dai-tdm-slot-width = <16>;
  88. };
  89. simple-audio-card,codec {
  90. sound-dai = <&audio_codec_bt_sco 1>;
  91. };
  92. };
  93. sound-wm8524 {
  94. compatible = "simple-audio-card";
  95. simple-audio-card,name = "wm8524-audio";
  96. simple-audio-card,format = "i2s";
  97. simple-audio-card,frame-master = <&cpudai>;
  98. simple-audio-card,bitclock-master = <&cpudai>;
  99. simple-audio-card,widgets =
  100. "Line", "Left Line Out Jack",
  101. "Line", "Right Line Out Jack";
  102. simple-audio-card,routing =
  103. "Left Line Out Jack", "LINEVOUTL",
  104. "Right Line Out Jack", "LINEVOUTR";
  105. cpudai: simple-audio-card,cpu {
  106. sound-dai = <&sai3>;
  107. dai-tdm-slot-num = <2>;
  108. dai-tdm-slot-width = <32>;
  109. };
  110. simple-audio-card,codec {
  111. sound-dai = <&wm8524>;
  112. clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
  113. };
  114. };
  115. };
  116. &A53_0 {
  117. cpu-supply = <&buck2_reg>;
  118. };
  119. &A53_1 {
  120. cpu-supply = <&buck2_reg>;
  121. };
  122. &A53_2 {
  123. cpu-supply = <&buck2_reg>;
  124. };
  125. &A53_3 {
  126. cpu-supply = <&buck2_reg>;
  127. };
  128. &fec1 {
  129. pinctrl-names = "default";
  130. pinctrl-0 = <&pinctrl_fec1>;
  131. phy-mode = "rgmii-id";
  132. phy-handle = <&ethphy0>;
  133. fsl,magic-packet;
  134. status = "okay";
  135. mdio {
  136. #address-cells = <1>;
  137. #size-cells = <0>;
  138. ethphy0: ethernet-phy@0 {
  139. compatible = "ethernet-phy-ieee802.3-c22";
  140. reg = <0>;
  141. reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
  142. reset-assert-us = <10000>;
  143. qca,disable-smarteee;
  144. vddio-supply = <&vddio>;
  145. vddio: vddio-regulator {
  146. regulator-min-microvolt = <1800000>;
  147. regulator-max-microvolt = <1800000>;
  148. };
  149. };
  150. };
  151. };
  152. &i2c1 {
  153. clock-frequency = <400000>;
  154. pinctrl-names = "default";
  155. pinctrl-0 = <&pinctrl_i2c1>;
  156. status = "okay";
  157. pmic@4b {
  158. compatible = "rohm,bd71847";
  159. reg = <0x4b>;
  160. pinctrl-names = "default";
  161. pinctrl-0 = <&pinctrl_pmic>;
  162. interrupt-parent = <&gpio1>;
  163. interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
  164. rohm,reset-snvs-powered;
  165. #clock-cells = <0>;
  166. clocks = <&osc_32k>;
  167. clock-output-names = "clk-32k-out";
  168. regulators {
  169. buck1_reg: BUCK1 {
  170. regulator-name = "buck1";
  171. regulator-min-microvolt = <700000>;
  172. regulator-max-microvolt = <1300000>;
  173. regulator-boot-on;
  174. regulator-always-on;
  175. regulator-ramp-delay = <1250>;
  176. };
  177. buck2_reg: BUCK2 {
  178. regulator-name = "buck2";
  179. regulator-min-microvolt = <700000>;
  180. regulator-max-microvolt = <1300000>;
  181. regulator-boot-on;
  182. regulator-always-on;
  183. regulator-ramp-delay = <1250>;
  184. rohm,dvs-run-voltage = <1000000>;
  185. rohm,dvs-idle-voltage = <900000>;
  186. };
  187. buck3_reg: BUCK3 {
  188. // BUCK5 in datasheet
  189. regulator-name = "buck3";
  190. regulator-min-microvolt = <700000>;
  191. regulator-max-microvolt = <1350000>;
  192. regulator-boot-on;
  193. regulator-always-on;
  194. };
  195. buck4_reg: BUCK4 {
  196. // BUCK6 in datasheet
  197. regulator-name = "buck4";
  198. regulator-min-microvolt = <3000000>;
  199. regulator-max-microvolt = <3300000>;
  200. regulator-boot-on;
  201. regulator-always-on;
  202. };
  203. buck5_reg: BUCK5 {
  204. // BUCK7 in datasheet
  205. regulator-name = "buck5";
  206. regulator-min-microvolt = <1605000>;
  207. regulator-max-microvolt = <1995000>;
  208. regulator-boot-on;
  209. regulator-always-on;
  210. };
  211. buck6_reg: BUCK6 {
  212. // BUCK8 in datasheet
  213. regulator-name = "buck6";
  214. regulator-min-microvolt = <800000>;
  215. regulator-max-microvolt = <1400000>;
  216. regulator-boot-on;
  217. regulator-always-on;
  218. };
  219. ldo1_reg: LDO1 {
  220. regulator-name = "ldo1";
  221. regulator-min-microvolt = <1600000>;
  222. regulator-max-microvolt = <3300000>;
  223. regulator-boot-on;
  224. regulator-always-on;
  225. };
  226. ldo2_reg: LDO2 {
  227. regulator-name = "ldo2";
  228. regulator-min-microvolt = <800000>;
  229. regulator-max-microvolt = <900000>;
  230. regulator-boot-on;
  231. regulator-always-on;
  232. };
  233. ldo3_reg: LDO3 {
  234. regulator-name = "ldo3";
  235. regulator-min-microvolt = <1800000>;
  236. regulator-max-microvolt = <3300000>;
  237. regulator-boot-on;
  238. regulator-always-on;
  239. };
  240. ldo4_reg: LDO4 {
  241. regulator-name = "ldo4";
  242. regulator-min-microvolt = <900000>;
  243. regulator-max-microvolt = <1800000>;
  244. regulator-boot-on;
  245. regulator-always-on;
  246. };
  247. ldo6_reg: LDO6 {
  248. regulator-name = "ldo6";
  249. regulator-min-microvolt = <900000>;
  250. regulator-max-microvolt = <1800000>;
  251. regulator-boot-on;
  252. regulator-always-on;
  253. };
  254. };
  255. };
  256. };
  257. &i2c2 {
  258. clock-frequency = <400000>;
  259. pinctrl-names = "default";
  260. pinctrl-0 = <&pinctrl_i2c2>;
  261. status = "okay";
  262. ptn5110: tcpc@50 {
  263. compatible = "nxp,ptn5110";
  264. pinctrl-names = "default";
  265. pinctrl-0 = <&pinctrl_typec1>;
  266. reg = <0x50>;
  267. interrupt-parent = <&gpio2>;
  268. interrupts = <11 8>;
  269. status = "okay";
  270. port {
  271. typec1_dr_sw: endpoint {
  272. remote-endpoint = <&usb1_drd_sw>;
  273. };
  274. };
  275. typec1_con: connector {
  276. compatible = "usb-c-connector";
  277. label = "USB-C";
  278. power-role = "dual";
  279. data-role = "dual";
  280. try-power-role = "sink";
  281. source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
  282. sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
  283. PDO_VAR(5000, 20000, 3000)>;
  284. op-sink-microwatt = <15000000>;
  285. self-powered;
  286. };
  287. };
  288. };
  289. &i2c3 {
  290. clock-frequency = <400000>;
  291. pinctrl-names = "default";
  292. pinctrl-0 = <&pinctrl_i2c3>;
  293. status = "okay";
  294. pca6416: gpio@20 {
  295. compatible = "ti,tca6416";
  296. reg = <0x20>;
  297. gpio-controller;
  298. #gpio-cells = <2>;
  299. };
  300. };
  301. &pcie_phy {
  302. fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
  303. fsl,tx-deemph-gen1 = <0x2d>;
  304. fsl,tx-deemph-gen2 = <0xf>;
  305. clocks = <&pcie0_refclk>;
  306. status = "okay";
  307. };
  308. &pcie0 {
  309. pinctrl-names = "default";
  310. pinctrl-0 = <&pinctrl_pcie0>;
  311. reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
  312. clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
  313. <&pcie0_refclk>;
  314. clock-names = "pcie", "pcie_aux", "pcie_bus";
  315. assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
  316. <&clk IMX8MM_CLK_PCIE1_CTRL>;
  317. assigned-clock-rates = <10000000>, <250000000>;
  318. assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
  319. <&clk IMX8MM_SYS_PLL2_250M>;
  320. vpcie-supply = <&reg_pcie0>;
  321. status = "okay";
  322. };
  323. &sai2 {
  324. #sound-dai-cells = <0>;
  325. pinctrl-names = "default";
  326. pinctrl-0 = <&pinctrl_sai2>;
  327. assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
  328. assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  329. assigned-clock-rates = <24576000>;
  330. status = "okay";
  331. };
  332. &sai3 {
  333. pinctrl-names = "default";
  334. pinctrl-0 = <&pinctrl_sai3>;
  335. assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
  336. assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  337. assigned-clock-rates = <24576000>;
  338. status = "okay";
  339. };
  340. &snvs_pwrkey {
  341. status = "okay";
  342. };
  343. &uart2 { /* console */
  344. pinctrl-names = "default";
  345. pinctrl-0 = <&pinctrl_uart2>;
  346. status = "okay";
  347. };
  348. &usbotg1 {
  349. dr_mode = "otg";
  350. hnp-disable;
  351. srp-disable;
  352. adp-disable;
  353. usb-role-switch;
  354. disable-over-current;
  355. samsung,picophy-pre-emp-curr-control = <3>;
  356. samsung,picophy-dc-vol-level-adjust = <7>;
  357. status = "okay";
  358. port {
  359. usb1_drd_sw: endpoint {
  360. remote-endpoint = <&typec1_dr_sw>;
  361. };
  362. };
  363. };
  364. &usdhc2 {
  365. assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
  366. assigned-clock-rates = <200000000>;
  367. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  368. pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  369. pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  370. pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  371. cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  372. bus-width = <4>;
  373. vmmc-supply = <&reg_usdhc2_vmmc>;
  374. status = "okay";
  375. };
  376. &wdog1 {
  377. pinctrl-names = "default";
  378. pinctrl-0 = <&pinctrl_wdog>;
  379. fsl,ext-reset-output;
  380. status = "okay";
  381. };
  382. &pwm1 {
  383. pinctrl-names = "default";
  384. pinctrl-0 = <&pinctrl_backlight>;
  385. status = "okay";
  386. };
  387. &iomuxc {
  388. pinctrl_fec1: fec1grp {
  389. fsl,pins = <
  390. MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
  391. MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
  392. MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
  393. MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
  394. MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
  395. MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
  396. MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
  397. MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
  398. MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
  399. MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
  400. MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
  401. MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
  402. MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
  403. MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
  404. MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
  405. >;
  406. };
  407. pinctrl_gpio_led: gpioledgrp {
  408. fsl,pins = <
  409. MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
  410. >;
  411. };
  412. pinctrl_ir: irgrp {
  413. fsl,pins = <
  414. MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
  415. >;
  416. };
  417. pinctrl_gpio_wlf: gpiowlfgrp {
  418. fsl,pins = <
  419. MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
  420. >;
  421. };
  422. pinctrl_i2c1: i2c1grp {
  423. fsl,pins = <
  424. MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
  425. MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
  426. >;
  427. };
  428. pinctrl_i2c2: i2c2grp {
  429. fsl,pins = <
  430. MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
  431. MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
  432. >;
  433. };
  434. pinctrl_i2c3: i2c3grp {
  435. fsl,pins = <
  436. MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
  437. MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
  438. >;
  439. };
  440. pinctrl_pcie0: pcie0grp {
  441. fsl,pins = <
  442. MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
  443. MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
  444. >;
  445. };
  446. pinctrl_pcie0_reg: pcie0reggrp {
  447. fsl,pins = <
  448. MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
  449. >;
  450. };
  451. pinctrl_pmic: pmicirqgrp {
  452. fsl,pins = <
  453. MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
  454. >;
  455. };
  456. pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
  457. fsl,pins = <
  458. MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
  459. >;
  460. };
  461. pinctrl_sai2: sai2grp {
  462. fsl,pins = <
  463. MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
  464. MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
  465. MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
  466. MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
  467. >;
  468. };
  469. pinctrl_sai3: sai3grp {
  470. fsl,pins = <
  471. MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
  472. MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
  473. MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
  474. MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
  475. >;
  476. };
  477. pinctrl_typec1: typec1grp {
  478. fsl,pins = <
  479. MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
  480. >;
  481. };
  482. pinctrl_uart2: uart2grp {
  483. fsl,pins = <
  484. MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
  485. MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
  486. >;
  487. };
  488. pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
  489. fsl,pins = <
  490. MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
  491. >;
  492. };
  493. pinctrl_usdhc2: usdhc2grp {
  494. fsl,pins = <
  495. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
  496. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
  497. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
  498. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
  499. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
  500. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
  501. MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  502. >;
  503. };
  504. pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
  505. fsl,pins = <
  506. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
  507. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
  508. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
  509. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
  510. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
  511. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
  512. MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  513. >;
  514. };
  515. pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
  516. fsl,pins = <
  517. MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
  518. MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
  519. MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
  520. MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
  521. MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
  522. MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
  523. MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  524. >;
  525. };
  526. pinctrl_wdog: wdoggrp {
  527. fsl,pins = <
  528. MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
  529. >;
  530. };
  531. pinctrl_backlight: backlightgrp {
  532. fsl,pins = <
  533. MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
  534. >;
  535. };
  536. };