imx8mm-beacon-som.dtsi 11 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright 2020 Compass Electronics Group, LLC
  4. */
  5. / {
  6. aliases {
  7. rtc0 = &rtc;
  8. rtc1 = &snvs_rtc;
  9. };
  10. usdhc1_pwrseq: usdhc1_pwrseq {
  11. compatible = "mmc-pwrseq-simple";
  12. pinctrl-names = "default";
  13. pinctrl-0 = <&pinctrl_usdhc1_gpio>;
  14. reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  15. clocks = <&osc_32k>;
  16. clock-names = "ext_clock";
  17. post-power-on-delay-ms = <80>;
  18. };
  19. memory@40000000 {
  20. device_type = "memory";
  21. reg = <0x0 0x40000000 0 0x80000000>;
  22. };
  23. };
  24. &A53_0 {
  25. cpu-supply = <&buck2_reg>;
  26. };
  27. &A53_1 {
  28. cpu-supply = <&buck2_reg>;
  29. };
  30. &A53_2 {
  31. cpu-supply = <&buck2_reg>;
  32. };
  33. &A53_3 {
  34. cpu-supply = <&buck2_reg>;
  35. };
  36. &ddrc {
  37. operating-points-v2 = <&ddrc_opp_table>;
  38. ddrc_opp_table: opp-table {
  39. compatible = "operating-points-v2";
  40. opp-25M {
  41. opp-hz = /bits/ 64 <25000000>;
  42. };
  43. opp-100M {
  44. opp-hz = /bits/ 64 <100000000>;
  45. };
  46. opp-750M {
  47. opp-hz = /bits/ 64 <750000000>;
  48. };
  49. };
  50. };
  51. &fec1 {
  52. pinctrl-names = "default";
  53. pinctrl-0 = <&pinctrl_fec1>;
  54. phy-mode = "rgmii-id";
  55. phy-handle = <&ethphy0>;
  56. fsl,magic-packet;
  57. status = "okay";
  58. mdio {
  59. #address-cells = <1>;
  60. #size-cells = <0>;
  61. ethphy0: ethernet-phy@0 {
  62. compatible = "ethernet-phy-ieee802.3-c22";
  63. reg = <0>;
  64. };
  65. };
  66. };
  67. &flexspi {
  68. pinctrl-names = "default";
  69. pinctrl-0 = <&pinctrl_flexspi>;
  70. status = "okay";
  71. flash@0 {
  72. reg = <0>;
  73. #address-cells = <1>;
  74. #size-cells = <1>;
  75. compatible = "jedec,spi-nor";
  76. spi-max-frequency = <80000000>;
  77. spi-tx-bus-width = <1>;
  78. spi-rx-bus-width = <4>;
  79. };
  80. };
  81. &i2c1 {
  82. clock-frequency = <400000>;
  83. pinctrl-names = "default";
  84. pinctrl-0 = <&pinctrl_i2c1>;
  85. status = "okay";
  86. pmic@4b {
  87. compatible = "rohm,bd71847";
  88. reg = <0x4b>;
  89. pinctrl-names = "default";
  90. pinctrl-0 = <&pinctrl_pmic>;
  91. interrupt-parent = <&gpio1>;
  92. interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
  93. rohm,reset-snvs-powered;
  94. #clock-cells = <0>;
  95. clocks = <&osc_32k 0>;
  96. clock-output-names = "clk-32k-out";
  97. regulators {
  98. buck1_reg: BUCK1 {
  99. regulator-name = "buck1";
  100. regulator-min-microvolt = <700000>;
  101. regulator-max-microvolt = <1300000>;
  102. regulator-boot-on;
  103. regulator-always-on;
  104. regulator-ramp-delay = <1250>;
  105. };
  106. buck2_reg: BUCK2 {
  107. regulator-name = "buck2";
  108. regulator-min-microvolt = <700000>;
  109. regulator-max-microvolt = <1300000>;
  110. regulator-boot-on;
  111. regulator-always-on;
  112. regulator-ramp-delay = <1250>;
  113. rohm,dvs-run-voltage = <1000000>;
  114. rohm,dvs-idle-voltage = <900000>;
  115. };
  116. buck3_reg: BUCK3 {
  117. // BUCK5 in datasheet
  118. regulator-name = "buck3";
  119. regulator-min-microvolt = <700000>;
  120. regulator-max-microvolt = <1350000>;
  121. regulator-boot-on;
  122. regulator-always-on;
  123. };
  124. buck4_reg: BUCK4 {
  125. // BUCK6 in datasheet
  126. regulator-name = "buck4";
  127. regulator-min-microvolt = <3000000>;
  128. regulator-max-microvolt = <3300000>;
  129. regulator-boot-on;
  130. regulator-always-on;
  131. };
  132. buck5_reg: BUCK5 {
  133. // BUCK7 in datasheet
  134. regulator-name = "buck5";
  135. regulator-min-microvolt = <1605000>;
  136. regulator-max-microvolt = <1995000>;
  137. regulator-boot-on;
  138. regulator-always-on;
  139. };
  140. buck6_reg: BUCK6 {
  141. // BUCK8 in datasheet
  142. regulator-name = "buck6";
  143. regulator-min-microvolt = <800000>;
  144. regulator-max-microvolt = <1400000>;
  145. regulator-boot-on;
  146. regulator-always-on;
  147. };
  148. ldo1_reg: LDO1 {
  149. regulator-name = "ldo1";
  150. regulator-min-microvolt = <1600000>;
  151. regulator-max-microvolt = <3300000>;
  152. regulator-boot-on;
  153. regulator-always-on;
  154. };
  155. ldo2_reg: LDO2 {
  156. regulator-name = "ldo2";
  157. regulator-min-microvolt = <800000>;
  158. regulator-max-microvolt = <900000>;
  159. regulator-boot-on;
  160. regulator-always-on;
  161. };
  162. ldo3_reg: LDO3 {
  163. regulator-name = "ldo3";
  164. regulator-min-microvolt = <1800000>;
  165. regulator-max-microvolt = <3300000>;
  166. regulator-boot-on;
  167. regulator-always-on;
  168. };
  169. ldo4_reg: LDO4 {
  170. regulator-name = "ldo4";
  171. regulator-min-microvolt = <900000>;
  172. regulator-max-microvolt = <1800000>;
  173. regulator-boot-on;
  174. regulator-always-on;
  175. };
  176. ldo6_reg: LDO6 {
  177. regulator-name = "ldo6";
  178. regulator-min-microvolt = <900000>;
  179. regulator-max-microvolt = <1800000>;
  180. regulator-boot-on;
  181. regulator-always-on;
  182. };
  183. };
  184. };
  185. };
  186. &i2c3 {
  187. clock-frequency = <400000>;
  188. pinctrl-names = "default";
  189. pinctrl-0 = <&pinctrl_i2c3>;
  190. status = "okay";
  191. eeprom@50 {
  192. compatible = "microchip,24c64", "atmel,24c64";
  193. pagesize = <32>;
  194. read-only; /* Manufacturing EEPROM programmed at factory */
  195. reg = <0x50>;
  196. };
  197. rtc: rtc@51 {
  198. compatible = "nxp,pcf85263";
  199. reg = <0x51>;
  200. };
  201. };
  202. &uart1 {
  203. pinctrl-names = "default";
  204. pinctrl-0 = <&pinctrl_uart1>;
  205. assigned-clocks = <&clk IMX8MM_CLK_UART1>;
  206. assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
  207. uart-has-rtscts;
  208. status = "okay";
  209. bluetooth {
  210. compatible = "brcm,bcm43438-bt";
  211. shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
  212. host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
  213. device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
  214. clocks = <&osc_32k>;
  215. max-speed = <4000000>;
  216. clock-names = "extclk";
  217. };
  218. };
  219. &usdhc1 {
  220. #address-cells = <1>;
  221. #size-cells = <0>;
  222. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  223. pinctrl-0 = <&pinctrl_usdhc1>;
  224. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  225. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  226. bus-width = <4>;
  227. non-removable;
  228. cap-power-off-card;
  229. keep-power-in-suspend;
  230. mmc-pwrseq = <&usdhc1_pwrseq>;
  231. status = "okay";
  232. brcmf: bcrmf@1 {
  233. reg = <1>;
  234. compatible = "brcm,bcm4329-fmac";
  235. pinctrl-names = "default";
  236. pinctrl-0 = <&pinctrl_wlan>;
  237. interrupt-parent = <&gpio2>;
  238. interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
  239. interrupt-names = "host-wake";
  240. };
  241. };
  242. &usdhc3 {
  243. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  244. pinctrl-0 = <&pinctrl_usdhc3>;
  245. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  246. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  247. bus-width = <8>;
  248. non-removable;
  249. status = "okay";
  250. };
  251. &wdog1 {
  252. pinctrl-names = "default";
  253. pinctrl-0 = <&pinctrl_wdog>;
  254. fsl,ext-reset-output;
  255. status = "okay";
  256. };
  257. &iomuxc {
  258. pinctrl_fec1: fec1grp {
  259. fsl,pins = <
  260. MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
  261. MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
  262. MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
  263. MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
  264. MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
  265. MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
  266. MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
  267. MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
  268. MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
  269. MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
  270. MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
  271. MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
  272. MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
  273. MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
  274. MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
  275. >;
  276. };
  277. pinctrl_i2c1: i2c1grp {
  278. fsl,pins = <
  279. MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
  280. MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
  281. >;
  282. };
  283. pinctrl_i2c3: i2c3grp {
  284. fsl,pins = <
  285. MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
  286. MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
  287. >;
  288. };
  289. pinctrl_flexspi: flexspigrp {
  290. fsl,pins = <
  291. MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
  292. MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
  293. MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
  294. MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
  295. MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
  296. MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
  297. >;
  298. };
  299. pinctrl_pmic: pmicirqgrp {
  300. fsl,pins = <
  301. MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
  302. >;
  303. };
  304. pinctrl_uart1: uart1grp {
  305. fsl,pins = <
  306. MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
  307. MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
  308. MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
  309. MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
  310. MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
  311. MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
  312. MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
  313. MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
  314. >;
  315. };
  316. pinctrl_usdhc1_gpio: usdhc1gpiogrp {
  317. fsl,pins = <
  318. MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
  319. >;
  320. };
  321. pinctrl_usdhc1: usdhc1grp {
  322. fsl,pins = <
  323. MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
  324. MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
  325. MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
  326. MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
  327. MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
  328. MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
  329. >;
  330. };
  331. pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
  332. fsl,pins = <
  333. MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
  334. MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
  335. MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
  336. MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
  337. MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
  338. MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
  339. >;
  340. };
  341. pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
  342. fsl,pins = <
  343. MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
  344. MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
  345. MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
  346. MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
  347. MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
  348. MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
  349. >;
  350. };
  351. pinctrl_usdhc3: usdhc3grp {
  352. fsl,pins = <
  353. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
  354. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
  355. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
  356. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
  357. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
  358. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
  359. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
  360. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
  361. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
  362. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
  363. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
  364. >;
  365. };
  366. pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
  367. fsl,pins = <
  368. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
  369. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
  370. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
  371. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
  372. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
  373. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
  374. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
  375. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
  376. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
  377. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
  378. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
  379. >;
  380. };
  381. pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
  382. fsl,pins = <
  383. MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
  384. MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
  385. MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
  386. MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
  387. MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
  388. MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
  389. MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
  390. MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
  391. MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
  392. MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
  393. MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
  394. >;
  395. };
  396. pinctrl_wdog: wdoggrp {
  397. fsl,pins = <
  398. MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
  399. >;
  400. };
  401. pinctrl_wlan: wlangrp {
  402. fsl,pins = <
  403. MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
  404. >;
  405. };
  406. };