fsl-lx2160a-rdb.dts 3.9 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. //
  3. // Device Tree file for LX2160ARDB
  4. //
  5. // Copyright 2018-2020 NXP
  6. /dts-v1/;
  7. #include "fsl-lx2160a.dtsi"
  8. / {
  9. model = "NXP Layerscape LX2160ARDB";
  10. compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
  11. aliases {
  12. crypto = &crypto;
  13. mmc0 = &esdhc0;
  14. mmc1 = &esdhc1;
  15. serial0 = &uart0;
  16. };
  17. chosen {
  18. stdout-path = "serial0:115200n8";
  19. };
  20. sb_3v3: regulator-sb3v3 {
  21. compatible = "regulator-fixed";
  22. regulator-name = "MC34717-3.3VSB";
  23. regulator-min-microvolt = <3300000>;
  24. regulator-max-microvolt = <3300000>;
  25. regulator-boot-on;
  26. regulator-always-on;
  27. };
  28. };
  29. &crypto {
  30. status = "okay";
  31. };
  32. &dpmac3 {
  33. phy-handle = <&aquantia_phy1>;
  34. phy-connection-type = "usxgmii";
  35. managed = "in-band-status";
  36. };
  37. &dpmac4 {
  38. phy-handle = <&aquantia_phy2>;
  39. phy-connection-type = "usxgmii";
  40. managed = "in-band-status";
  41. };
  42. &dpmac5 {
  43. phy-handle = <&inphi_phy>;
  44. };
  45. &dpmac6 {
  46. phy-handle = <&inphi_phy>;
  47. };
  48. &dpmac17 {
  49. phy-handle = <&rgmii_phy1>;
  50. phy-connection-type = "rgmii-id";
  51. };
  52. &dpmac18 {
  53. phy-handle = <&rgmii_phy2>;
  54. phy-connection-type = "rgmii-id";
  55. };
  56. &emdio1 {
  57. status = "okay";
  58. rgmii_phy1: ethernet-phy@1 {
  59. /* AR8035 PHY */
  60. compatible = "ethernet-phy-id004d.d072";
  61. interrupts-extended = <&extirq 4 IRQ_TYPE_LEVEL_LOW>;
  62. reg = <0x1>;
  63. eee-broken-1000t;
  64. };
  65. rgmii_phy2: ethernet-phy@2 {
  66. /* AR8035 PHY */
  67. compatible = "ethernet-phy-id004d.d072";
  68. interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
  69. reg = <0x2>;
  70. eee-broken-1000t;
  71. };
  72. aquantia_phy1: ethernet-phy@4 {
  73. /* AQR107 PHY */
  74. compatible = "ethernet-phy-ieee802.3-c45";
  75. interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
  76. reg = <0x4>;
  77. };
  78. aquantia_phy2: ethernet-phy@5 {
  79. /* AQR107 PHY */
  80. compatible = "ethernet-phy-ieee802.3-c45";
  81. interrupts-extended = <&extirq 3 IRQ_TYPE_LEVEL_LOW>;
  82. reg = <0x5>;
  83. };
  84. };
  85. &can0 {
  86. status = "okay";
  87. can-transceiver {
  88. max-bitrate = <5000000>;
  89. };
  90. };
  91. &can1 {
  92. status = "okay";
  93. can-transceiver {
  94. max-bitrate = <5000000>;
  95. };
  96. };
  97. &emdio2 {
  98. status = "okay";
  99. inphi_phy: ethernet-phy@0 {
  100. compatible = "ethernet-phy-id0210.7440";
  101. reg = <0x0>;
  102. };
  103. };
  104. &esdhc0 {
  105. sd-uhs-sdr104;
  106. sd-uhs-sdr50;
  107. sd-uhs-sdr25;
  108. sd-uhs-sdr12;
  109. status = "okay";
  110. };
  111. &esdhc1 {
  112. mmc-hs200-1_8v;
  113. mmc-hs400-1_8v;
  114. bus-width = <8>;
  115. status = "okay";
  116. };
  117. &fspi {
  118. status = "okay";
  119. mt35xu512aba0: flash@0 {
  120. #address-cells = <1>;
  121. #size-cells = <1>;
  122. compatible = "jedec,spi-nor";
  123. m25p,fast-read;
  124. spi-max-frequency = <50000000>;
  125. reg = <0>;
  126. spi-rx-bus-width = <8>;
  127. spi-tx-bus-width = <8>;
  128. };
  129. mt35xu512aba1: flash@1 {
  130. #address-cells = <1>;
  131. #size-cells = <1>;
  132. compatible = "jedec,spi-nor";
  133. m25p,fast-read;
  134. spi-max-frequency = <50000000>;
  135. reg = <1>;
  136. spi-rx-bus-width = <8>;
  137. spi-tx-bus-width = <8>;
  138. };
  139. };
  140. &i2c0 {
  141. status = "okay";
  142. i2c-mux@77 {
  143. compatible = "nxp,pca9547";
  144. reg = <0x77>;
  145. #address-cells = <1>;
  146. #size-cells = <0>;
  147. i2c@2 {
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. reg = <0x2>;
  151. power-monitor@40 {
  152. compatible = "ti,ina220";
  153. reg = <0x40>;
  154. shunt-resistor = <500>;
  155. };
  156. };
  157. i2c@3 {
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. reg = <0x3>;
  161. temperature-sensor@4c {
  162. compatible = "nxp,sa56004";
  163. reg = <0x4c>;
  164. vcc-supply = <&sb_3v3>;
  165. };
  166. temperature-sensor@4d {
  167. compatible = "nxp,sa56004";
  168. reg = <0x4d>;
  169. vcc-supply = <&sb_3v3>;
  170. };
  171. };
  172. };
  173. };
  174. &i2c4 {
  175. status = "okay";
  176. rtc@51 {
  177. compatible = "nxp,pcf2129";
  178. reg = <0x51>;
  179. /* IRQ_RTC_B -> IRQ08, active low */
  180. interrupts-extended = <&extirq 8 IRQ_TYPE_LEVEL_LOW>;
  181. };
  182. };
  183. &optee {
  184. status = "okay";
  185. };
  186. &pcs_mdio3 {
  187. status = "okay";
  188. };
  189. &pcs_mdio4 {
  190. status = "okay";
  191. };
  192. &sata0 {
  193. status = "okay";
  194. };
  195. &sata1 {
  196. status = "okay";
  197. };
  198. &sata2 {
  199. status = "okay";
  200. };
  201. &sata3 {
  202. status = "okay";
  203. };
  204. &uart0 {
  205. status = "okay";
  206. };
  207. &uart1 {
  208. status = "okay";
  209. };
  210. &usb0 {
  211. status = "okay";
  212. };
  213. &usb1 {
  214. status = "okay";
  215. };