fsl-lx2160a-bluebox3.dts 11 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. //
  3. // Device Tree file for LX2160A BLUEBOX3
  4. //
  5. // Copyright 2020-2021 NXP
  6. /dts-v1/;
  7. #include "fsl-lx2160a.dtsi"
  8. / {
  9. model = "NXP Layerscape LX2160ABLUEBOX3";
  10. compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
  11. aliases {
  12. crypto = &crypto;
  13. mmc0 = &esdhc0;
  14. mmc1 = &esdhc1;
  15. serial0 = &uart0;
  16. };
  17. chosen {
  18. stdout-path = "serial0:115200n8";
  19. };
  20. sb_3v3: regulator-sb3v3 {
  21. compatible = "regulator-fixed";
  22. regulator-name = "MC34717-3.3VSB";
  23. regulator-min-microvolt = <3300000>;
  24. regulator-max-microvolt = <3300000>;
  25. regulator-boot-on;
  26. regulator-always-on;
  27. };
  28. };
  29. &can0 {
  30. status = "okay";
  31. can-transceiver {
  32. max-bitrate = <5000000>;
  33. };
  34. };
  35. &can1 {
  36. status = "okay";
  37. can-transceiver {
  38. max-bitrate = <5000000>;
  39. };
  40. };
  41. &crypto {
  42. status = "okay";
  43. };
  44. &dpmac5 {
  45. phy-handle = <&aqr113c_phy1>;
  46. phy-mode = "usxgmii";
  47. managed = "in-band-status";
  48. };
  49. &dpmac6 {
  50. phy-handle = <&aqr113c_phy2>;
  51. phy-mode = "usxgmii";
  52. managed = "in-band-status";
  53. };
  54. &dpmac9 {
  55. phy-handle = <&aqr113c_phy3>;
  56. phy-mode = "usxgmii";
  57. managed = "in-band-status";
  58. };
  59. &dpmac10 {
  60. phy-handle = <&aqr113c_phy4>;
  61. phy-mode = "usxgmii";
  62. managed = "in-band-status";
  63. };
  64. &dpmac17 {
  65. phy-mode = "rgmii";
  66. status = "okay";
  67. fixed-link {
  68. speed = <1000>;
  69. full-duplex;
  70. };
  71. };
  72. &dpmac18 {
  73. phy-mode = "rgmii";
  74. status = "okay";
  75. fixed-link {
  76. speed = <1000>;
  77. full-duplex;
  78. };
  79. };
  80. &emdio1 {
  81. status = "okay";
  82. aqr113c_phy2: ethernet-phy@0 {
  83. compatible = "ethernet-phy-ieee802.3-c45";
  84. reg = <0x0>;
  85. /* IRQ_10G_PHY2 */
  86. interrupts-extended = <&extirq 3 IRQ_TYPE_LEVEL_LOW>;
  87. };
  88. aqr113c_phy1: ethernet-phy@8 {
  89. compatible = "ethernet-phy-ieee802.3-c45";
  90. reg = <0x8>;
  91. /* IRQ_10G_PHY1 */
  92. interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
  93. };
  94. sw1_mii3_phy: ethernet-phy@5 {
  95. /* AR8035 */
  96. compatible = "ethernet-phy-id004d.d072";
  97. reg = <0x5>;
  98. interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>;
  99. };
  100. sw2_mii3_phy: ethernet-phy@6 {
  101. /* AR8035 */
  102. compatible = "ethernet-phy-id004d.d072";
  103. reg = <0x6>;
  104. interrupts-extended = <&extirq 7 IRQ_TYPE_LEVEL_LOW>;
  105. };
  106. };
  107. &emdio2 {
  108. status = "okay";
  109. aqr113c_phy4: ethernet-phy@0 {
  110. compatible = "ethernet-phy-ieee802.3-c45";
  111. reg = <0x0>;
  112. /* IRQ_10G_PHY4 */
  113. interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
  114. };
  115. aqr113c_phy3: ethernet-phy@8 {
  116. compatible = "ethernet-phy-ieee802.3-c45";
  117. reg = <0x8>;
  118. /* IRQ_10G_PHY3 */
  119. interrupts-extended = <&extirq 4 IRQ_TYPE_LEVEL_LOW>;
  120. };
  121. };
  122. &esdhc0 {
  123. sd-uhs-sdr104;
  124. sd-uhs-sdr50;
  125. sd-uhs-sdr25;
  126. sd-uhs-sdr12;
  127. status = "okay";
  128. };
  129. &esdhc1 {
  130. mmc-hs200-1_8v;
  131. mmc-hs400-1_8v;
  132. bus-width = <8>;
  133. status = "okay";
  134. };
  135. &fspi {
  136. status = "okay";
  137. mt35xu512aba0: flash@0 {
  138. compatible = "jedec,spi-nor";
  139. #address-cells = <1>;
  140. #size-cells = <1>;
  141. reg = <0>;
  142. m25p,fast-read;
  143. spi-max-frequency = <50000000>;
  144. spi-rx-bus-width = <8>;
  145. spi-tx-bus-width = <8>;
  146. };
  147. mt35xu512aba1: flash@1 {
  148. compatible = "jedec,spi-nor";
  149. #address-cells = <1>;
  150. #size-cells = <1>;
  151. reg = <1>;
  152. m25p,fast-read;
  153. spi-max-frequency = <50000000>;
  154. spi-rx-bus-width = <8>;
  155. spi-tx-bus-width = <8>;
  156. };
  157. };
  158. &i2c0 {
  159. status = "okay";
  160. i2c-mux@77 {
  161. compatible = "nxp,pca9547";
  162. reg = <0x77>;
  163. #address-cells = <1>;
  164. #size-cells = <0>;
  165. i2c@2 {
  166. #address-cells = <1>;
  167. #size-cells = <0>;
  168. reg = <0x2>;
  169. power-monitor@40 {
  170. compatible = "ti,ina220";
  171. reg = <0x40>;
  172. shunt-resistor = <500>;
  173. };
  174. };
  175. i2c@3 {
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. reg = <0x3>;
  179. temp2: temperature-sensor@48 {
  180. compatible = "nxp,sa56004";
  181. reg = <0x48>;
  182. vcc-supply = <&sb_3v3>;
  183. #thermal-sensor-cells = <1>;
  184. };
  185. temp1: temperature-sensor@4c {
  186. compatible = "nxp,sa56004";
  187. reg = <0x4c>;
  188. vcc-supply = <&sb_3v3>;
  189. #thermal-sensor-cells = <1>;
  190. };
  191. };
  192. i2c@4 {
  193. #address-cells = <1>;
  194. #size-cells = <0>;
  195. reg = <0x4>;
  196. rtc@51 {
  197. compatible = "nxp,pcf2129";
  198. reg = <0x51>;
  199. interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>;
  200. };
  201. };
  202. i2c@7 {
  203. #address-cells = <1>;
  204. #size-cells = <0>;
  205. reg = <0x7>;
  206. i2c-mux@75 {
  207. compatible = "nxp,pca9547";
  208. reg = <0x75>;
  209. #address-cells = <1>;
  210. #size-cells = <0>;
  211. i2c@0 {
  212. #address-cells = <1>;
  213. #size-cells = <0>;
  214. reg = <0x0>;
  215. spi_bridge: spi@28 {
  216. compatible = "nxp,sc18is602b";
  217. reg = <0x28>;
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. };
  221. };
  222. };
  223. };
  224. };
  225. };
  226. &i2c5 {
  227. status = "okay";
  228. i2c-mux@77 {
  229. compatible = "nxp,pca9846";
  230. reg = <0x77>;
  231. #address-cells = <1>;
  232. #size-cells = <0>;
  233. i2c@1 {
  234. #address-cells = <1>;
  235. #size-cells = <0>;
  236. reg = <0x1>;
  237. /* The I2C multiplexer and temperature sensors are on
  238. * the T6 riser card.
  239. */
  240. i2c-mux@70 {
  241. compatible = "nxp,pca9548";
  242. reg = <0x70>;
  243. #address-cells = <1>;
  244. #size-cells = <0>;
  245. i2c@6 {
  246. #address-cells = <1>;
  247. #size-cells = <0>;
  248. reg = <0x6>;
  249. q12: temperature-sensor@4c {
  250. compatible = "nxp,sa56004";
  251. reg = <0x4c>;
  252. vcc-supply = <&sb_3v3>;
  253. #thermal-sensor-cells = <1>;
  254. };
  255. };
  256. i2c@7 {
  257. #address-cells = <1>;
  258. #size-cells = <0>;
  259. reg = <0x7>;
  260. q11: temperature-sensor@4c {
  261. compatible = "nxp,sa56004";
  262. reg = <0x4c>;
  263. vcc-supply = <&sb_3v3>;
  264. #thermal-sensor-cells = <1>;
  265. };
  266. q13: temperature-sensor@48 {
  267. compatible = "nxp,sa56004";
  268. reg = <0x48>;
  269. vcc-supply = <&sb_3v3>;
  270. #thermal-sensor-cells = <1>;
  271. };
  272. q14: temperature-sensor@4a {
  273. compatible = "nxp,sa56004";
  274. reg = <0x4a>;
  275. vcc-supply = <&sb_3v3>;
  276. #thermal-sensor-cells = <1>;
  277. };
  278. };
  279. };
  280. };
  281. };
  282. };
  283. &pcs_mdio5 {
  284. status = "okay";
  285. };
  286. &pcs_mdio6 {
  287. status = "okay";
  288. };
  289. &pcs_mdio9 {
  290. status = "okay";
  291. };
  292. &pcs_mdio10 {
  293. status = "okay";
  294. };
  295. &spi_bridge {
  296. sw1: ethernet-switch@0 {
  297. compatible = "nxp,sja1110a";
  298. reg = <0>;
  299. spi-max-frequency = <4000000>;
  300. spi-cpol;
  301. dsa,member = <0 0>;
  302. ethernet-ports {
  303. #address-cells = <1>;
  304. #size-cells = <0>;
  305. /* Microcontroller port */
  306. port@0 {
  307. reg = <0>;
  308. status = "disabled";
  309. };
  310. /* SW1_P1 */
  311. port@1 {
  312. reg = <1>;
  313. label = "con_2x20";
  314. phy-mode = "sgmii";
  315. fixed-link {
  316. speed = <1000>;
  317. full-duplex;
  318. };
  319. };
  320. port@2 {
  321. reg = <2>;
  322. ethernet = <&dpmac17>;
  323. phy-mode = "rgmii-id";
  324. rx-internal-delay-ps = <2000>;
  325. tx-internal-delay-ps = <2000>;
  326. fixed-link {
  327. speed = <1000>;
  328. full-duplex;
  329. };
  330. };
  331. port@3 {
  332. reg = <3>;
  333. label = "1ge_p1";
  334. phy-mode = "rgmii-id";
  335. phy-handle = <&sw1_mii3_phy>;
  336. };
  337. sw1p4: port@4 {
  338. reg = <4>;
  339. link = <&sw2p1>;
  340. phy-mode = "sgmii";
  341. fixed-link {
  342. speed = <1000>;
  343. full-duplex;
  344. };
  345. };
  346. port@5 {
  347. reg = <5>;
  348. label = "trx1";
  349. phy-mode = "internal";
  350. phy-handle = <&sw1_port5_base_t1_phy>;
  351. };
  352. port@6 {
  353. reg = <6>;
  354. label = "trx2";
  355. phy-mode = "internal";
  356. phy-handle = <&sw1_port6_base_t1_phy>;
  357. };
  358. port@7 {
  359. reg = <7>;
  360. label = "trx3";
  361. phy-mode = "internal";
  362. phy-handle = <&sw1_port7_base_t1_phy>;
  363. };
  364. port@8 {
  365. reg = <8>;
  366. label = "trx4";
  367. phy-mode = "internal";
  368. phy-handle = <&sw1_port8_base_t1_phy>;
  369. };
  370. port@9 {
  371. reg = <9>;
  372. label = "trx5";
  373. phy-mode = "internal";
  374. phy-handle = <&sw1_port9_base_t1_phy>;
  375. };
  376. port@a {
  377. reg = <10>;
  378. label = "trx6";
  379. phy-mode = "internal";
  380. phy-handle = <&sw1_port10_base_t1_phy>;
  381. };
  382. };
  383. mdios {
  384. #address-cells = <1>;
  385. #size-cells = <0>;
  386. mdio@0 {
  387. compatible = "nxp,sja1110-base-t1-mdio";
  388. #address-cells = <1>;
  389. #size-cells = <0>;
  390. reg = <0>;
  391. sw1_port5_base_t1_phy: ethernet-phy@1 {
  392. compatible = "ethernet-phy-ieee802.3-c45";
  393. reg = <0x1>;
  394. };
  395. sw1_port6_base_t1_phy: ethernet-phy@2 {
  396. compatible = "ethernet-phy-ieee802.3-c45";
  397. reg = <0x2>;
  398. };
  399. sw1_port7_base_t1_phy: ethernet-phy@3 {
  400. compatible = "ethernet-phy-ieee802.3-c45";
  401. reg = <0x3>;
  402. };
  403. sw1_port8_base_t1_phy: ethernet-phy@4 {
  404. compatible = "ethernet-phy-ieee802.3-c45";
  405. reg = <0x4>;
  406. };
  407. sw1_port9_base_t1_phy: ethernet-phy@5 {
  408. compatible = "ethernet-phy-ieee802.3-c45";
  409. reg = <0x5>;
  410. };
  411. sw1_port10_base_t1_phy: ethernet-phy@6 {
  412. compatible = "ethernet-phy-ieee802.3-c45";
  413. reg = <0x6>;
  414. };
  415. };
  416. };
  417. };
  418. sw2: ethernet-switch@2 {
  419. compatible = "nxp,sja1110a";
  420. reg = <2>;
  421. spi-max-frequency = <4000000>;
  422. spi-cpol;
  423. dsa,member = <0 1>;
  424. ethernet-ports {
  425. #address-cells = <1>;
  426. #size-cells = <0>;
  427. /* Microcontroller port */
  428. port@0 {
  429. reg = <0>;
  430. status = "disabled";
  431. };
  432. sw2p1: port@1 {
  433. reg = <1>;
  434. link = <&sw1p4>;
  435. phy-mode = "sgmii";
  436. fixed-link {
  437. speed = <1000>;
  438. full-duplex;
  439. };
  440. };
  441. port@2 {
  442. reg = <2>;
  443. ethernet = <&dpmac18>;
  444. phy-mode = "rgmii-id";
  445. rx-internal-delay-ps = <2000>;
  446. tx-internal-delay-ps = <2000>;
  447. fixed-link {
  448. speed = <1000>;
  449. full-duplex;
  450. };
  451. };
  452. port@3 {
  453. reg = <3>;
  454. label = "1ge_p2";
  455. phy-mode = "rgmii-id";
  456. phy-handle = <&sw2_mii3_phy>;
  457. };
  458. port@4 {
  459. reg = <4>;
  460. label = "to_sw3";
  461. phy-mode = "2500base-x";
  462. fixed-link {
  463. speed = <2500>;
  464. full-duplex;
  465. };
  466. };
  467. port@5 {
  468. reg = <5>;
  469. label = "trx7";
  470. phy-mode = "internal";
  471. phy-handle = <&sw2_port5_base_t1_phy>;
  472. };
  473. port@6 {
  474. reg = <6>;
  475. label = "trx8";
  476. phy-mode = "internal";
  477. phy-handle = <&sw2_port6_base_t1_phy>;
  478. };
  479. port@7 {
  480. reg = <7>;
  481. label = "trx9";
  482. phy-mode = "internal";
  483. phy-handle = <&sw2_port7_base_t1_phy>;
  484. };
  485. port@8 {
  486. reg = <8>;
  487. label = "trx10";
  488. phy-mode = "internal";
  489. phy-handle = <&sw2_port8_base_t1_phy>;
  490. };
  491. port@9 {
  492. reg = <9>;
  493. label = "trx11";
  494. phy-mode = "internal";
  495. phy-handle = <&sw2_port9_base_t1_phy>;
  496. };
  497. port@a {
  498. reg = <10>;
  499. label = "trx12";
  500. phy-mode = "internal";
  501. phy-handle = <&sw2_port10_base_t1_phy>;
  502. };
  503. };
  504. mdios {
  505. #address-cells = <1>;
  506. #size-cells = <0>;
  507. mdio@0 {
  508. compatible = "nxp,sja1110-base-t1-mdio";
  509. #address-cells = <1>;
  510. #size-cells = <0>;
  511. reg = <0>;
  512. sw2_port5_base_t1_phy: ethernet-phy@1 {
  513. compatible = "ethernet-phy-ieee802.3-c45";
  514. reg = <0x1>;
  515. };
  516. sw2_port6_base_t1_phy: ethernet-phy@2 {
  517. compatible = "ethernet-phy-ieee802.3-c45";
  518. reg = <0x2>;
  519. };
  520. sw2_port7_base_t1_phy: ethernet-phy@3 {
  521. compatible = "ethernet-phy-ieee802.3-c45";
  522. reg = <0x3>;
  523. };
  524. sw2_port8_base_t1_phy: ethernet-phy@4 {
  525. compatible = "ethernet-phy-ieee802.3-c45";
  526. reg = <0x4>;
  527. };
  528. sw2_port9_base_t1_phy: ethernet-phy@5 {
  529. compatible = "ethernet-phy-ieee802.3-c45";
  530. reg = <0x5>;
  531. };
  532. sw2_port10_base_t1_phy: ethernet-phy@6 {
  533. compatible = "ethernet-phy-ieee802.3-c45";
  534. reg = <0x6>;
  535. };
  536. };
  537. };
  538. };
  539. };
  540. &uart0 {
  541. status = "okay";
  542. };
  543. &uart1 {
  544. status = "okay";
  545. };
  546. &usb0 {
  547. status = "okay";
  548. };
  549. &usb1 {
  550. status = "okay";
  551. };