android_kernel_samsung_sm8650_ksu/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NXP LS1088A RDB Board.
 *
 * Copyright 2017-2020 NXP
 *
 * Harninder Rai <[email protected]>
 *
 */

/dts-v1/;

#include "fsl-ls1088a.dtsi"

/ {
	model = "LS1088A RDB Board";
	compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
};

&dpmac2 {
	phy-handle = <&mdio2_aquantia_phy>;
	phy-connection-type = "10gbase-r";
	pcs-handle = <&pcs2>;
};

&dpmac3 {
	phy-handle = <&mdio1_phy5>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_0>;
};

&dpmac4 {
	phy-handle = <&mdio1_phy6>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_1>;
};

&dpmac5 {
	phy-handle = <&mdio1_phy7>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_2>;
};

&dpmac6 {
	phy-handle = <&mdio1_phy8>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_3>;
};

&dpmac7 {
	phy-handle = <&mdio1_phy1>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_0>;
};

&dpmac8 {
	phy-handle = <&mdio1_phy2>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_1>;
};

&dpmac9 {
	phy-handle = <&mdio1_phy3>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_2>;
};

&dpmac10 {
	phy-handle = <&mdio1_phy4>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_3>;
};

&emdio1 {
	status = "okay";

	mdio1_phy5: ethernet-phy@c {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0xc>;
	};

	mdio1_phy6: ethernet-phy@d {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0xd>;
	};

	mdio1_phy7: ethernet-phy@e {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0xe>;
	};

	mdio1_phy8: ethernet-phy@f {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0xf>;
	};

	mdio1_phy1: ethernet-phy@1c {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x1c>;
	};

	mdio1_phy2: ethernet-phy@1d {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x1d>;
	};

	mdio1_phy3: ethernet-phy@1e {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x1e>;
	};

	mdio1_phy4: ethernet-phy@1f {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x1f>;
	};
};

&emdio2 {
	status = "okay";

	mdio2_aquantia_phy: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c45";
		interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x0>;
	};
};

&i2c0 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			temp-sensor@4c {
				compatible = "adi,adt7461a";
				reg = <0x4c>;
			};

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
				/* IRQ_RTC_B -> IRQ0_B(CPLD) -> IRQ00(CPU), active low */
				interrupts-extended = <&extirq 0 IRQ_TYPE_LEVEL_LOW>;
			};
		};
	};
};

&ifc {
	ranges = <0 0 0x5 0x30000000 0x00010000
		  2 0 0x5 0x20000000 0x00010000>;
	status = "okay";

	nand@0,0 {
		compatible = "fsl,ifc-nand";
		reg = <0x0 0x0 0x10000>;
	};

	fpga: board-control@2,0 {
		compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
		reg = <0x2 0x0 0x0000100>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&esdhc {
	mmc-hs200-1_8v;
	status = "okay";
};

&pcs_mdio2 {
	status = "okay";
};

&pcs_mdio3 {
	status = "okay";
};

&pcs_mdio7 {
	status = "okay";
};

&qspi {
	status = "okay";

	s25fs512s0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <0>;
	};

	s25fs512s1: flash@1 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <1>;
	};
};

&sata {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	dr_mode = "otg";
	status = "okay";
};