fsl-ls1046a-rdb.dts 2.9 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree Include file for Freescale Layerscape-1046A family SoC.
  4. *
  5. * Copyright 2016 Freescale Semiconductor, Inc.
  6. * Copyright 2019-2020 NXP
  7. *
  8. * Mingkai Hu <[email protected]>
  9. */
  10. /dts-v1/;
  11. #include "fsl-ls1046a.dtsi"
  12. / {
  13. model = "LS1046A RDB Board";
  14. compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
  15. aliases {
  16. serial0 = &duart0;
  17. serial1 = &duart1;
  18. serial2 = &duart2;
  19. serial3 = &duart3;
  20. };
  21. chosen {
  22. stdout-path = "serial0:115200n8";
  23. };
  24. };
  25. &duart0 {
  26. status = "okay";
  27. };
  28. &duart1 {
  29. status = "okay";
  30. };
  31. &esdhc {
  32. mmc-hs200-1_8v;
  33. sd-uhs-sdr104;
  34. sd-uhs-sdr50;
  35. sd-uhs-sdr25;
  36. sd-uhs-sdr12;
  37. };
  38. &i2c0 {
  39. status = "okay";
  40. ina220@40 {
  41. compatible = "ti,ina220";
  42. reg = <0x40>;
  43. shunt-resistor = <1000>;
  44. };
  45. temp-sensor@4c {
  46. compatible = "adi,adt7461";
  47. reg = <0x4c>;
  48. };
  49. eeprom@52 {
  50. compatible = "onnn,cat24c05", "atmel,24c04";
  51. reg = <0x52>;
  52. };
  53. };
  54. &i2c3 {
  55. status = "okay";
  56. rtc@51 {
  57. compatible = "nxp,pcf2129";
  58. reg = <0x51>;
  59. /* IRQ_RTC_B -> IRQ05, active low */
  60. interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
  61. };
  62. };
  63. &ifc {
  64. #address-cells = <2>;
  65. #size-cells = <1>;
  66. /* NAND Flashe and CPLD on board */
  67. ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
  68. 0x2 0x0 0x0 0x7fb00000 0x00000100>;
  69. status = "okay";
  70. nand@0,0 {
  71. compatible = "fsl,ifc-nand";
  72. #address-cells = <1>;
  73. #size-cells = <1>;
  74. reg = <0x0 0x0 0x10000>;
  75. };
  76. cpld: board-control@2,0 {
  77. compatible = "fsl,ls1046ardb-cpld";
  78. reg = <0x2 0x0 0x0000100>;
  79. };
  80. };
  81. &qspi {
  82. status = "okay";
  83. s25fs512s0: flash@0 {
  84. compatible = "jedec,spi-nor";
  85. #address-cells = <1>;
  86. #size-cells = <1>;
  87. spi-max-frequency = <50000000>;
  88. spi-rx-bus-width = <4>;
  89. spi-tx-bus-width = <1>;
  90. reg = <0>;
  91. };
  92. s25fs512s1: flash@1 {
  93. compatible = "jedec,spi-nor";
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. spi-max-frequency = <50000000>;
  97. spi-rx-bus-width = <4>;
  98. spi-tx-bus-width = <1>;
  99. reg = <1>;
  100. };
  101. };
  102. &usb1 {
  103. dr_mode = "otg";
  104. };
  105. #include "fsl-ls1046-post.dtsi"
  106. &fman0 {
  107. ethernet@e4000 {
  108. phy-handle = <&rgmii_phy1>;
  109. phy-connection-type = "rgmii-id";
  110. };
  111. ethernet@e6000 {
  112. phy-handle = <&rgmii_phy2>;
  113. phy-connection-type = "rgmii-id";
  114. };
  115. ethernet@e8000 {
  116. phy-handle = <&sgmii_phy1>;
  117. phy-connection-type = "sgmii";
  118. };
  119. ethernet@ea000 {
  120. phy-handle = <&sgmii_phy2>;
  121. phy-connection-type = "sgmii";
  122. };
  123. ethernet@f0000 { /* 10GEC1 */
  124. phy-handle = <&aqr106_phy>;
  125. phy-connection-type = "xgmii";
  126. };
  127. ethernet@f2000 { /* 10GEC2 */
  128. fixed-link = <0 1 1000 0 0>;
  129. phy-connection-type = "xgmii";
  130. };
  131. mdio@fc000 {
  132. rgmii_phy1: ethernet-phy@1 {
  133. reg = <0x1>;
  134. };
  135. rgmii_phy2: ethernet-phy@2 {
  136. reg = <0x2>;
  137. };
  138. sgmii_phy1: ethernet-phy@3 {
  139. reg = <0x3>;
  140. };
  141. sgmii_phy2: ethernet-phy@4 {
  142. reg = <0x4>;
  143. };
  144. };
  145. mdio@fd000 {
  146. aqr106_phy: ethernet-phy@0 {
  147. compatible = "ethernet-phy-ieee802.3-c45";
  148. interrupts = <0 131 4>;
  149. reg = <0x0>;
  150. };
  151. };
  152. };