fsl-ls1028a-qds.dts 6.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree file for NXP LS1028A QDS Board.
  4. *
  5. * Copyright 2018 NXP
  6. *
  7. * Harninder Rai <[email protected]>
  8. *
  9. */
  10. /dts-v1/;
  11. #include "fsl-ls1028a.dtsi"
  12. / {
  13. model = "LS1028A QDS Board";
  14. compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
  15. aliases {
  16. crypto = &crypto;
  17. gpio0 = &gpio1;
  18. gpio1 = &gpio2;
  19. gpio2 = &gpio3;
  20. serial0 = &duart0;
  21. serial1 = &duart1;
  22. mmc0 = &esdhc;
  23. mmc1 = &esdhc1;
  24. rtc1 = &ftm_alarm1;
  25. };
  26. chosen {
  27. stdout-path = "serial0:115200n8";
  28. };
  29. memory@80000000 {
  30. device_type = "memory";
  31. reg = <0x0 0x80000000 0x1 0x00000000>;
  32. };
  33. sys_mclk: clock-mclk {
  34. compatible = "fixed-clock";
  35. #clock-cells = <0>;
  36. clock-frequency = <25000000>;
  37. };
  38. reg_1p8v: regulator-1p8v {
  39. compatible = "regulator-fixed";
  40. regulator-name = "1P8V";
  41. regulator-min-microvolt = <1800000>;
  42. regulator-max-microvolt = <1800000>;
  43. regulator-always-on;
  44. };
  45. sb_3v3: regulator-sb3v3 {
  46. compatible = "regulator-fixed";
  47. regulator-name = "3v3_vbus";
  48. regulator-min-microvolt = <3300000>;
  49. regulator-max-microvolt = <3300000>;
  50. regulator-boot-on;
  51. regulator-always-on;
  52. };
  53. sound {
  54. compatible = "simple-audio-card";
  55. simple-audio-card,format = "i2s";
  56. simple-audio-card,widgets =
  57. "Microphone", "Microphone Jack",
  58. "Headphone", "Headphone Jack",
  59. "Speaker", "Speaker Ext",
  60. "Line", "Line In Jack";
  61. simple-audio-card,routing =
  62. "MIC_IN", "Microphone Jack",
  63. "Microphone Jack", "Mic Bias",
  64. "LINE_IN", "Line In Jack",
  65. "Headphone Jack", "HP_OUT",
  66. "Speaker Ext", "LINE_OUT";
  67. simple-audio-card,cpu {
  68. sound-dai = <&sai1>;
  69. frame-master;
  70. bitclock-master;
  71. };
  72. simple-audio-card,codec {
  73. sound-dai = <&sgtl5000>;
  74. frame-master;
  75. bitclock-master;
  76. system-clock-frequency = <25000000>;
  77. };
  78. };
  79. mdio-mux {
  80. compatible = "mdio-mux-multiplexer";
  81. mux-controls = <&mux 0>;
  82. mdio-parent-bus = <&enetc_mdio_pf3>;
  83. #address-cells = <1>;
  84. #size-cells = <0>;
  85. /* on-board RGMII PHY */
  86. mdio@0 {
  87. #address-cells = <1>;
  88. #size-cells = <0>;
  89. reg = <0>;
  90. qds_phy1: ethernet-phy@5 {
  91. /* Atheros 8035 */
  92. reg = <5>;
  93. };
  94. };
  95. mdio_slot1: mdio@4 {
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. reg = <4>;
  99. };
  100. mdio_slot2: mdio@5 {
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. reg = <5>;
  104. };
  105. mdio_slot3: mdio@6 {
  106. #address-cells = <1>;
  107. #size-cells = <0>;
  108. reg = <6>;
  109. };
  110. mdio_slot4: mdio@7 {
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. reg = <7>;
  114. };
  115. };
  116. };
  117. &can0 {
  118. status = "okay";
  119. };
  120. &can1 {
  121. status = "okay";
  122. };
  123. &dspi0 {
  124. bus-num = <0>;
  125. status = "okay";
  126. flash@0 {
  127. #address-cells = <1>;
  128. #size-cells = <1>;
  129. compatible = "jedec,spi-nor";
  130. spi-cpol;
  131. spi-cpha;
  132. reg = <0>;
  133. spi-max-frequency = <10000000>;
  134. };
  135. flash@1 {
  136. #address-cells = <1>;
  137. #size-cells = <1>;
  138. compatible = "jedec,spi-nor";
  139. spi-cpol;
  140. spi-cpha;
  141. reg = <1>;
  142. spi-max-frequency = <10000000>;
  143. };
  144. flash@2 {
  145. #address-cells = <1>;
  146. #size-cells = <1>;
  147. compatible = "jedec,spi-nor";
  148. spi-cpol;
  149. spi-cpha;
  150. reg = <2>;
  151. spi-max-frequency = <10000000>;
  152. };
  153. };
  154. &dspi1 {
  155. bus-num = <1>;
  156. status = "okay";
  157. flash@0 {
  158. #address-cells = <1>;
  159. #size-cells = <1>;
  160. compatible = "jedec,spi-nor";
  161. spi-cpol;
  162. spi-cpha;
  163. reg = <0>;
  164. spi-max-frequency = <10000000>;
  165. };
  166. flash@1 {
  167. #address-cells = <1>;
  168. #size-cells = <1>;
  169. compatible = "jedec,spi-nor";
  170. spi-cpol;
  171. spi-cpha;
  172. reg = <1>;
  173. spi-max-frequency = <10000000>;
  174. };
  175. flash@2 {
  176. #address-cells = <1>;
  177. #size-cells = <1>;
  178. compatible = "jedec,spi-nor";
  179. spi-cpol;
  180. spi-cpha;
  181. reg = <2>;
  182. spi-max-frequency = <10000000>;
  183. };
  184. };
  185. &dspi2 {
  186. bus-num = <2>;
  187. status = "okay";
  188. flash@0 {
  189. #address-cells = <1>;
  190. #size-cells = <1>;
  191. compatible = "jedec,spi-nor";
  192. spi-cpol;
  193. spi-cpha;
  194. reg = <0>;
  195. spi-max-frequency = <10000000>;
  196. };
  197. };
  198. &duart0 {
  199. status = "okay";
  200. };
  201. &duart1 {
  202. status = "okay";
  203. };
  204. &enetc_port1 {
  205. phy-handle = <&qds_phy1>;
  206. phy-mode = "rgmii-id";
  207. status = "okay";
  208. };
  209. &enetc_port2 {
  210. status = "okay";
  211. };
  212. &esdhc {
  213. status = "okay";
  214. };
  215. &esdhc1 {
  216. status = "okay";
  217. };
  218. &fspi {
  219. status = "okay";
  220. mt35xu02g0: flash@0 {
  221. compatible = "jedec,spi-nor";
  222. #address-cells = <1>;
  223. #size-cells = <1>;
  224. spi-max-frequency = <50000000>;
  225. /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
  226. spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
  227. spi-tx-bus-width = <1>; /* 1 SPI Tx line */
  228. reg = <0>;
  229. };
  230. };
  231. &ftm_alarm1 {
  232. status = "okay";
  233. };
  234. &i2c0 {
  235. status = "okay";
  236. i2c-mux@77 {
  237. compatible = "nxp,pca9547";
  238. reg = <0x77>;
  239. #address-cells = <1>;
  240. #size-cells = <0>;
  241. i2c@2 {
  242. #address-cells = <1>;
  243. #size-cells = <0>;
  244. reg = <0x2>;
  245. current-monitor@40 {
  246. compatible = "ti,ina220";
  247. reg = <0x40>;
  248. shunt-resistor = <1000>;
  249. };
  250. current-monitor@41 {
  251. compatible = "ti,ina220";
  252. reg = <0x41>;
  253. shunt-resistor = <1000>;
  254. };
  255. };
  256. i2c@3 {
  257. #address-cells = <1>;
  258. #size-cells = <0>;
  259. reg = <0x3>;
  260. temperature-sensor@4c {
  261. compatible = "nxp,sa56004";
  262. reg = <0x4c>;
  263. vcc-supply = <&sb_3v3>;
  264. };
  265. eeprom@56 {
  266. compatible = "atmel,24c512";
  267. reg = <0x56>;
  268. };
  269. eeprom@57 {
  270. compatible = "atmel,24c512";
  271. reg = <0x57>;
  272. };
  273. };
  274. i2c@5 {
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. reg = <0x5>;
  278. sgtl5000: audio-codec@a {
  279. #sound-dai-cells = <0>;
  280. compatible = "fsl,sgtl5000";
  281. reg = <0xa>;
  282. VDDA-supply = <&reg_1p8v>;
  283. VDDIO-supply = <&reg_1p8v>;
  284. clocks = <&sys_mclk>;
  285. };
  286. };
  287. };
  288. fpga@66 {
  289. compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
  290. "simple-mfd";
  291. reg = <0x66>;
  292. mux: mux-controller {
  293. compatible = "reg-mux";
  294. #mux-control-cells = <1>;
  295. mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
  296. };
  297. };
  298. };
  299. &i2c1 {
  300. status = "okay";
  301. rtc@51 {
  302. compatible = "nxp,pcf2129";
  303. reg = <0x51>;
  304. };
  305. };
  306. &lpuart0 {
  307. status = "okay";
  308. };
  309. &lpuart1 {
  310. status = "okay";
  311. };
  312. &mscc_felix_port4 {
  313. ethernet = <&enetc_port2>;
  314. status = "okay";
  315. };
  316. &sai1 {
  317. status = "okay";
  318. };
  319. &sata {
  320. status = "okay";
  321. };
  322. &usb0 {
  323. dr_mode = "host";
  324. status = "okay";
  325. };
  326. &usb1 {
  327. dr_mode = "host";
  328. status = "okay";
  329. };