fsl-ls1028a-qds-7777.dts 1.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree fragment for LS1028A QDS board, serdes 7777
  4. *
  5. * Copyright 2019-2021 NXP
  6. *
  7. * Requires a LS1028A QDS board without lane B rework.
  8. * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
  9. * disabled, plugged in slot 1.
  10. */
  11. /dts-v1/;
  12. /plugin/;
  13. &mdio_slot1 {
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. /* 4 ports on AQR412 */
  17. slot1_sxgmii0: ethernet-phy@0 {
  18. reg = <0x0>;
  19. compatible = "ethernet-phy-ieee802.3-c45";
  20. };
  21. slot1_sxgmii1: ethernet-phy@1 {
  22. reg = <0x1>;
  23. compatible = "ethernet-phy-ieee802.3-c45";
  24. };
  25. slot1_sxgmii2: ethernet-phy@2 {
  26. reg = <0x2>;
  27. compatible = "ethernet-phy-ieee802.3-c45";
  28. };
  29. slot1_sxgmii3: ethernet-phy@3 {
  30. reg = <0x3>;
  31. compatible = "ethernet-phy-ieee802.3-c45";
  32. };
  33. };
  34. &mscc_felix_ports {
  35. port@0 {
  36. status = "okay";
  37. phy-handle = <&slot1_sxgmii0>;
  38. phy-mode = "2500base-x";
  39. };
  40. port@1 {
  41. status = "okay";
  42. phy-handle = <&slot1_sxgmii1>;
  43. phy-mode = "2500base-x";
  44. };
  45. port@2 {
  46. status = "okay";
  47. phy-handle = <&slot1_sxgmii2>;
  48. phy-mode = "2500base-x";
  49. };
  50. port@3 {
  51. status = "okay";
  52. phy-handle = <&slot1_sxgmii3>;
  53. phy-mode = "2500base-x";
  54. };
  55. };
  56. &mscc_felix {
  57. status = "okay";
  58. };