exynosautov9-sadk.dts 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Samsung ExynosAutov9 SADK board device tree source
  4. *
  5. * Copyright (c) 2021 Samsung Electronics Co., Ltd.
  6. *
  7. */
  8. /dts-v1/;
  9. #include "exynosautov9.dtsi"
  10. #include <dt-bindings/gpio/gpio.h>
  11. / {
  12. model = "Samsung ExynosAuto v9 SADK board";
  13. compatible = "samsung,exynosautov9-sadk", "samsung,exynosautov9";
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. aliases {
  17. serial0 = &serial_0;
  18. };
  19. chosen {
  20. stdout-path = &serial_0;
  21. };
  22. memory@80000000 {
  23. device_type = "memory";
  24. reg = <0x0 0x80000000 0x0 0x77000000>,
  25. <0x8 0x80000000 0x1 0x7ba00000>,
  26. <0xa 0x00000000 0x2 0x00000000>;
  27. };
  28. ufs_0_fixed_vcc_reg: regulator-0 {
  29. compatible = "regulator-fixed";
  30. regulator-name = "ufs-vcc";
  31. gpio = <&gpq0 1 GPIO_ACTIVE_HIGH>;
  32. regulator-boot-on;
  33. enable-active-high;
  34. };
  35. ufs_1_fixed_vcc_reg: regulator-1 {
  36. compatible = "regulator-fixed";
  37. regulator-name = "ufs-vcc";
  38. gpio = <&gpg2 2 GPIO_ACTIVE_HIGH>;
  39. regulator-boot-on;
  40. enable-active-high;
  41. };
  42. };
  43. &serial_0 {
  44. pinctrl-0 = <&uart0_bus_dual>;
  45. status = "okay";
  46. };
  47. &ufs_0_phy {
  48. status = "okay";
  49. };
  50. &ufs_1_phy {
  51. status = "okay";
  52. };
  53. &ufs_0 {
  54. status = "okay";
  55. vcc-supply = <&ufs_0_fixed_vcc_reg>;
  56. vcc-fixed-regulator;
  57. };
  58. &ufs_1 {
  59. status = "okay";
  60. vcc-supply = <&ufs_1_fixed_vcc_reg>;
  61. vcc-fixed-regulator;
  62. };
  63. &usi_0 {
  64. samsung,clkreq-on; /* needed for UART mode */
  65. status = "okay";
  66. };
  67. &xtcxo {
  68. clock-frequency = <26000000>;
  69. };