t8103-pmgr.dtsi 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR MIT
  2. /*
  3. * PMGR Power domains for the Apple T8103 "M1" SoC
  4. *
  5. * Copyright The Asahi Linux Contributors
  6. */
  7. &pmgr {
  8. ps_sbr: power-controller@100 {
  9. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  10. reg = <0x100 4>;
  11. #power-domain-cells = <0>;
  12. #reset-cells = <0>;
  13. label = "sbr";
  14. apple,always-on; /* Core device */
  15. };
  16. ps_aic: power-controller@108 {
  17. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  18. reg = <0x108 4>;
  19. #power-domain-cells = <0>;
  20. #reset-cells = <0>;
  21. label = "aic";
  22. apple,always-on; /* Core device */
  23. };
  24. ps_dwi: power-controller@110 {
  25. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  26. reg = <0x110 4>;
  27. #power-domain-cells = <0>;
  28. #reset-cells = <0>;
  29. label = "dwi";
  30. apple,always-on; /* Core device */
  31. };
  32. ps_soc_spmi0: power-controller@118 {
  33. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  34. reg = <0x118 4>;
  35. #power-domain-cells = <0>;
  36. #reset-cells = <0>;
  37. label = "soc_spmi0";
  38. };
  39. ps_soc_spmi1: power-controller@120 {
  40. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  41. reg = <0x120 4>;
  42. #power-domain-cells = <0>;
  43. #reset-cells = <0>;
  44. label = "soc_spmi1";
  45. };
  46. ps_soc_spmi2: power-controller@128 {
  47. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  48. reg = <0x128 4>;
  49. #power-domain-cells = <0>;
  50. #reset-cells = <0>;
  51. label = "soc_spmi2";
  52. };
  53. ps_gpio: power-controller@130 {
  54. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  55. reg = <0x130 4>;
  56. #power-domain-cells = <0>;
  57. #reset-cells = <0>;
  58. label = "gpio";
  59. };
  60. ps_pms_busif: power-controller@138 {
  61. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  62. reg = <0x138 4>;
  63. #power-domain-cells = <0>;
  64. #reset-cells = <0>;
  65. label = "pms_busif";
  66. apple,always-on; /* Core device */
  67. };
  68. ps_pms: power-controller@140 {
  69. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  70. reg = <0x140 4>;
  71. #power-domain-cells = <0>;
  72. #reset-cells = <0>;
  73. label = "pms";
  74. apple,always-on; /* Core device */
  75. };
  76. ps_pms_fpwm0: power-controller@148 {
  77. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  78. reg = <0x148 4>;
  79. #power-domain-cells = <0>;
  80. #reset-cells = <0>;
  81. label = "pms_fpwm0";
  82. power-domains = <&ps_pms>;
  83. };
  84. ps_pms_fpwm1: power-controller@150 {
  85. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  86. reg = <0x150 4>;
  87. #power-domain-cells = <0>;
  88. #reset-cells = <0>;
  89. label = "pms_fpwm1";
  90. power-domains = <&ps_pms>;
  91. };
  92. ps_pms_fpwm2: power-controller@158 {
  93. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  94. reg = <0x158 4>;
  95. #power-domain-cells = <0>;
  96. #reset-cells = <0>;
  97. label = "pms_fpwm2";
  98. power-domains = <&ps_pms>;
  99. };
  100. ps_pms_fpwm3: power-controller@160 {
  101. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  102. reg = <0x160 4>;
  103. #power-domain-cells = <0>;
  104. #reset-cells = <0>;
  105. label = "pms_fpwm3";
  106. power-domains = <&ps_pms>;
  107. };
  108. ps_pms_fpwm4: power-controller@168 {
  109. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  110. reg = <0x168 4>;
  111. #power-domain-cells = <0>;
  112. #reset-cells = <0>;
  113. label = "pms_fpwm4";
  114. power-domains = <&ps_pms>;
  115. };
  116. ps_soc_dpe: power-controller@170 {
  117. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  118. reg = <0x170 4>;
  119. #power-domain-cells = <0>;
  120. #reset-cells = <0>;
  121. label = "soc_dpe";
  122. apple,always-on; /* Core device */
  123. };
  124. ps_pmgr_soc_ocla: power-controller@178 {
  125. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  126. reg = <0x178 4>;
  127. #power-domain-cells = <0>;
  128. #reset-cells = <0>;
  129. label = "pmgr_soc_ocla";
  130. };
  131. ps_ispsens0: power-controller@180 {
  132. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  133. reg = <0x180 4>;
  134. #power-domain-cells = <0>;
  135. #reset-cells = <0>;
  136. label = "ispsens0";
  137. };
  138. ps_ispsens1: power-controller@188 {
  139. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  140. reg = <0x188 4>;
  141. #power-domain-cells = <0>;
  142. #reset-cells = <0>;
  143. label = "ispsens1";
  144. };
  145. ps_ispsens2: power-controller@190 {
  146. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  147. reg = <0x190 4>;
  148. #power-domain-cells = <0>;
  149. #reset-cells = <0>;
  150. label = "ispsens2";
  151. };
  152. ps_ispsens3: power-controller@198 {
  153. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  154. reg = <0x198 4>;
  155. #power-domain-cells = <0>;
  156. #reset-cells = <0>;
  157. label = "ispsens3";
  158. };
  159. ps_pcie_ref: power-controller@1a0 {
  160. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  161. reg = <0x1a0 4>;
  162. #power-domain-cells = <0>;
  163. #reset-cells = <0>;
  164. label = "pcie_ref";
  165. };
  166. ps_aft0: power-controller@1a8 {
  167. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  168. reg = <0x1a8 4>;
  169. #power-domain-cells = <0>;
  170. #reset-cells = <0>;
  171. label = "aft0";
  172. };
  173. ps_devc0_ivdmc: power-controller@1b0 {
  174. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  175. reg = <0x1b0 4>;
  176. #power-domain-cells = <0>;
  177. #reset-cells = <0>;
  178. label = "devc0_ivdmc";
  179. };
  180. ps_imx: power-controller@1b8 {
  181. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  182. reg = <0x1b8 4>;
  183. #power-domain-cells = <0>;
  184. #reset-cells = <0>;
  185. label = "imx";
  186. apple,always-on; /* Apple fabric, critical block */
  187. };
  188. ps_sio_busif: power-controller@1c0 {
  189. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  190. reg = <0x1c0 4>;
  191. #power-domain-cells = <0>;
  192. #reset-cells = <0>;
  193. label = "sio_busif";
  194. };
  195. ps_sio: power-controller@1c8 {
  196. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  197. reg = <0x1c8 4>;
  198. #power-domain-cells = <0>;
  199. #reset-cells = <0>;
  200. label = "sio";
  201. power-domains = <&ps_sio_busif>;
  202. };
  203. ps_sio_cpu: power-controller@1d0 {
  204. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  205. reg = <0x1d0 4>;
  206. #power-domain-cells = <0>;
  207. #reset-cells = <0>;
  208. label = "sio_cpu";
  209. power-domains = <&ps_sio>;
  210. };
  211. ps_fpwm0: power-controller@1d8 {
  212. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  213. reg = <0x1d8 4>;
  214. #power-domain-cells = <0>;
  215. #reset-cells = <0>;
  216. label = "fpwm0";
  217. };
  218. ps_fpwm1: power-controller@1e0 {
  219. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  220. reg = <0x1e0 4>;
  221. #power-domain-cells = <0>;
  222. #reset-cells = <0>;
  223. label = "fpwm1";
  224. };
  225. ps_fpwm2: power-controller@1e8 {
  226. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  227. reg = <0x1e8 4>;
  228. #power-domain-cells = <0>;
  229. #reset-cells = <0>;
  230. label = "fpwm2";
  231. };
  232. ps_i2c0: power-controller@1f0 {
  233. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  234. reg = <0x1f0 4>;
  235. #power-domain-cells = <0>;
  236. #reset-cells = <0>;
  237. label = "i2c0";
  238. power-domains = <&ps_sio>;
  239. };
  240. ps_i2c1: power-controller@1f8 {
  241. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  242. reg = <0x1f8 4>;
  243. #power-domain-cells = <0>;
  244. #reset-cells = <0>;
  245. label = "i2c1";
  246. power-domains = <&ps_sio>;
  247. };
  248. ps_i2c2: power-controller@200 {
  249. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  250. reg = <0x200 4>;
  251. #power-domain-cells = <0>;
  252. #reset-cells = <0>;
  253. label = "i2c2";
  254. power-domains = <&ps_sio>;
  255. };
  256. ps_i2c3: power-controller@208 {
  257. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  258. reg = <0x208 4>;
  259. #power-domain-cells = <0>;
  260. #reset-cells = <0>;
  261. label = "i2c3";
  262. power-domains = <&ps_sio>;
  263. };
  264. ps_i2c4: power-controller@210 {
  265. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  266. reg = <0x210 4>;
  267. #power-domain-cells = <0>;
  268. #reset-cells = <0>;
  269. label = "i2c4";
  270. power-domains = <&ps_sio>;
  271. };
  272. ps_spi_p: power-controller@218 {
  273. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  274. reg = <0x218 4>;
  275. #power-domain-cells = <0>;
  276. #reset-cells = <0>;
  277. label = "spi_p";
  278. power-domains = <&ps_sio>;
  279. };
  280. ps_uart_p: power-controller@220 {
  281. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  282. reg = <0x220 4>;
  283. #power-domain-cells = <0>;
  284. #reset-cells = <0>;
  285. label = "uart_p";
  286. power-domains = <&ps_sio>;
  287. };
  288. ps_audio_p: power-controller@228 {
  289. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  290. reg = <0x228 4>;
  291. #power-domain-cells = <0>;
  292. #reset-cells = <0>;
  293. label = "audio_p";
  294. power-domains = <&ps_sio>;
  295. };
  296. ps_sio_adma: power-controller@230 {
  297. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  298. reg = <0x230 4>;
  299. #power-domain-cells = <0>;
  300. #reset-cells = <0>;
  301. label = "sio_adma";
  302. power-domains = <&ps_sio>, <&ps_pms>;
  303. };
  304. ps_aes: power-controller@238 {
  305. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  306. reg = <0x238 4>;
  307. #power-domain-cells = <0>;
  308. #reset-cells = <0>;
  309. label = "aes";
  310. power-domains = <&ps_sio>;
  311. };
  312. ps_spi0: power-controller@240 {
  313. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  314. reg = <0x240 4>;
  315. #power-domain-cells = <0>;
  316. #reset-cells = <0>;
  317. label = "spi0";
  318. power-domains = <&ps_sio>, <&ps_spi_p>;
  319. };
  320. ps_spi1: power-controller@248 {
  321. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  322. reg = <0x248 4>;
  323. #power-domain-cells = <0>;
  324. #reset-cells = <0>;
  325. label = "spi1";
  326. power-domains = <&ps_sio>, <&ps_spi_p>;
  327. };
  328. ps_spi2: power-controller@250 {
  329. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  330. reg = <0x250 4>;
  331. #power-domain-cells = <0>;
  332. #reset-cells = <0>;
  333. label = "spi2";
  334. power-domains = <&ps_sio>, <&ps_spi_p>;
  335. };
  336. ps_spi3: power-controller@258 {
  337. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  338. reg = <0x258 4>;
  339. #power-domain-cells = <0>;
  340. #reset-cells = <0>;
  341. label = "spi3";
  342. power-domains = <&ps_sio>, <&ps_spi_p>;
  343. };
  344. ps_uart_n: power-controller@268 {
  345. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  346. reg = <0x268 4>;
  347. #power-domain-cells = <0>;
  348. #reset-cells = <0>;
  349. label = "uart_n";
  350. power-domains = <&ps_uart_p>;
  351. };
  352. ps_uart0: power-controller@270 {
  353. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  354. reg = <0x270 4>;
  355. #power-domain-cells = <0>;
  356. #reset-cells = <0>;
  357. label = "uart0";
  358. power-domains = <&ps_uart_p>;
  359. };
  360. ps_uart1: power-controller@278 {
  361. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  362. reg = <0x278 4>;
  363. #power-domain-cells = <0>;
  364. #reset-cells = <0>;
  365. label = "uart1";
  366. power-domains = <&ps_uart_p>;
  367. };
  368. ps_uart2: power-controller@280 {
  369. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  370. reg = <0x280 4>;
  371. #power-domain-cells = <0>;
  372. #reset-cells = <0>;
  373. label = "uart2";
  374. power-domains = <&ps_uart_p>;
  375. };
  376. ps_uart3: power-controller@288 {
  377. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  378. reg = <0x288 4>;
  379. #power-domain-cells = <0>;
  380. #reset-cells = <0>;
  381. label = "uart3";
  382. power-domains = <&ps_uart_p>;
  383. };
  384. ps_uart4: power-controller@290 {
  385. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  386. reg = <0x290 4>;
  387. #power-domain-cells = <0>;
  388. #reset-cells = <0>;
  389. label = "uart4";
  390. power-domains = <&ps_uart_p>;
  391. };
  392. ps_uart5: power-controller@298 {
  393. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  394. reg = <0x298 4>;
  395. #power-domain-cells = <0>;
  396. #reset-cells = <0>;
  397. label = "uart5";
  398. power-domains = <&ps_uart_p>;
  399. };
  400. ps_uart6: power-controller@2a0 {
  401. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  402. reg = <0x2a0 4>;
  403. #power-domain-cells = <0>;
  404. #reset-cells = <0>;
  405. label = "uart6";
  406. power-domains = <&ps_uart_p>;
  407. };
  408. ps_uart7: power-controller@2a8 {
  409. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  410. reg = <0x2a8 4>;
  411. #power-domain-cells = <0>;
  412. #reset-cells = <0>;
  413. label = "uart7";
  414. power-domains = <&ps_uart_p>;
  415. };
  416. ps_uart8: power-controller@2b0 {
  417. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  418. reg = <0x2b0 4>;
  419. #power-domain-cells = <0>;
  420. #reset-cells = <0>;
  421. label = "uart8";
  422. power-domains = <&ps_uart_p>;
  423. };
  424. ps_mca0: power-controller@2b8 {
  425. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  426. reg = <0x2b8 4>;
  427. #power-domain-cells = <0>;
  428. #reset-cells = <0>;
  429. label = "mca0";
  430. power-domains = <&ps_audio_p>, <&ps_sio_adma>;
  431. };
  432. ps_mca1: power-controller@2c0 {
  433. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  434. reg = <0x2c0 4>;
  435. #power-domain-cells = <0>;
  436. #reset-cells = <0>;
  437. label = "mca1";
  438. power-domains = <&ps_audio_p>, <&ps_sio_adma>;
  439. };
  440. ps_mca2: power-controller@2c8 {
  441. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  442. reg = <0x2c8 4>;
  443. #power-domain-cells = <0>;
  444. #reset-cells = <0>;
  445. label = "mca2";
  446. power-domains = <&ps_audio_p>, <&ps_sio_adma>;
  447. };
  448. ps_mca3: power-controller@2d0 {
  449. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  450. reg = <0x2d0 4>;
  451. #power-domain-cells = <0>;
  452. #reset-cells = <0>;
  453. label = "mca3";
  454. power-domains = <&ps_audio_p>, <&ps_sio_adma>;
  455. };
  456. ps_mca4: power-controller@2d8 {
  457. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  458. reg = <0x2d8 4>;
  459. #power-domain-cells = <0>;
  460. #reset-cells = <0>;
  461. label = "mca4";
  462. power-domains = <&ps_audio_p>, <&ps_sio_adma>;
  463. };
  464. ps_mca5: power-controller@2e0 {
  465. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  466. reg = <0x2e0 4>;
  467. #power-domain-cells = <0>;
  468. #reset-cells = <0>;
  469. label = "mca5";
  470. power-domains = <&ps_audio_p>, <&ps_sio_adma>;
  471. };
  472. ps_dpa0: power-controller@2e8 {
  473. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  474. reg = <0x2e8 4>;
  475. #power-domain-cells = <0>;
  476. #reset-cells = <0>;
  477. label = "dpa0";
  478. power-domains = <&ps_audio_p>;
  479. };
  480. ps_dpa1: power-controller@2f0 {
  481. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  482. reg = <0x2f0 4>;
  483. #power-domain-cells = <0>;
  484. #reset-cells = <0>;
  485. label = "dpa1";
  486. power-domains = <&ps_audio_p>;
  487. };
  488. ps_mcc: power-controller@2f8 {
  489. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  490. reg = <0x2f8 4>;
  491. #power-domain-cells = <0>;
  492. #reset-cells = <0>;
  493. label = "mcc";
  494. apple,always-on; /* Memory controller */
  495. };
  496. ps_spi4: power-controller@260 {
  497. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  498. reg = <0x260 4>;
  499. #power-domain-cells = <0>;
  500. #reset-cells = <0>;
  501. label = "spi4";
  502. power-domains = <&ps_sio>, <&ps_spi_p>;
  503. };
  504. ps_dcs0: power-controller@300 {
  505. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  506. reg = <0x300 4>;
  507. #power-domain-cells = <0>;
  508. #reset-cells = <0>;
  509. label = "dcs0";
  510. apple,always-on; /* LPDDR4 interface */
  511. };
  512. ps_dcs1: power-controller@310 {
  513. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  514. reg = <0x310 4>;
  515. #power-domain-cells = <0>;
  516. #reset-cells = <0>;
  517. label = "dcs1";
  518. apple,always-on; /* LPDDR4 interface */
  519. };
  520. ps_dcs2: power-controller@308 {
  521. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  522. reg = <0x308 4>;
  523. #power-domain-cells = <0>;
  524. #reset-cells = <0>;
  525. label = "dcs2";
  526. apple,always-on; /* LPDDR4 interface */
  527. };
  528. ps_dcs3: power-controller@318 {
  529. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  530. reg = <0x318 4>;
  531. #power-domain-cells = <0>;
  532. #reset-cells = <0>;
  533. label = "dcs3";
  534. apple,always-on; /* LPDDR4 interface */
  535. };
  536. ps_smx: power-controller@340 {
  537. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  538. reg = <0x340 4>;
  539. #power-domain-cells = <0>;
  540. #reset-cells = <0>;
  541. label = "smx";
  542. apple,always-on; /* Apple fabric, critical block */
  543. };
  544. ps_apcie: power-controller@348 {
  545. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  546. reg = <0x348 4>;
  547. #power-domain-cells = <0>;
  548. #reset-cells = <0>;
  549. label = "apcie";
  550. power-domains = <&ps_imx>, <&ps_pcie_ref>;
  551. };
  552. ps_rmx: power-controller@350 {
  553. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  554. reg = <0x350 4>;
  555. #power-domain-cells = <0>;
  556. #reset-cells = <0>;
  557. label = "rmx";
  558. /* Apple Fabric, display/image stuff: this can power down */
  559. };
  560. ps_mmx: power-controller@358 {
  561. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  562. reg = <0x358 4>;
  563. #power-domain-cells = <0>;
  564. #reset-cells = <0>;
  565. label = "mmx";
  566. /* Apple Fabric, media stuff: this can power down */
  567. };
  568. ps_disp0_fe: power-controller@360 {
  569. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  570. reg = <0x360 4>;
  571. #power-domain-cells = <0>;
  572. #reset-cells = <0>;
  573. label = "disp0_fe";
  574. power-domains = <&ps_rmx>;
  575. apple,always-on; /* TODO: figure out if we can enable PM here */
  576. };
  577. ps_dispext_fe: power-controller@368 {
  578. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  579. reg = <0x368 4>;
  580. #power-domain-cells = <0>;
  581. #reset-cells = <0>;
  582. label = "dispext_fe";
  583. power-domains = <&ps_rmx>;
  584. };
  585. ps_dispext_cpu0: power-controller@378 {
  586. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  587. reg = <0x378 4>;
  588. #power-domain-cells = <0>;
  589. #reset-cells = <0>;
  590. label = "dispext_cpu0";
  591. power-domains = <&ps_dispext_fe>;
  592. apple,min-state = <4>;
  593. };
  594. ps_jpg: power-controller@3c0 {
  595. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  596. reg = <0x3c0 4>;
  597. #power-domain-cells = <0>;
  598. #reset-cells = <0>;
  599. label = "jpg";
  600. power-domains = <&ps_mmx>;
  601. };
  602. ps_msr: power-controller@3c8 {
  603. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  604. reg = <0x3c8 4>;
  605. #power-domain-cells = <0>;
  606. #reset-cells = <0>;
  607. label = "msr";
  608. power-domains = <&ps_mmx>;
  609. };
  610. ps_msr_ase_core: power-controller@3d0 {
  611. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  612. reg = <0x3d0 4>;
  613. #power-domain-cells = <0>;
  614. #reset-cells = <0>;
  615. label = "msr_ase_core";
  616. };
  617. ps_pmp: power-controller@3d8 {
  618. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  619. reg = <0x3d8 4>;
  620. #power-domain-cells = <0>;
  621. #reset-cells = <0>;
  622. label = "pmp";
  623. };
  624. ps_pms_sram: power-controller@3e0 {
  625. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  626. reg = <0x3e0 4>;
  627. #power-domain-cells = <0>;
  628. #reset-cells = <0>;
  629. label = "pms_sram";
  630. };
  631. ps_apcie_gp: power-controller@3e8 {
  632. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  633. reg = <0x3e8 4>;
  634. #power-domain-cells = <0>;
  635. #reset-cells = <0>;
  636. label = "apcie_gp";
  637. power-domains = <&ps_apcie>;
  638. };
  639. ps_ans2: power-controller@3f0 {
  640. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  641. reg = <0x3f0 4>;
  642. #power-domain-cells = <0>;
  643. #reset-cells = <0>;
  644. label = "ans2";
  645. };
  646. ps_gfx: power-controller@3f8 {
  647. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  648. reg = <0x3f8 4>;
  649. #power-domain-cells = <0>;
  650. #reset-cells = <0>;
  651. label = "gfx";
  652. };
  653. ps_dcs4: power-controller@320 {
  654. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  655. reg = <0x320 4>;
  656. #power-domain-cells = <0>;
  657. #reset-cells = <0>;
  658. label = "dcs4";
  659. apple,always-on; /* LPDDR4 interface */
  660. };
  661. ps_dcs5: power-controller@330 {
  662. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  663. reg = <0x330 4>;
  664. #power-domain-cells = <0>;
  665. #reset-cells = <0>;
  666. label = "dcs5";
  667. apple,always-on; /* LPDDR4 interface */
  668. };
  669. ps_dcs6: power-controller@328 {
  670. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  671. reg = <0x328 4>;
  672. #power-domain-cells = <0>;
  673. #reset-cells = <0>;
  674. label = "dcs6";
  675. apple,always-on; /* LPDDR4 interface */
  676. };
  677. ps_dcs7: power-controller@338 {
  678. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  679. reg = <0x338 4>;
  680. #power-domain-cells = <0>;
  681. #reset-cells = <0>;
  682. label = "dcs7";
  683. apple,always-on; /* LPDDR4 interface */
  684. };
  685. ps_dispdfr_fe: power-controller@3a8 {
  686. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  687. reg = <0x3a8 4>;
  688. #power-domain-cells = <0>;
  689. #reset-cells = <0>;
  690. label = "dispdfr_fe";
  691. power-domains = <&ps_rmx>;
  692. };
  693. ps_dispdfr_be: power-controller@3b0 {
  694. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  695. reg = <0x3b0 4>;
  696. #power-domain-cells = <0>;
  697. #reset-cells = <0>;
  698. label = "dispdfr_be";
  699. power-domains = <&ps_dispdfr_fe>;
  700. };
  701. ps_mipi_dsi: power-controller@3b8 {
  702. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  703. reg = <0x3b8 4>;
  704. #power-domain-cells = <0>;
  705. #reset-cells = <0>;
  706. label = "mipi_dsi";
  707. power-domains = <&ps_dispdfr_be>;
  708. };
  709. ps_isp_sys: power-controller@400 {
  710. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  711. reg = <0x400 4>;
  712. #power-domain-cells = <0>;
  713. #reset-cells = <0>;
  714. label = "isp_sys";
  715. power-domains = <&ps_rmx>;
  716. };
  717. ps_venc_sys: power-controller@408 {
  718. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  719. reg = <0x408 4>;
  720. #power-domain-cells = <0>;
  721. #reset-cells = <0>;
  722. label = "venc_sys";
  723. power-domains = <&ps_mmx>;
  724. };
  725. ps_avd_sys: power-controller@410 {
  726. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  727. reg = <0x410 4>;
  728. #power-domain-cells = <0>;
  729. #reset-cells = <0>;
  730. label = "avd_sys";
  731. power-domains = <&ps_mmx>;
  732. };
  733. ps_apcie_st: power-controller@418 {
  734. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  735. reg = <0x418 4>;
  736. #power-domain-cells = <0>;
  737. #reset-cells = <0>;
  738. label = "apcie_st";
  739. power-domains = <&ps_apcie>, <&ps_ans2>;
  740. };
  741. ps_ane_sys: power-controller@470 {
  742. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  743. reg = <0x470 4>;
  744. #power-domain-cells = <0>;
  745. #reset-cells = <0>;
  746. label = "ane_sys";
  747. };
  748. ps_atc0_common: power-controller@420 {
  749. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  750. reg = <0x420 4>;
  751. #power-domain-cells = <0>;
  752. #reset-cells = <0>;
  753. label = "atc0_common";
  754. };
  755. ps_atc0_pcie: power-controller@428 {
  756. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  757. reg = <0x428 4>;
  758. #power-domain-cells = <0>;
  759. #reset-cells = <0>;
  760. label = "atc0_pcie";
  761. power-domains = <&ps_atc0_common>;
  762. };
  763. ps_atc0_cio: power-controller@430 {
  764. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  765. reg = <0x430 4>;
  766. #power-domain-cells = <0>;
  767. #reset-cells = <0>;
  768. label = "atc0_cio";
  769. power-domains = <&ps_atc0_common>;
  770. };
  771. ps_atc0_cio_pcie: power-controller@438 {
  772. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  773. reg = <0x438 4>;
  774. #power-domain-cells = <0>;
  775. #reset-cells = <0>;
  776. label = "atc0_cio_pcie";
  777. power-domains = <&ps_atc0_cio>;
  778. };
  779. ps_atc0_cio_usb: power-controller@440 {
  780. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  781. reg = <0x440 4>;
  782. #power-domain-cells = <0>;
  783. #reset-cells = <0>;
  784. label = "atc0_cio_usb";
  785. power-domains = <&ps_atc0_cio>;
  786. };
  787. ps_atc1_common: power-controller@448 {
  788. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  789. reg = <0x448 4>;
  790. #power-domain-cells = <0>;
  791. #reset-cells = <0>;
  792. label = "atc1_common";
  793. };
  794. ps_atc1_pcie: power-controller@450 {
  795. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  796. reg = <0x450 4>;
  797. #power-domain-cells = <0>;
  798. #reset-cells = <0>;
  799. label = "atc1_pcie";
  800. power-domains = <&ps_atc1_common>;
  801. };
  802. ps_atc1_cio: power-controller@458 {
  803. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  804. reg = <0x458 4>;
  805. #power-domain-cells = <0>;
  806. #reset-cells = <0>;
  807. label = "atc1_cio";
  808. power-domains = <&ps_atc1_common>;
  809. };
  810. ps_atc1_cio_pcie: power-controller@460 {
  811. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  812. reg = <0x460 4>;
  813. #power-domain-cells = <0>;
  814. #reset-cells = <0>;
  815. label = "atc1_cio_pcie";
  816. power-domains = <&ps_atc1_cio>;
  817. };
  818. ps_atc1_cio_usb: power-controller@468 {
  819. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  820. reg = <0x468 4>;
  821. #power-domain-cells = <0>;
  822. #reset-cells = <0>;
  823. label = "atc1_cio_usb";
  824. power-domains = <&ps_atc1_cio>;
  825. };
  826. ps_sep: power-controller@c00 {
  827. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  828. reg = <0xc00 4>;
  829. #power-domain-cells = <0>;
  830. #reset-cells = <0>;
  831. label = "sep";
  832. apple,always-on; /* Locked on */
  833. };
  834. ps_venc_dma: power-controller@8000 {
  835. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  836. reg = <0x8000 4>;
  837. #power-domain-cells = <0>;
  838. #reset-cells = <0>;
  839. label = "venc_dma";
  840. power-domains = <&ps_venc_sys>;
  841. };
  842. ps_venc_pipe4: power-controller@8008 {
  843. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  844. reg = <0x8008 4>;
  845. #power-domain-cells = <0>;
  846. #reset-cells = <0>;
  847. label = "venc_pipe4";
  848. power-domains = <&ps_venc_dma>;
  849. };
  850. ps_venc_pipe5: power-controller@8010 {
  851. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  852. reg = <0x8010 4>;
  853. #power-domain-cells = <0>;
  854. #reset-cells = <0>;
  855. label = "venc_pipe5";
  856. power-domains = <&ps_venc_dma>;
  857. };
  858. ps_venc_me0: power-controller@8018 {
  859. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  860. reg = <0x8018 4>;
  861. #power-domain-cells = <0>;
  862. #reset-cells = <0>;
  863. label = "venc_me0";
  864. power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>;
  865. };
  866. ps_venc_me1: power-controller@8020 {
  867. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  868. reg = <0x8020 4>;
  869. #power-domain-cells = <0>;
  870. #reset-cells = <0>;
  871. label = "venc_me1";
  872. power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>;
  873. };
  874. ps_ane_sys_cpu: power-controller@c000 {
  875. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  876. reg = <0xc000 4>;
  877. #power-domain-cells = <0>;
  878. #reset-cells = <0>;
  879. label = "ane_sys_cpu";
  880. power-domains = <&ps_ane_sys>;
  881. };
  882. ps_disp0_cpu0: power-controller@10018 {
  883. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  884. reg = <0x10018 4>;
  885. #power-domain-cells = <0>;
  886. #reset-cells = <0>;
  887. label = "disp0_cpu0";
  888. power-domains = <&ps_disp0_fe>;
  889. apple,always-on; /* TODO: figure out if we can enable PM here */
  890. apple,min-state = <4>;
  891. };
  892. };
  893. &pmgr_mini {
  894. ps_debug: power-controller@58 {
  895. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  896. reg = <0x58 4>;
  897. #power-domain-cells = <0>;
  898. #reset-cells = <0>;
  899. label = "debug";
  900. apple,always-on; /* Core AON device */
  901. };
  902. ps_nub_spmi0: power-controller@60 {
  903. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  904. reg = <0x60 4>;
  905. #power-domain-cells = <0>;
  906. #reset-cells = <0>;
  907. label = "nub_spmi0";
  908. apple,always-on; /* Core AON device */
  909. };
  910. ps_nub_aon: power-controller@70 {
  911. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  912. reg = <0x70 4>;
  913. #power-domain-cells = <0>;
  914. #reset-cells = <0>;
  915. label = "nub_aon";
  916. apple,always-on; /* Core AON device */
  917. };
  918. ps_nub_gpio: power-controller@80 {
  919. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  920. reg = <0x80 4>;
  921. #power-domain-cells = <0>;
  922. #reset-cells = <0>;
  923. label = "nub_gpio";
  924. apple,always-on; /* Core AON device */
  925. };
  926. ps_nub_fabric: power-controller@a8 {
  927. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  928. reg = <0xa8 4>;
  929. #power-domain-cells = <0>;
  930. #reset-cells = <0>;
  931. label = "nub_fabric";
  932. apple,always-on; /* Core AON device */
  933. };
  934. ps_nub_sram: power-controller@b0 {
  935. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  936. reg = <0xb0 4>;
  937. #power-domain-cells = <0>;
  938. #reset-cells = <0>;
  939. label = "nub_sram";
  940. apple,always-on; /* Core AON device */
  941. };
  942. ps_debug_usb: power-controller@b8 {
  943. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  944. reg = <0xb8 4>;
  945. #power-domain-cells = <0>;
  946. #reset-cells = <0>;
  947. label = "debug_usb";
  948. apple,always-on; /* Core AON device */
  949. power-domains = <&ps_debug>;
  950. };
  951. ps_debug_auth: power-controller@c0 {
  952. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  953. reg = <0xc0 4>;
  954. #power-domain-cells = <0>;
  955. #reset-cells = <0>;
  956. label = "debug_auth";
  957. apple,always-on; /* Core AON device */
  958. power-domains = <&ps_debug>;
  959. };
  960. ps_nub_spmi1: power-controller@68 {
  961. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  962. reg = <0x68 4>;
  963. #power-domain-cells = <0>;
  964. #reset-cells = <0>;
  965. label = "nub_spmi1";
  966. apple,always-on; /* Core AON device */
  967. };
  968. ps_msg: power-controller@78 {
  969. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  970. reg = <0x78 4>;
  971. #power-domain-cells = <0>;
  972. #reset-cells = <0>;
  973. label = "msg";
  974. };
  975. ps_atc0_usb_aon: power-controller@88 {
  976. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  977. reg = <0x88 4>;
  978. #power-domain-cells = <0>;
  979. #reset-cells = <0>;
  980. label = "atc0_usb_aon";
  981. };
  982. ps_atc1_usb_aon: power-controller@90 {
  983. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  984. reg = <0x90 4>;
  985. #power-domain-cells = <0>;
  986. #reset-cells = <0>;
  987. label = "atc1_usb_aon";
  988. };
  989. ps_atc0_usb: power-controller@98 {
  990. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  991. reg = <0x98 4>;
  992. #power-domain-cells = <0>;
  993. #reset-cells = <0>;
  994. label = "atc0_usb";
  995. power-domains = <&ps_atc0_usb_aon>, <&ps_atc0_common>;
  996. };
  997. ps_atc1_usb: power-controller@a0 {
  998. compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
  999. reg = <0xa0 4>;
  1000. #power-domain-cells = <0>;
  1001. #reset-cells = <0>;
  1002. label = "atc1_usb";
  1003. power-domains = <&ps_atc1_usb_aon>, <&ps_atc1_common>;
  1004. };
  1005. };