meson-s4.dtsi 3.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
  4. */
  5. #include <dt-bindings/interrupt-controller/irq.h>
  6. #include <dt-bindings/interrupt-controller/arm-gic.h>
  7. #include <dt-bindings/gpio/gpio.h>
  8. / {
  9. cpus {
  10. #address-cells = <2>;
  11. #size-cells = <0>;
  12. cpu0: cpu@0 {
  13. device_type = "cpu";
  14. compatible = "arm,cortex-a35";
  15. reg = <0x0 0x0>;
  16. enable-method = "psci";
  17. };
  18. cpu1: cpu@1 {
  19. device_type = "cpu";
  20. compatible = "arm,cortex-a35";
  21. reg = <0x0 0x1>;
  22. enable-method = "psci";
  23. };
  24. cpu2: cpu@2 {
  25. device_type = "cpu";
  26. compatible = "arm,cortex-a35";
  27. reg = <0x0 0x2>;
  28. enable-method = "psci";
  29. };
  30. cpu3: cpu@3 {
  31. device_type = "cpu";
  32. compatible = "arm,cortex-a35";
  33. reg = <0x0 0x3>;
  34. enable-method = "psci";
  35. };
  36. };
  37. timer {
  38. compatible = "arm,armv8-timer";
  39. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  40. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  41. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  42. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  43. };
  44. psci {
  45. compatible = "arm,psci-1.0";
  46. method = "smc";
  47. };
  48. xtal: xtal-clk {
  49. compatible = "fixed-clock";
  50. clock-frequency = <24000000>;
  51. clock-output-names = "xtal";
  52. #clock-cells = <0>;
  53. };
  54. pwrc: power-controller {
  55. compatible = "amlogic,meson-s4-pwrc";
  56. #power-domain-cells = <1>;
  57. status = "okay";
  58. };
  59. soc {
  60. compatible = "simple-bus";
  61. #address-cells = <2>;
  62. #size-cells = <2>;
  63. ranges;
  64. gic: interrupt-controller@fff01000 {
  65. compatible = "arm,gic-400";
  66. #interrupt-cells = <3>;
  67. #address-cells = <0>;
  68. interrupt-controller;
  69. reg = <0x0 0xfff01000 0 0x1000>,
  70. <0x0 0xfff02000 0 0x2000>,
  71. <0x0 0xfff04000 0 0x2000>,
  72. <0x0 0xfff06000 0 0x2000>;
  73. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  74. };
  75. apb4: apb4@fe000000 {
  76. compatible = "simple-bus";
  77. reg = <0x0 0xfe000000 0x0 0x480000>;
  78. #address-cells = <2>;
  79. #size-cells = <2>;
  80. ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
  81. periphs_pinctrl: pinctrl@4000 {
  82. compatible = "amlogic,meson-s4-periphs-pinctrl";
  83. #address-cells = <2>;
  84. #size-cells = <2>;
  85. ranges;
  86. gpio: bank@4000 {
  87. reg = <0x0 0x4000 0x0 0x004c>,
  88. <0x0 0x40c0 0x0 0x0220>;
  89. reg-names = "mux", "gpio";
  90. gpio-controller;
  91. #gpio-cells = <2>;
  92. gpio-ranges = <&periphs_pinctrl 0 0 82>;
  93. };
  94. };
  95. gpio_intc: interrupt-controller@4080 {
  96. compatible = "amlogic,meson-s4-gpio-intc",
  97. "amlogic,meson-gpio-intc";
  98. reg = <0x0 0x4080 0x0 0x20>;
  99. interrupt-controller;
  100. #interrupt-cells = <2>;
  101. amlogic,channel-interrupts =
  102. <10 11 12 13 14 15 16 17 18 19 20 21>;
  103. };
  104. uart_B: serial@7a000 {
  105. compatible = "amlogic,meson-s4-uart",
  106. "amlogic,meson-ao-uart";
  107. reg = <0x0 0x7a000 0x0 0x18>;
  108. interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
  109. status = "disabled";
  110. clocks = <&xtal>, <&xtal>, <&xtal>;
  111. clock-names = "xtal", "pclk", "baud";
  112. };
  113. reset: reset-controller@2000 {
  114. compatible = "amlogic,meson-s4-reset";
  115. reg = <0x0 0x2000 0x0 0x98>;
  116. #reset-cells = <1>;
  117. };
  118. };
  119. };
  120. };