sun50i-a64-sopine.dtsi 2.6 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. // Copyright (c) 2017 Icenowy Zheng <[email protected]>
  3. // Based on sun50i-a64-pine64.dts, which is:
  4. // Copyright (c) 2016 ARM Ltd.
  5. #include "sun50i-a64.dtsi"
  6. #include "sun50i-a64-cpu-opp.dtsi"
  7. #include <dt-bindings/gpio/gpio.h>
  8. &codec_analog {
  9. cpvdd-supply = <&reg_eldo1>;
  10. };
  11. &cpu0 {
  12. cpu-supply = <&reg_dcdc2>;
  13. };
  14. &cpu1 {
  15. cpu-supply = <&reg_dcdc2>;
  16. };
  17. &cpu2 {
  18. cpu-supply = <&reg_dcdc2>;
  19. };
  20. &cpu3 {
  21. cpu-supply = <&reg_dcdc2>;
  22. };
  23. &mmc0 {
  24. pinctrl-names = "default";
  25. pinctrl-0 = <&mmc0_pins>;
  26. vmmc-supply = <&reg_dcdc1>;
  27. disable-wp;
  28. bus-width = <4>;
  29. cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 push-pull switch */
  30. status = "okay";
  31. };
  32. &r_rsb {
  33. status = "okay";
  34. axp803: pmic@3a3 {
  35. compatible = "x-powers,axp803";
  36. reg = <0x3a3>;
  37. interrupt-parent = <&r_intc>;
  38. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
  39. };
  40. };
  41. &spi0 {
  42. status = "okay";
  43. flash@0 {
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. compatible = "jedec,spi-nor";
  47. reg = <0>;
  48. spi-max-frequency = <40000000>;
  49. };
  50. };
  51. #include "axp803.dtsi"
  52. &reg_aldo2 {
  53. regulator-always-on;
  54. regulator-min-microvolt = <1800000>;
  55. regulator-max-microvolt = <3300000>;
  56. regulator-name = "vcc-pl";
  57. };
  58. &reg_aldo3 {
  59. regulator-always-on;
  60. regulator-min-microvolt = <3000000>;
  61. regulator-max-microvolt = <3000000>;
  62. regulator-name = "vcc-pll-avcc";
  63. };
  64. &reg_dcdc1 {
  65. regulator-always-on;
  66. regulator-min-microvolt = <3300000>;
  67. regulator-max-microvolt = <3300000>;
  68. regulator-name = "vcc-3v3";
  69. };
  70. &reg_dcdc2 {
  71. regulator-always-on;
  72. regulator-min-microvolt = <1040000>;
  73. regulator-max-microvolt = <1300000>;
  74. regulator-name = "vdd-cpux";
  75. };
  76. /* DCDC3 is polyphased with DCDC2 */
  77. &reg_dcdc5 {
  78. regulator-always-on;
  79. regulator-min-microvolt = <1200000>;
  80. regulator-max-microvolt = <1200000>;
  81. regulator-name = "vcc-dram";
  82. };
  83. &reg_dcdc6 {
  84. regulator-always-on;
  85. regulator-min-microvolt = <1100000>;
  86. regulator-max-microvolt = <1100000>;
  87. regulator-name = "vdd-sys";
  88. };
  89. &reg_eldo1 {
  90. regulator-always-on;
  91. regulator-min-microvolt = <1800000>;
  92. regulator-max-microvolt = <1800000>;
  93. regulator-name = "vdd-1v8-lpddr";
  94. };
  95. &reg_fldo1 {
  96. regulator-min-microvolt = <1200000>;
  97. regulator-max-microvolt = <1200000>;
  98. regulator-name = "vcc-1v2-hsic";
  99. };
  100. /*
  101. * The A64 chip cannot work without this regulator off, although
  102. * it seems to be only driving the AR100 core.
  103. * Maybe we don't still know well about CPUs domain.
  104. */
  105. &reg_fldo2 {
  106. regulator-always-on;
  107. regulator-min-microvolt = <1100000>;
  108. regulator-max-microvolt = <1100000>;
  109. regulator-name = "vdd-cpus";
  110. };
  111. &reg_rtc_ldo {
  112. regulator-name = "vcc-rtc";
  113. };