regs-syscon-power-s3c64xx.h 3.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright 2008 Openmoko, Inc.
  4. * Copyright 2008 Simtec Electronics
  5. * http://armlinux.simtec.co.uk/
  6. * Ben Dooks <[email protected]>
  7. *
  8. * S3C64XX - syscon power and sleep control registers
  9. */
  10. #ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H
  11. #define __MACH_S3C64XX_REGS_SYSCON_POWER_H __FILE__
  12. #define S3C64XX_PWR_CFG S3C_SYSREG(0x804)
  13. #define S3C64XX_PWRCFG_OSC_OTG_DISABLE (1 << 17)
  14. #define S3C64XX_PWRCFG_MMC2_DISABLE (1 << 16)
  15. #define S3C64XX_PWRCFG_MMC1_DISABLE (1 << 15)
  16. #define S3C64XX_PWRCFG_MMC0_DISABLE (1 << 14)
  17. #define S3C64XX_PWRCFG_HSI_DISABLE (1 << 13)
  18. #define S3C64XX_PWRCFG_TS_DISABLE (1 << 12)
  19. #define S3C64XX_PWRCFG_RTC_TICK_DISABLE (1 << 11)
  20. #define S3C64XX_PWRCFG_RTC_ALARM_DISABLE (1 << 10)
  21. #define S3C64XX_PWRCFG_MSM_DISABLE (1 << 9)
  22. #define S3C64XX_PWRCFG_KEY_DISABLE (1 << 8)
  23. #define S3C64XX_PWRCFG_BATF_DISABLE (1 << 7)
  24. #define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5)
  25. #define S3C64XX_PWRCFG_CFG_WFI_SHIFT (5)
  26. #define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5)
  27. #define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5)
  28. #define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5)
  29. #define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5)
  30. #define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3)
  31. #define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT (3)
  32. #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3)
  33. #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3)
  34. #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3)
  35. #define S3C64XX_PWRCFG_CFG_BAT_WAKE (1 << 2)
  36. #define S3C64XX_PWRCFG_OSC27_EN (1 << 0)
  37. #define S3C64XX_EINT_MASK S3C_SYSREG(0x808)
  38. #define S3C64XX_NORMAL_CFG S3C_SYSREG(0x810)
  39. #define S3C64XX_NORMALCFG_IROM_ON (1 << 30)
  40. #define S3C64XX_NORMALCFG_DOMAIN_ETM_ON (1 << 16)
  41. #define S3C64XX_NORMALCFG_DOMAIN_S_ON (1 << 15)
  42. #define S3C64XX_NORMALCFG_DOMAIN_F_ON (1 << 14)
  43. #define S3C64XX_NORMALCFG_DOMAIN_P_ON (1 << 13)
  44. #define S3C64XX_NORMALCFG_DOMAIN_I_ON (1 << 12)
  45. #define S3C64XX_NORMALCFG_DOMAIN_G_ON (1 << 10)
  46. #define S3C64XX_NORMALCFG_DOMAIN_V_ON (1 << 9)
  47. #define S3C64XX_STOP_CFG S3C_SYSREG(0x814)
  48. #define S3C64XX_STOPCFG_MEMORY_ARM_ON (1 << 29)
  49. #define S3C64XX_STOPCFG_TOP_MEMORY_ON (1 << 20)
  50. #define S3C64XX_STOPCFG_ARM_LOGIC_ON (1 << 17)
  51. #define S3C64XX_STOPCFG_TOP_LOGIC_ON (1 << 8)
  52. #define S3C64XX_STOPCFG_OSC_EN (1 << 0)
  53. #define S3C64XX_SLEEP_CFG S3C_SYSREG(0x818)
  54. #define S3C64XX_SLEEPCFG_OSC_EN (1 << 0)
  55. #define S3C64XX_STOP_MEM_CFG S3C_SYSREG(0x81c)
  56. #define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN (1 << 6)
  57. #define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN (1 << 5)
  58. #define S3C64XX_STOPMEMCFG_OTG_RETAIN (1 << 4)
  59. #define S3C64XX_STOPMEMCFG_HSMCC_RETAIN (1 << 3)
  60. #define S3C64XX_STOPMEMCFG_IROM_RETAIN (1 << 2)
  61. #define S3C64XX_STOPMEMCFG_IRDA_RETAIN (1 << 1)
  62. #define S3C64XX_STOPMEMCFG_NFCON_RETAIN (1 << 0)
  63. #define S3C64XX_OSC_STABLE S3C_SYSREG(0x824)
  64. #define S3C64XX_PWR_STABLE S3C_SYSREG(0x828)
  65. #define S3C64XX_WAKEUP_STAT S3C_SYSREG(0x908)
  66. #define S3C64XX_WAKEUPSTAT_MMC2 (1 << 11)
  67. #define S3C64XX_WAKEUPSTAT_MMC1 (1 << 10)
  68. #define S3C64XX_WAKEUPSTAT_MMC0 (1 << 9)
  69. #define S3C64XX_WAKEUPSTAT_HSI (1 << 8)
  70. #define S3C64XX_WAKEUPSTAT_BATFLT (1 << 6)
  71. #define S3C64XX_WAKEUPSTAT_MSM (1 << 5)
  72. #define S3C64XX_WAKEUPSTAT_KEY (1 << 4)
  73. #define S3C64XX_WAKEUPSTAT_TS (1 << 3)
  74. #define S3C64XX_WAKEUPSTAT_RTC_TICK (1 << 2)
  75. #define S3C64XX_WAKEUPSTAT_RTC_ALARM (1 << 1)
  76. #define S3C64XX_WAKEUPSTAT_EINT (1 << 0)
  77. #define S3C64XX_BLK_PWR_STAT S3C_SYSREG(0x90c)
  78. #define S3C64XX_BLKPWRSTAT_G (1 << 7)
  79. #define S3C64XX_BLKPWRSTAT_ETM (1 << 6)
  80. #define S3C64XX_BLKPWRSTAT_S (1 << 5)
  81. #define S3C64XX_BLKPWRSTAT_F (1 << 4)
  82. #define S3C64XX_BLKPWRSTAT_P (1 << 3)
  83. #define S3C64XX_BLKPWRSTAT_I (1 << 2)
  84. #define S3C64XX_BLKPWRSTAT_V (1 << 1)
  85. #define S3C64XX_BLKPWRSTAT_TOP (1 << 0)
  86. #define S3C64XX_INFORM0 S3C_SYSREG(0xA00)
  87. #define S3C64XX_INFORM1 S3C_SYSREG(0xA04)
  88. #define S3C64XX_INFORM2 S3C_SYSREG(0xA08)
  89. #define S3C64XX_INFORM3 S3C_SYSREG(0xA0C)
  90. #endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H */