pll-s3c2440-16934400.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2006-2008 Simtec Electronics
  4. // http://armlinux.simtec.co.uk/
  5. // Ben Dooks <[email protected]>
  6. // Vincent Sanders <[email protected]>
  7. //
  8. // S3C2440/S3C2442 CPU PLL tables (16.93444MHz Crystal)
  9. #include <linux/types.h>
  10. #include <linux/kernel.h>
  11. #include <linux/device.h>
  12. #include <linux/clk.h>
  13. #include <linux/err.h>
  14. #include <linux/soc/samsung/s3c-cpufreq-core.h>
  15. #include <linux/soc/samsung/s3c-pm.h>
  16. /* This array should be sorted in ascending order of the frequencies */
  17. static struct cpufreq_frequency_table s3c2440_plls_169344[] = {
  18. { .frequency = 78019200, .driver_data = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */
  19. { .frequency = 84067200, .driver_data = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */
  20. { .frequency = 90115200, .driver_data = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */
  21. { .frequency = 96163200, .driver_data = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */
  22. { .frequency = 102135600, .driver_data = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */
  23. { .frequency = 108259200, .driver_data = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */
  24. { .frequency = 114307200, .driver_data = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */
  25. { .frequency = 120234240, .driver_data = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */
  26. { .frequency = 126161280, .driver_data = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */
  27. { .frequency = 132088320, .driver_data = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */
  28. { .frequency = 138015360, .driver_data = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */
  29. { .frequency = 144789120, .driver_data = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */
  30. { .frequency = 150100363, .driver_data = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */
  31. { .frequency = 156038400, .driver_data = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */
  32. { .frequency = 162086400, .driver_data = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */
  33. { .frequency = 168134400, .driver_data = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */
  34. { .frequency = 174048000, .driver_data = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */
  35. { .frequency = 180230400, .driver_data = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */
  36. { .frequency = 186278400, .driver_data = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */
  37. { .frequency = 192326400, .driver_data = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */
  38. { .frequency = 198132480, .driver_data = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */
  39. { .frequency = 204271200, .driver_data = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */
  40. { .frequency = 210268800, .driver_data = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */
  41. { .frequency = 216518400, .driver_data = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */
  42. { .frequency = 222264000, .driver_data = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */
  43. { .frequency = 228614400, .driver_data = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */
  44. { .frequency = 234259200, .driver_data = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */
  45. { .frequency = 240468480, .driver_data = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */
  46. { .frequency = 246960000, .driver_data = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */
  47. { .frequency = 252322560, .driver_data = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */
  48. { .frequency = 258249600, .driver_data = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */
  49. { .frequency = 264176640, .driver_data = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */
  50. { .frequency = 270950400, .driver_data = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */
  51. { .frequency = 276030720, .driver_data = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */
  52. { .frequency = 282240000, .driver_data = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */
  53. { .frequency = 289578240, .driver_data = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */
  54. { .frequency = 294235200, .driver_data = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */
  55. { .frequency = 300200727, .driver_data = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */
  56. { .frequency = 306358690, .driver_data = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */
  57. { .frequency = 312076800, .driver_data = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */
  58. { .frequency = 318366720, .driver_data = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */
  59. { .frequency = 324172800, .driver_data = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */
  60. { .frequency = 330220800, .driver_data = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */
  61. { .frequency = 336268800, .driver_data = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */
  62. { .frequency = 342074880, .driver_data = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */
  63. { .frequency = 348096000, .driver_data = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */
  64. { .frequency = 355622400, .driver_data = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */
  65. { .frequency = 360460800, .driver_data = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */
  66. { .frequency = 366206400, .driver_data = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */
  67. { .frequency = 372556800, .driver_data = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */
  68. { .frequency = 378201600, .driver_data = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */
  69. { .frequency = 384652800, .driver_data = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */
  70. { .frequency = 391608000, .driver_data = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */
  71. { .frequency = 396264960, .driver_data = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */
  72. { .frequency = 402192000, .driver_data = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */
  73. };
  74. static int s3c2440_plls169344_add(struct device *dev,
  75. struct subsys_interface *sif)
  76. {
  77. struct clk *xtal_clk;
  78. unsigned long xtal;
  79. xtal_clk = clk_get(NULL, "xtal");
  80. if (IS_ERR(xtal_clk))
  81. return PTR_ERR(xtal_clk);
  82. xtal = clk_get_rate(xtal_clk);
  83. clk_put(xtal_clk);
  84. if (xtal == 169344000) {
  85. printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n");
  86. return s3c_plltab_register(s3c2440_plls_169344,
  87. ARRAY_SIZE(s3c2440_plls_169344));
  88. }
  89. return 0;
  90. }
  91. static struct subsys_interface s3c2440_plls169344_interface = {
  92. .name = "s3c2440_plls169344",
  93. .subsys = &s3c2440_subsys,
  94. .add_dev = s3c2440_plls169344_add,
  95. };
  96. static int __init s3c2440_pll_16934400(void)
  97. {
  98. return subsys_interface_register(&s3c2440_plls169344_interface);
  99. }
  100. arch_initcall(s3c2440_pll_16934400);
  101. static struct subsys_interface s3c2442_plls169344_interface = {
  102. .name = "s3c2442_plls169344",
  103. .subsys = &s3c2442_subsys,
  104. .add_dev = s3c2440_plls169344_add,
  105. };
  106. static int __init s3c2442_pll_16934400(void)
  107. {
  108. return subsys_interface_register(&s3c2442_plls169344_interface);
  109. }
  110. arch_initcall(s3c2442_pll_16934400);