hardware.h 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * arch/arm/mach-rpc/include/mach/hardware.h
  4. *
  5. * Copyright (C) 1996-1999 Russell King.
  6. *
  7. * This file contains the hardware definitions of the RiscPC series machines.
  8. */
  9. #ifndef __ASM_ARCH_HARDWARE_H
  10. #define __ASM_ARCH_HARDWARE_H
  11. #include <mach/memory.h>
  12. /*
  13. * What hardware must be present
  14. */
  15. #define HAS_IOMD
  16. #define HAS_VIDC20
  17. /* Hardware addresses of major areas.
  18. * *_START is the physical address
  19. * *_SIZE is the size of the region
  20. * *_BASE is the virtual address
  21. */
  22. #define RPC_RAM_SIZE 0x10000000
  23. #define RPC_RAM_START 0x10000000
  24. #define EASI_SIZE 0x08000000 /* EASI I/O */
  25. #define EASI_START 0x08000000
  26. #define EASI_BASE IOMEM(0xe5000000)
  27. #define IO_START 0x03000000 /* I/O */
  28. #define IO_SIZE 0x01000000
  29. #define IO_BASE IOMEM(0xe0000000)
  30. #define SCREEN_START 0x02000000 /* VRAM */
  31. #define SCREEN_END 0xdfc00000
  32. #define SCREEN_BASE 0xdf800000
  33. #define UNCACHEABLE_ADDR (FLUSH_BASE + 0x10000)
  34. /*
  35. * IO Addresses
  36. */
  37. #define ECARD_EASI_BASE (EASI_BASE)
  38. #define VIDC_BASE (IO_BASE + 0x00400000)
  39. #define EXPMASK_BASE (IO_BASE + 0x00360000)
  40. #define ECARD_IOC4_BASE (IO_BASE + 0x00270000)
  41. #define ECARD_IOC_BASE (IO_BASE + 0x00240000)
  42. #define IOMD_BASE (IO_BASE + 0x00200000)
  43. #define IOC_BASE (IO_BASE + 0x00200000)
  44. #define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000)
  45. #define FLOPPYDMA_BASE (IO_BASE + 0x0002a000)
  46. #define PCIO_BASE (IO_BASE + 0x00010000)
  47. #define ECARD_MEMC_BASE (IO_BASE + 0x00000000)
  48. #define vidc_writel(val) __raw_writel(val, VIDC_BASE)
  49. #define NETSLOT_BASE 0x0302b000
  50. #define NETSLOT_SIZE 0x00001000
  51. #define PODSLOT_IOC0_BASE 0x03240000
  52. #define PODSLOT_IOC4_BASE 0x03270000
  53. #define PODSLOT_IOC_SIZE (1 << 14)
  54. #define PODSLOT_MEMC_BASE 0x03000000
  55. #define PODSLOT_MEMC_SIZE (1 << 14)
  56. #define PODSLOT_EASI_BASE 0x08000000
  57. #define PODSLOT_EASI_SIZE (1 << 24)
  58. #define EXPMASK_STATUS (EXPMASK_BASE + 0x00)
  59. #define EXPMASK_ENABLE (EXPMASK_BASE + 0x04)
  60. #endif