sleep.S 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Exynos low-level resume code
  7. */
  8. #include <linux/linkage.h>
  9. #include <asm/asm-offsets.h>
  10. #include <asm/hardware/cache-l2x0.h>
  11. #include "smc.h"
  12. #define CPU_MASK 0xff0ffff0
  13. #define CPU_CORTEX_A9 0x410fc090
  14. .text
  15. .align
  16. /*
  17. * sleep magic, to allow the bootloader to check for an valid
  18. * image to resume to. Must be the first word before the
  19. * exynos_cpu_resume entry.
  20. */
  21. .word 0x2bedf00d
  22. /*
  23. * exynos_cpu_resume
  24. *
  25. * resume code entry for bootloader to call
  26. */
  27. ENTRY(exynos_cpu_resume)
  28. #ifdef CONFIG_CACHE_L2X0
  29. mrc p15, 0, r0, c0, c0, 0
  30. ldr r1, =CPU_MASK
  31. and r0, r0, r1
  32. ldr r1, =CPU_CORTEX_A9
  33. cmp r0, r1
  34. bleq l2c310_early_resume
  35. #endif
  36. b cpu_resume
  37. ENDPROC(exynos_cpu_resume)
  38. .align
  39. .arch armv7-a
  40. .arch_extension sec
  41. ENTRY(exynos_cpu_resume_ns)
  42. mrc p15, 0, r0, c0, c0, 0
  43. ldr r1, =CPU_MASK
  44. and r0, r0, r1
  45. ldr r1, =CPU_CORTEX_A9
  46. cmp r0, r1
  47. bne skip_cp15
  48. adr r0, _cp15_save_power
  49. ldr r1, [r0]
  50. ldr r1, [r0, r1]
  51. adr r0, _cp15_save_diag
  52. ldr r2, [r0]
  53. ldr r2, [r0, r2]
  54. mov r0, #SMC_CMD_C15RESUME
  55. dsb
  56. smc #0
  57. #ifdef CONFIG_CACHE_L2X0
  58. adr r0, 1f
  59. ldr r2, [r0]
  60. add r0, r2, r0
  61. /* Check that the address has been initialised. */
  62. ldr r1, [r0, #L2X0_R_PHY_BASE]
  63. teq r1, #0
  64. beq skip_l2x0
  65. /* Check if controller has been enabled. */
  66. ldr r2, [r1, #L2X0_CTRL]
  67. tst r2, #0x1
  68. bne skip_l2x0
  69. ldr r1, [r0, #L2X0_R_TAG_LATENCY]
  70. ldr r2, [r0, #L2X0_R_DATA_LATENCY]
  71. ldr r3, [r0, #L2X0_R_PREFETCH_CTRL]
  72. mov r0, #SMC_CMD_L2X0SETUP1
  73. smc #0
  74. /* Reload saved regs pointer because smc corrupts registers. */
  75. adr r0, 1f
  76. ldr r2, [r0]
  77. add r0, r2, r0
  78. ldr r1, [r0, #L2X0_R_PWR_CTRL]
  79. ldr r2, [r0, #L2X0_R_AUX_CTRL]
  80. mov r0, #SMC_CMD_L2X0SETUP2
  81. smc #0
  82. mov r0, #SMC_CMD_L2X0INVALL
  83. smc #0
  84. mov r1, #1
  85. mov r0, #SMC_CMD_L2X0CTRL
  86. smc #0
  87. skip_l2x0:
  88. #endif /* CONFIG_CACHE_L2X0 */
  89. skip_cp15:
  90. b cpu_resume
  91. ENDPROC(exynos_cpu_resume_ns)
  92. .align
  93. _cp15_save_power:
  94. .long cp15_save_power - .
  95. _cp15_save_diag:
  96. .long cp15_save_diag - .
  97. #ifdef CONFIG_CACHE_L2X0
  98. 1: .long l2x0_saved_regs - .
  99. #endif /* CONFIG_CACHE_L2X0 */
  100. .data
  101. .align 2
  102. .globl cp15_save_diag
  103. cp15_save_diag:
  104. .long 0 @ cp15 diagnostic
  105. .globl cp15_save_power
  106. cp15_save_power:
  107. .long 0 @ cp15 power control