tegra30-pegatron-chagall.dts 82 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/gpio-keys.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/thermal/thermal.h>
  6. #include "tegra30.dtsi"
  7. #include "tegra30-cpu-opp.dtsi"
  8. #include "tegra30-cpu-opp-microvolt.dtsi"
  9. #include "tegra30-asus-lvds-display.dtsi"
  10. / {
  11. model = "Pegatron Chagall";
  12. compatible = "pegatron,chagall", "nvidia,tegra30";
  13. chassis-type = "tablet";
  14. aliases {
  15. mmc0 = &sdmmc4; /* eMMC */
  16. mmc1 = &sdmmc1; /* uSD slot */
  17. mmc2 = &sdmmc3; /* WiFi */
  18. rtc0 = &pmic;
  19. rtc1 = "/rtc@7000e000";
  20. display0 = &lcd;
  21. display1 = &hdmi;
  22. serial1 = &uartc; /* Bluetooth */
  23. serial2 = &uartb; /* GPS */
  24. };
  25. /*
  26. * The decompressor and also some bootloaders rely on a
  27. * pre-existing /chosen node to be available to insert the
  28. * command line and merge other ATAGS info.
  29. */
  30. chosen {};
  31. memory@80000000 {
  32. reg = <0x80000000 0x40000000>;
  33. };
  34. reserved-memory {
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. ranges;
  38. linux,cma@80000000 {
  39. compatible = "shared-dma-pool";
  40. alloc-ranges = <0x80000000 0x30000000>;
  41. size = <0x10000000>; /* 256MiB */
  42. linux,cma-default;
  43. reusable;
  44. };
  45. ramoops@beb00000 {
  46. compatible = "ramoops";
  47. reg = <0xbeb00000 0x10000>; /* 64kB */
  48. console-size = <0x8000>; /* 32kB */
  49. record-size = <0x400>; /* 1kB */
  50. ecc-size = <16>;
  51. };
  52. trustzone@bfe00000 {
  53. reg = <0xbfe00000 0x200000>; /* 2MB */
  54. no-map;
  55. };
  56. };
  57. host1x@50000000 {
  58. hdmi: hdmi@54280000 {
  59. status = "okay";
  60. hdmi-supply = <&hdmi_5v0_sys>;
  61. pll-supply = <&vdd_1v8_vio>;
  62. vdd-supply = <&vdd_3v3_sys>;
  63. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  64. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  65. };
  66. };
  67. vde@6001a000 {
  68. assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
  69. assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
  70. assigned-clock-rates = <408000000>;
  71. };
  72. pinmux@70000868 {
  73. pinctrl-names = "default";
  74. pinctrl-0 = <&state_default>;
  75. state_default: pinmux {
  76. /* SDMMC1 pinmux */
  77. sdmmc1_clk_pz0 {
  78. nvidia,pins = "sdmmc1_clk_pz0";
  79. nvidia,function = "sdmmc1";
  80. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  81. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  82. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  83. };
  84. sdmmc1_dat3_py4 {
  85. nvidia,pins = "sdmmc1_dat3_py4",
  86. "sdmmc1_dat2_py5",
  87. "sdmmc1_dat1_py6",
  88. "sdmmc1_dat0_py7",
  89. "sdmmc1_cmd_pz1";
  90. nvidia,function = "sdmmc1";
  91. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  92. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  93. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  94. };
  95. /* SDMMC2 pinmux */
  96. vi_d1_pd5 {
  97. nvidia,pins = "vi_d1_pd5",
  98. "vi_d2_pl0",
  99. "vi_d3_pl1",
  100. "vi_d5_pl3",
  101. "vi_d7_pl5";
  102. nvidia,function = "sdmmc2";
  103. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  104. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  105. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  106. };
  107. vi_d8_pl6 {
  108. nvidia,pins = "vi_d8_pl6",
  109. "vi_d9_pl7";
  110. nvidia,function = "sdmmc2";
  111. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  112. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  113. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  114. nvidia,lock = <0>;
  115. nvidia,ioreset = <0>;
  116. };
  117. /* SDMMC3 pinmux */
  118. sdmmc3_clk_pa6 {
  119. nvidia,pins = "sdmmc3_clk_pa6";
  120. nvidia,function = "sdmmc3";
  121. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  122. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  123. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  124. };
  125. sdmmc3_cmd_pa7 {
  126. nvidia,pins = "sdmmc3_cmd_pa7",
  127. "sdmmc3_dat3_pb4",
  128. "sdmmc3_dat2_pb5",
  129. "sdmmc3_dat2_pb5",
  130. "sdmmc3_dat1_pb6",
  131. "sdmmc3_dat0_pb7",
  132. "sdmmc3_dat5_pd0",
  133. "sdmmc3_dat4_pd1",
  134. "sdmmc3_dat6_pd3",
  135. "sdmmc3_dat7_pd4";
  136. nvidia,function = "sdmmc3";
  137. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  138. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  139. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  140. };
  141. /* SDMMC4 pinmux */
  142. sdmmc4_clk_pcc4 {
  143. nvidia,pins = "sdmmc4_clk_pcc4";
  144. nvidia,function = "sdmmc4";
  145. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  146. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  147. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  148. };
  149. sdmmc4_cmd_pt7 {
  150. nvidia,pins = "sdmmc4_cmd_pt7",
  151. "sdmmc4_dat0_paa0",
  152. "sdmmc4_dat1_paa1",
  153. "sdmmc4_dat2_paa2",
  154. "sdmmc4_dat3_paa3",
  155. "sdmmc4_dat4_paa4",
  156. "sdmmc4_dat5_paa5",
  157. "sdmmc4_dat6_paa6",
  158. "sdmmc4_dat7_paa7";
  159. nvidia,function = "sdmmc4";
  160. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  161. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  162. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  163. };
  164. /* I2C pinmux */
  165. gen1_i2c_scl_pc4 {
  166. nvidia,pins = "gen1_i2c_scl_pc4",
  167. "gen1_i2c_sda_pc5";
  168. nvidia,function = "i2c1";
  169. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  170. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  171. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  172. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  173. nvidia,lock = <0>;
  174. };
  175. gen2_i2c_scl_pt5 {
  176. nvidia,pins = "gen2_i2c_scl_pt5",
  177. "gen2_i2c_sda_pt6";
  178. nvidia,function = "i2c2";
  179. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  180. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  181. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  182. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  183. nvidia,lock = <0>;
  184. };
  185. cam_i2c_scl_pbb1 {
  186. nvidia,pins = "cam_i2c_scl_pbb1",
  187. "cam_i2c_sda_pbb2";
  188. nvidia,function = "i2c3";
  189. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  190. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  191. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  192. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  193. nvidia,lock = <0>;
  194. };
  195. ddc_scl_pv4 {
  196. nvidia,pins = "ddc_scl_pv4",
  197. "ddc_sda_pv5";
  198. nvidia,function = "i2c4";
  199. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  200. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  201. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  202. nvidia,lock = <0>;
  203. };
  204. pwr_i2c_scl_pz6 {
  205. nvidia,pins = "pwr_i2c_scl_pz6",
  206. "pwr_i2c_sda_pz7";
  207. nvidia,function = "i2cpwr";
  208. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  209. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  210. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  211. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  212. nvidia,lock = <0>;
  213. };
  214. /* HDMI-CEC pinmux */
  215. hdmi_cec_pee3 {
  216. nvidia,pins = "hdmi_cec_pee3";
  217. nvidia,function = "cec";
  218. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  219. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  220. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  221. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  222. nvidia,lock = <0>;
  223. };
  224. /* UART-A */
  225. ulpi_data0_po1 {
  226. nvidia,pins = "ulpi_data0_po1";
  227. nvidia,function = "uarta";
  228. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  229. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  230. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  231. };
  232. ulpi_data1_po2 {
  233. nvidia,pins = "ulpi_data1_po2",
  234. "ulpi_data2_po3",
  235. "ulpi_data3_po4",
  236. "ulpi_data4_po5",
  237. "ulpi_data5_po6",
  238. "ulpi_data6_po7";
  239. nvidia,function = "uarta";
  240. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  241. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  242. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  243. };
  244. ulpi_data7_po0 {
  245. nvidia,pins = "ulpi_data7_po0";
  246. nvidia,function = "uarta";
  247. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  248. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  249. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  250. };
  251. /* UART-B */
  252. uart2_txd_pc2 {
  253. nvidia,pins = "uart2_txd_pc2",
  254. "uart2_rts_n_pj6";
  255. nvidia,function = "uartb";
  256. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  257. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  258. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  259. };
  260. uart2_rxd_pc3 {
  261. nvidia,pins = "uart2_rxd_pc3",
  262. "uart2_cts_n_pj5";
  263. nvidia,function = "uartb";
  264. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  265. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  266. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  267. };
  268. /* UART-C */
  269. uart3_cts_n_pa1 {
  270. nvidia,pins = "uart3_cts_n_pa1",
  271. "uart3_rxd_pw7";
  272. nvidia,function = "uartc";
  273. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  274. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  275. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  276. };
  277. uart3_rts_n_pc0 {
  278. nvidia,pins = "uart3_rts_n_pc0",
  279. "uart3_txd_pw6";
  280. nvidia,function = "uartc";
  281. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  282. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  283. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  284. };
  285. /* UART-D */
  286. ulpi_clk_py0 {
  287. nvidia,pins = "ulpi_clk_py0",
  288. "ulpi_stp_py3";
  289. nvidia,function = "uartd";
  290. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  291. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  292. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  293. };
  294. ulpi_dir_py1 {
  295. nvidia,pins = "ulpi_dir_py1",
  296. "ulpi_nxt_py2";
  297. nvidia,function = "uartd";
  298. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  299. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  300. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  301. };
  302. /* I2S pinmux */
  303. dap1_fs_pn0 {
  304. nvidia,pins = "dap1_fs_pn0",
  305. "dap1_din_pn1",
  306. "dap1_dout_pn2",
  307. "dap1_sclk_pn3";
  308. nvidia,function = "i2s0";
  309. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  310. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  311. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  312. };
  313. dap2_fs_pa2 {
  314. nvidia,pins = "dap2_fs_pa2",
  315. "dap2_sclk_pa3",
  316. "dap2_din_pa4",
  317. "dap2_dout_pa5";
  318. nvidia,function = "i2s1";
  319. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  320. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  321. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  322. };
  323. dap3_fs_pp0 {
  324. nvidia,pins = "dap3_fs_pp0",
  325. "dap3_din_pp1",
  326. "dap3_dout_pp2",
  327. "dap3_sclk_pp3";
  328. nvidia,function = "i2s2";
  329. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  330. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  331. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  332. };
  333. dap4_fs_pp4 {
  334. nvidia,pins = "dap4_fs_pp4",
  335. "dap4_din_pp5",
  336. "dap4_dout_pp6",
  337. "dap4_sclk_pp7";
  338. nvidia,function = "i2s3";
  339. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  340. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  341. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  342. };
  343. pcc2 {
  344. nvidia,pins = "pcc2";
  345. nvidia,function = "i2s4";
  346. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  347. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  348. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  349. };
  350. /* PCI-e pinmux */
  351. pex_l2_rst_n_pcc6 {
  352. nvidia,pins = "pex_l2_rst_n_pcc6",
  353. "pex_l0_rst_n_pdd1",
  354. "pex_l1_rst_n_pdd5";
  355. nvidia,function = "pcie";
  356. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  357. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  358. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  359. };
  360. pex_l2_clkreq_n_pcc7 {
  361. nvidia,pins = "pex_l2_clkreq_n_pcc7",
  362. "pex_l0_prsnt_n_pdd0",
  363. "pex_l0_clkreq_n_pdd2",
  364. "pex_l2_prsnt_n_pdd7";
  365. nvidia,function = "pcie";
  366. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  367. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  368. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  369. };
  370. pex_wake_n_pdd3 {
  371. nvidia,pins = "pex_wake_n_pdd3";
  372. nvidia,function = "pcie";
  373. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  374. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  375. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  376. };
  377. /* SPI pinmux */
  378. spi1_mosi_px4 {
  379. nvidia,pins = "spi1_mosi_px4",
  380. "spi1_sck_px5",
  381. "spi1_cs0_n_px6",
  382. "spi1_miso_px7";
  383. nvidia,function = "spi1";
  384. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  385. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  386. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  387. };
  388. spi2_cs1_n_pw2 {
  389. nvidia,pins = "spi2_cs1_n_pw2",
  390. "spi2_cs2_n_pw3";
  391. nvidia,function = "spi2";
  392. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  393. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  394. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  395. };
  396. spi2_sck_px2 {
  397. nvidia,pins = "spi2_sck_px2";
  398. nvidia,function = "gmi";
  399. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  400. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  401. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  402. };
  403. gmi_a16_pj7 {
  404. nvidia,pins = "gmi_a16_pj7",
  405. "gmi_a19_pk7";
  406. nvidia,function = "spi4";
  407. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  408. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  409. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  410. };
  411. gmi_a17_pb0 {
  412. nvidia,pins = "gmi_a17_pb0",
  413. "gmi_a18_pb1";
  414. nvidia,function = "spi4";
  415. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  416. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  417. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  418. };
  419. spi2_mosi_px0 {
  420. nvidia,pins = "spi2_mosi_px0";
  421. nvidia,function = "spi6";
  422. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  423. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  424. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  425. };
  426. spdif_out_pk5 {
  427. nvidia,pins = "spdif_out_pk5";
  428. nvidia,function = "spdif";
  429. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  430. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  431. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  432. };
  433. spdif_in_pk6 {
  434. nvidia,pins = "spdif_in_pk6";
  435. nvidia,function = "spdif";
  436. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  437. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  438. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  439. };
  440. /* Display A pinmux */
  441. lcd_pwr0_pb2 {
  442. nvidia,pins = "lcd_pwr0_pb2",
  443. "lcd_pclk_pb3",
  444. "lcd_pwr1_pc1",
  445. "lcd_pwr2_pc6",
  446. "lcd_d0_pe0",
  447. "lcd_d1_pe1",
  448. "lcd_d2_pe2",
  449. "lcd_d3_pe3",
  450. "lcd_d4_pe4",
  451. "lcd_d5_pe5",
  452. "lcd_d6_pe6",
  453. "lcd_d7_pe7",
  454. "lcd_d8_pf0",
  455. "lcd_d9_pf1",
  456. "lcd_d10_pf2",
  457. "lcd_d11_pf3",
  458. "lcd_d12_pf4",
  459. "lcd_d13_pf5",
  460. "lcd_d14_pf6",
  461. "lcd_d15_pf7",
  462. "lcd_de_pj1",
  463. "lcd_hsync_pj3",
  464. "lcd_vsync_pj4",
  465. "lcd_d16_pm0",
  466. "lcd_d17_pm1",
  467. "lcd_d18_pm2",
  468. "lcd_d19_pm3",
  469. "lcd_d20_pm4",
  470. "lcd_d21_pm5",
  471. "lcd_d22_pm6",
  472. "lcd_d23_pm7",
  473. "lcd_cs0_n_pn4",
  474. "lcd_sdout_pn5",
  475. "lcd_dc0_pn6",
  476. "lcd_sdin_pz2",
  477. "lcd_wr_n_pz3",
  478. "lcd_sck_pz4",
  479. "lcd_cs1_n_pw0",
  480. "lcd_m1_pw1";
  481. nvidia,function = "displaya";
  482. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  483. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  484. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  485. };
  486. lcd_dc1_pd2 {
  487. nvidia,pins = "lcd_dc1_pd2";
  488. nvidia,function = "displaya";
  489. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  490. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  491. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  492. };
  493. clk_32k_out_pa0 {
  494. nvidia,pins = "clk_32k_out_pa0";
  495. nvidia,function = "blink";
  496. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  497. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  498. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  499. };
  500. /* KBC keys */
  501. kb_row0_pr0 {
  502. nvidia,pins = "kb_row0_pr0",
  503. "kb_row1_pr1",
  504. "kb_row2_pr2",
  505. "kb_row3_pr3",
  506. "kb_row8_ps0",
  507. "kb_col0_pq0",
  508. "kb_col1_pq1",
  509. "kb_col2_pq2",
  510. "kb_col3_pq3",
  511. "kb_col4_pq4",
  512. "kb_col5_pq5",
  513. "kb_col7_pq7";
  514. nvidia,function = "kbc";
  515. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  516. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  517. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  518. };
  519. kb_row4_pr4 {
  520. nvidia,pins = "kb_row4_pr4",
  521. "kb_row7_pr7",
  522. "kb_row10_ps2",
  523. "kb_row13_ps5";
  524. nvidia,function = "kbc";
  525. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  526. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  527. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  528. };
  529. kb_row11_ps3 {
  530. nvidia,pins = "kb_row11_ps3",
  531. "kb_row12_ps4",
  532. "kb_row15_ps7";
  533. nvidia,function = "kbc";
  534. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  535. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  536. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  537. };
  538. kb_row14_ps6 {
  539. nvidia,pins = "kb_row14_ps6";
  540. nvidia,function = "kbc";
  541. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  542. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  543. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  544. };
  545. gmi_iordy_pi5 {
  546. nvidia,pins = "gmi_iordy_pi5";
  547. nvidia,function = "rsvd1";
  548. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  549. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  550. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  551. };
  552. vi_pclk_pt0 {
  553. nvidia,pins = "vi_pclk_pt0";
  554. nvidia,function = "rsvd1";
  555. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  556. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  557. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  558. nvidia,lock = <0>;
  559. nvidia,ioreset = <0>;
  560. };
  561. pu1 {
  562. nvidia,pins = "pu1";
  563. nvidia,function = "rsvd1";
  564. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  565. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  566. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  567. };
  568. pu2 {
  569. nvidia,pins = "pu2";
  570. nvidia,function = "rsvd1";
  571. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  572. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  573. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  574. };
  575. pv0 {
  576. nvidia,pins = "pv0";
  577. nvidia,function = "rsvd1";
  578. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  579. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  580. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  581. };
  582. pv1 {
  583. nvidia,pins = "pv1";
  584. nvidia,function = "rsvd1";
  585. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  586. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  587. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  588. };
  589. pcc1 {
  590. nvidia,pins = "pcc1";
  591. nvidia,function = "rsvd2";
  592. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  593. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  594. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  595. };
  596. sdmmc4_rst_n_pcc3 {
  597. nvidia,pins = "sdmmc4_rst_n_pcc3";
  598. nvidia,function = "rsvd2";
  599. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  600. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  601. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  602. };
  603. pv3 {
  604. nvidia,pins = "pv3";
  605. nvidia,function = "rsvd2";
  606. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  607. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  608. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  609. };
  610. vi_vsync_pd6 {
  611. nvidia,pins = "vi_vsync_pd6",
  612. "vi_hsync_pd7";
  613. nvidia,function = "rsvd2";
  614. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  615. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  616. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  617. nvidia,lock = <0>;
  618. nvidia,ioreset = <0>;
  619. };
  620. vi_d10_pt2 {
  621. nvidia,pins = "vi_d10_pt2",
  622. "vi_d0_pt4", "pbb0";
  623. nvidia,function = "rsvd2";
  624. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  625. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  626. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  627. };
  628. vi_d11_pt3 {
  629. nvidia,pins = "vi_d11_pt3";
  630. nvidia,function = "rsvd2";
  631. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  632. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  633. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  634. };
  635. pu0 {
  636. nvidia,pins = "pu0";
  637. nvidia,function = "rsvd4";
  638. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  639. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  640. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  641. };
  642. pu3 {
  643. nvidia,pins = "pu3";
  644. nvidia,function = "rsvd4";
  645. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  646. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  647. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  648. };
  649. pu6 {
  650. nvidia,pins = "pu6";
  651. nvidia,function = "rsvd4";
  652. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  653. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  654. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  655. };
  656. pex_l1_prsnt_n_pdd4 {
  657. nvidia,pins = "pex_l1_prsnt_n_pdd4",
  658. "pex_l1_clkreq_n_pdd6";
  659. nvidia,function = "rsvd4";
  660. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  661. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  662. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  663. };
  664. gmi_wait_pi7 {
  665. nvidia,pins = "gmi_wait_pi7",
  666. "gmi_cs0_n_pj0",
  667. "gmi_cs1_n_pj2",
  668. "gmi_cs4_n_pk2";
  669. nvidia,function = "nand";
  670. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  671. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  672. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  673. };
  674. gmi_ad0_pg0 {
  675. nvidia,pins = "gmi_ad0_pg0",
  676. "gmi_ad1_pg1",
  677. "gmi_ad2_pg2",
  678. "gmi_ad3_pg3",
  679. "gmi_ad4_pg4",
  680. "gmi_ad5_pg5",
  681. "gmi_ad6_pg6",
  682. "gmi_ad7_pg7",
  683. "gmi_wr_n_pi0",
  684. "gmi_oe_n_pi1",
  685. "gmi_dqs_pi2",
  686. "gmi_adv_n_pk0",
  687. "gmi_clk_pk1";
  688. nvidia,function = "nand";
  689. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  690. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  691. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  692. };
  693. gmi_cs2_n_pk3 {
  694. nvidia,pins = "gmi_cs2_n_pk3";
  695. nvidia,function = "rsvd1";
  696. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  697. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  698. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  699. };
  700. gmi_cs3_n_pk4 {
  701. nvidia,pins = "gmi_cs3_n_pk4";
  702. nvidia,function = "nand";
  703. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  704. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  705. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  706. };
  707. gmi_ad10_ph2 {
  708. nvidia,pins = "gmi_ad10_ph2",
  709. "gmi_ad11_ph3",
  710. "gmi_ad14_ph6";
  711. nvidia,function = "nand";
  712. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  713. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  714. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  715. };
  716. gmi_ad13_ph5 {
  717. nvidia,pins = "gmi_ad13_ph5",
  718. "gmi_ad12_ph4",
  719. "gmi_cs7_n_pi6";
  720. nvidia,function = "nand";
  721. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  722. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  723. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  724. };
  725. gmi_rst_n_pi4 {
  726. nvidia,pins = "gmi_rst_n_pi4";
  727. nvidia,function = "gmi";
  728. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  729. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  730. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  731. };
  732. gmi_ad8_ph0 {
  733. nvidia,pins = "gmi_ad8_ph0";
  734. nvidia,function = "pwm0";
  735. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  736. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  737. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  738. };
  739. gmi_ad9_ph1 {
  740. nvidia,pins = "gmi_ad9_ph1";
  741. nvidia,function = "pwm1";
  742. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  743. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  744. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  745. };
  746. gmi_wp_n_pc7 {
  747. nvidia,pins = "gmi_wp_n_pc7";
  748. nvidia,function = "gmi";
  749. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  750. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  751. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  752. };
  753. gmi_cs6_n_pi3 {
  754. nvidia,pins = "gmi_cs6_n_pi3";
  755. nvidia,function = "sata";
  756. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  757. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  758. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  759. };
  760. vi_d4_pl2 {
  761. nvidia,pins = "vi_d4_pl2";
  762. nvidia,function = "vi";
  763. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  764. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  765. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  766. };
  767. vi_d6_pl4 {
  768. nvidia,pins = "vi_d6_pl4";
  769. nvidia,function = "vi";
  770. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  771. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  772. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  773. nvidia,lock = <0>;
  774. nvidia,ioreset = <0>;
  775. };
  776. vi_mclk_pt1 {
  777. nvidia,pins = "vi_mclk_pt1";
  778. nvidia,function = "vi";
  779. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  780. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  781. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  782. };
  783. /* HDMI hot-plug-detect */
  784. hdmi_int_pn7 {
  785. nvidia,pins = "hdmi_int_pn7";
  786. nvidia,function = "hdmi";
  787. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  788. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  789. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  790. };
  791. pu4 {
  792. nvidia,pins = "pu4";
  793. nvidia,function = "pwm1";
  794. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  795. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  796. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  797. };
  798. pu5 {
  799. nvidia,pins = "pu5";
  800. nvidia,function = "pwm2";
  801. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  802. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  803. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  804. };
  805. jtag_rtck_pu7 {
  806. nvidia,pins = "jtag_rtck_pu7";
  807. nvidia,function = "rtck";
  808. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  809. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  810. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  811. };
  812. crt_hsync_pv6 {
  813. nvidia,pins = "crt_hsync_pv6",
  814. "crt_vsync_pv7";
  815. nvidia,function = "crt";
  816. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  817. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  818. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  819. };
  820. clk1_out_pw4 {
  821. nvidia,pins = "clk1_out_pw4";
  822. nvidia,function = "extperiph1";
  823. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  824. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  825. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  826. };
  827. clk2_out_pw5 {
  828. nvidia,pins = "clk2_out_pw5";
  829. nvidia,function = "extperiph2";
  830. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  831. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  832. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  833. };
  834. clk3_out_pee0 {
  835. nvidia,pins = "clk3_out_pee0";
  836. nvidia,function = "extperiph3";
  837. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  838. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  839. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  840. };
  841. sys_clk_req_pz5 {
  842. nvidia,pins = "sys_clk_req_pz5";
  843. nvidia,function = "sysclk";
  844. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  845. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  846. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  847. };
  848. pbb4 {
  849. nvidia,pins = "pbb4";
  850. nvidia,function = "vgp4";
  851. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  852. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  853. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  854. };
  855. pbb5 {
  856. nvidia,pins = "pbb5";
  857. nvidia,function = "vgp5";
  858. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  859. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  860. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  861. };
  862. pbb6 {
  863. nvidia,pins = "pbb6";
  864. nvidia,function = "vgp6";
  865. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  866. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  867. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  868. };
  869. clk1_req_pee2 {
  870. nvidia,pins = "clk1_req_pee2";
  871. nvidia,function = "dap";
  872. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  873. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  874. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  875. };
  876. clk2_req_pcc5 {
  877. nvidia,pins = "clk2_req_pcc5";
  878. nvidia,function = "dap";
  879. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  880. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  881. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  882. };
  883. clk3_req_pee1 {
  884. nvidia,pins = "clk3_req_pee1";
  885. nvidia,function = "dev3";
  886. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  887. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  888. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  889. };
  890. owr {
  891. nvidia,pins = "owr";
  892. nvidia,function = "owr";
  893. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  894. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  895. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  896. };
  897. pv2 {
  898. nvidia,pins = "pv2",
  899. "kb_row5_pr5";
  900. nvidia,function = "owr";
  901. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  902. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  903. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  904. };
  905. pbb3 {
  906. nvidia,pins = "pbb3";
  907. nvidia,function = "vgp3";
  908. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  909. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  910. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  911. };
  912. pbb7 {
  913. nvidia,pins = "pbb7";
  914. nvidia,function = "i2s4";
  915. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  916. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  917. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  918. };
  919. cam_mclk_pcc0 {
  920. nvidia,pins = "cam_mclk_pcc0";
  921. nvidia,function = "vi_alt3";
  922. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  923. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  924. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  925. };
  926. /* GPIO power/drive control */
  927. drive_dap1 {
  928. nvidia,pins = "drive_dap1",
  929. "drive_dap2",
  930. "drive_dbg",
  931. "drive_at5",
  932. "drive_gme",
  933. "drive_ddc",
  934. "drive_ao1",
  935. "drive_uart3";
  936. nvidia,high-speed-mode = <0>;
  937. nvidia,schmitt = <TEGRA_PIN_ENABLE>;
  938. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  939. nvidia,pull-down-strength = <31>;
  940. nvidia,pull-up-strength = <31>;
  941. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  942. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  943. };
  944. drive_sdio1 {
  945. nvidia,pins = "drive_sdio1";
  946. nvidia,high-speed-mode = <0>;
  947. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  948. nvidia,pull-down-strength = <5>;
  949. nvidia,pull-up-strength = <5>;
  950. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
  951. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
  952. };
  953. drive_sdio3 {
  954. nvidia,pins = "drive_sdio3";
  955. nvidia,high-speed-mode = <0>;
  956. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  957. nvidia,pull-down-strength = <46>;
  958. nvidia,pull-up-strength = <42>;
  959. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
  960. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
  961. };
  962. drive_gma {
  963. nvidia,pins = "drive_gma",
  964. "drive_gmb",
  965. "drive_gmc",
  966. "drive_gmd";
  967. nvidia,pull-down-strength = <9>;
  968. nvidia,pull-up-strength = <9>;
  969. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  970. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  971. };
  972. drive_lcd2 {
  973. nvidia,pins = "drive_lcd2";
  974. nvidia,high-speed-mode = <0>;
  975. nvidia,schmitt = <TEGRA_PIN_ENABLE>;
  976. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>;
  977. nvidia,pull-down-strength = <20>;
  978. nvidia,pull-up-strength = <20>;
  979. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  980. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  981. };
  982. };
  983. };
  984. uartb: serial@70006040 {
  985. compatible = "nvidia,tegra30-hsuart";
  986. /delete-property/ reg-shift;
  987. status = "okay";
  988. /* Broadcom GPS BCM47511 */
  989. };
  990. uartc: serial@70006200 {
  991. compatible = "nvidia,tegra30-hsuart";
  992. /delete-property/ reg-shift;
  993. status = "okay";
  994. nvidia,adjust-baud-rates = <0 9600 100>,
  995. <9600 115200 200>,
  996. <1000000 4000000 136>;
  997. /* Azurewave AW-AH663 BCM4330B1 */
  998. bluetooth {
  999. compatible = "brcm,bcm4330-bt";
  1000. max-speed = <4000000>;
  1001. clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  1002. clock-names = "txco";
  1003. interrupt-parent = <&gpio>;
  1004. interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
  1005. interrupt-names = "host-wakeup";
  1006. device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
  1007. shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
  1008. vbat-supply = <&vdd_3v3_sys>;
  1009. vddio-supply = <&vdd_1v8_vio>;
  1010. };
  1011. };
  1012. pwm: pwm@7000a000 {
  1013. status = "okay";
  1014. };
  1015. lcd_ddc: i2c@7000c000 {
  1016. status = "okay";
  1017. clock-frequency = <400000>;
  1018. /* Wolfson Microelectronics WM8903 audio codec */
  1019. wm8903: audio-codec@1a {
  1020. compatible = "wlf,wm8903";
  1021. reg = <0x1a>;
  1022. interrupt-parent = <&gpio>;
  1023. interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_BOTH>;
  1024. gpio-controller;
  1025. #gpio-cells = <2>;
  1026. micdet-cfg = <0>;
  1027. micdet-delay = <100>;
  1028. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  1029. AVDD-supply = <&vdd_1v8_vio>;
  1030. CPVDD-supply = <&vdd_1v8_vio>;
  1031. DBVDD-supply = <&vdd_1v8_vio>;
  1032. DCVDD-supply = <&vdd_1v8_vio>;
  1033. };
  1034. };
  1035. i2c2: i2c@7000c400 {
  1036. status = "okay";
  1037. clock-frequency = <400000>;
  1038. /* Atmel touchscreen */
  1039. touchscreen@4d {
  1040. compatible = "atmel,maxtouch";
  1041. reg = <0x4d>;
  1042. interrupt-parent = <&gpio>;
  1043. interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
  1044. reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
  1045. vdda-supply = <&vdd_3v3_sys>;
  1046. vdd-supply = <&vdd_3v3_sys>;
  1047. };
  1048. };
  1049. i2c3: i2c@7000c500 {
  1050. status = "okay";
  1051. clock-frequency = <400000>;
  1052. light-sensor@44 {
  1053. compatible = "isil,isl29023";
  1054. reg = <0x44>;
  1055. interrupt-parent = <&gpio>;
  1056. interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_LEVEL_HIGH>;
  1057. vcc-supply = <&vdd_3v3_sen>;
  1058. };
  1059. /* AsahiKASEI AK8975 magnetometer sensor */
  1060. magnetometer@c {
  1061. compatible = "asahi-kasei,ak8975";
  1062. reg = <0x0c>;
  1063. vdd-supply = <&vdd_3v3_sen>;
  1064. vid-supply = <&vdd_1v8_vio>;
  1065. mount-matrix = "0", "1", "0",
  1066. "1", "0", "0",
  1067. "0", "0", "-1";
  1068. };
  1069. gyroscope@68 {
  1070. compatible = "invensense,mpu3050";
  1071. reg = <0x68>;
  1072. interrupt-parent = <&gpio>;
  1073. interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
  1074. vdd-supply = <&vdd_3v3_sen>;
  1075. vlogic-supply = <&vdd_1v8_vio>;
  1076. mount-matrix = "0", "1", "0",
  1077. "1", "0", "0",
  1078. "0", "0", "-1";
  1079. /* External I2C interface */
  1080. i2c-gate {
  1081. #address-cells = <1>;
  1082. #size-cells = <0>;
  1083. accelerometer@f {
  1084. compatible = "kionix,kxtf9";
  1085. reg = <0x0f>;
  1086. interrupt-parent = <&gpio>;
  1087. interrupts = <TEGRA_GPIO(L, 1) IRQ_TYPE_EDGE_RISING>;
  1088. vdd-supply = <&vdd_1v8_vio>;
  1089. vddio-supply = <&vdd_1v8_vio>;
  1090. mount-matrix = "-1", "0", "0",
  1091. "0", "1", "0",
  1092. "0", "0", "1";
  1093. };
  1094. };
  1095. };
  1096. };
  1097. hdmi_ddc: i2c@7000c700 {
  1098. status = "okay";
  1099. clock-frequency = <93750>;
  1100. };
  1101. i2c5: i2c@7000d000 {
  1102. status = "okay";
  1103. clock-frequency = <400000>;
  1104. nct72: temperature-sensor@4c {
  1105. compatible = "onnn,nct1008";
  1106. reg = <0x4c>;
  1107. interrupt-parent = <&gpio>;
  1108. interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_EDGE_FALLING>;
  1109. vcc-supply = <&vdd_3v3_sys>;
  1110. #thermal-sensor-cells = <1>;
  1111. };
  1112. /* Texas Instruments TPS659110 PMIC */
  1113. pmic: pmic@2d {
  1114. compatible = "ti,tps65911";
  1115. reg = <0x2d>;
  1116. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  1117. #interrupt-cells = <2>;
  1118. interrupt-controller;
  1119. wakeup-source;
  1120. ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
  1121. ti,system-power-controller;
  1122. ti,sleep-keep-ck32k;
  1123. ti,sleep-enable;
  1124. #gpio-cells = <2>;
  1125. gpio-controller;
  1126. vcc1-supply = <&vdd_5v0_sys>;
  1127. vcc2-supply = <&vdd_5v0_sys>;
  1128. vcc3-supply = <&vdd_1v8_vio>;
  1129. vcc4-supply = <&vdd_1v8_vio>;
  1130. vcc5-supply = <&vdd_5v0_sys>;
  1131. vcc6-supply = <&vddio_1v2_ddr>;
  1132. vcc7-supply = <&vdd_5v0_sys>;
  1133. vccio-supply = <&vdd_5v0_sys>;
  1134. pmic-sleep-hog {
  1135. gpio-hog;
  1136. gpios = <0 GPIO_ACTIVE_HIGH>,
  1137. <2 GPIO_ACTIVE_HIGH>,
  1138. <6 GPIO_ACTIVE_HIGH>,
  1139. <8 GPIO_ACTIVE_HIGH>;
  1140. output-high;
  1141. };
  1142. regulators {
  1143. /* VDD1 is not used by Chagall */
  1144. vddio_1v2_ddr: vdd2 {
  1145. regulator-name = "vddio_1v2_ddr";
  1146. regulator-min-microvolt = <1200000>;
  1147. regulator-max-microvolt = <1200000>;
  1148. regulator-always-on;
  1149. regulator-boot-on;
  1150. };
  1151. vdd_cpu: vddctrl {
  1152. regulator-name = "vdd_cpu,vdd_sys";
  1153. regulator-min-microvolt = <600000>;
  1154. regulator-max-microvolt = <1400000>;
  1155. regulator-coupled-with = <&vdd_core>;
  1156. regulator-coupled-max-spread = <300000>;
  1157. regulator-max-step-microvolt = <100000>;
  1158. regulator-always-on;
  1159. regulator-boot-on;
  1160. ti,regulator-ext-sleep-control = <1>;
  1161. nvidia,tegra-cpu-regulator;
  1162. };
  1163. vdd_1v8_vio: vio {
  1164. regulator-name = "vdd_1v8_gen";
  1165. /* FIXME: eMMC won't work, if set to 1.8 V */
  1166. regulator-min-microvolt = <1500000>;
  1167. regulator-max-microvolt = <3300000>;
  1168. regulator-always-on;
  1169. regulator-boot-on;
  1170. };
  1171. /* eMMC VDD */
  1172. vcore_emmc: ldo1 {
  1173. regulator-name = "vdd_emmc_core";
  1174. regulator-min-microvolt = <1000000>;
  1175. regulator-max-microvolt = <3300000>;
  1176. regulator-always-on;
  1177. };
  1178. /* uSD slot VDD */
  1179. vdd_usd: ldo2 {
  1180. regulator-name = "vdd_usd";
  1181. regulator-min-microvolt = <3200000>;
  1182. regulator-max-microvolt = <3200000>;
  1183. };
  1184. /* uSD slot VDDIO */
  1185. vddio_usd: ldo3 {
  1186. regulator-name = "vddio_usd";
  1187. regulator-min-microvolt = <1900000>;
  1188. regulator-max-microvolt = <3200000>;
  1189. };
  1190. ldo4 {
  1191. regulator-name = "vdd_rtc";
  1192. regulator-min-microvolt = <1200000>;
  1193. regulator-max-microvolt = <1200000>;
  1194. regulator-always-on;
  1195. };
  1196. ldo5 {
  1197. regulator-name = "vdd_1v3_cam_isp";
  1198. regulator-min-microvolt = <1300000>;
  1199. regulator-max-microvolt = <1300000>;
  1200. };
  1201. ldo6 {
  1202. regulator-name = "avdd_dsi_csi,pwrdet_mipi";
  1203. regulator-min-microvolt = <1200000>;
  1204. regulator-max-microvolt = <1200000>;
  1205. };
  1206. ldo7 {
  1207. regulator-name = "vdd_pllm,x,u,a_p_c_s";
  1208. regulator-min-microvolt = <1200000>;
  1209. regulator-max-microvolt = <1200000>;
  1210. regulator-always-on;
  1211. regulator-boot-on;
  1212. ti,regulator-ext-sleep-control = <8>;
  1213. };
  1214. ldo8 {
  1215. regulator-name = "vdd_ddr_hs";
  1216. regulator-min-microvolt = <1000000>;
  1217. regulator-max-microvolt = <1000000>;
  1218. regulator-always-on;
  1219. ti,regulator-ext-sleep-control = <8>;
  1220. };
  1221. };
  1222. };
  1223. vdd_core: core-regulator@60 {
  1224. compatible = "ti,tps62361";
  1225. reg = <0x60>;
  1226. regulator-name = "tps62361-vout";
  1227. regulator-min-microvolt = <500000>;
  1228. regulator-max-microvolt = <1770000>;
  1229. regulator-coupled-with = <&vdd_cpu>;
  1230. regulator-coupled-max-spread = <300000>;
  1231. regulator-max-step-microvolt = <100000>;
  1232. regulator-boot-on;
  1233. regulator-always-on;
  1234. ti,enable-vout-discharge;
  1235. ti,vsel0-state-high;
  1236. ti,vsel1-state-high;
  1237. nvidia,tegra-core-regulator;
  1238. };
  1239. };
  1240. vdd_5v0_sys: regulator-5v {
  1241. compatible = "regulator-fixed";
  1242. regulator-name = "vdd_5v0_sys";
  1243. regulator-min-microvolt = <5000000>;
  1244. regulator-max-microvolt = <5000000>;
  1245. regulator-always-on;
  1246. regulator-boot-on;
  1247. };
  1248. vdd_3v3_sys: regulator-3v {
  1249. compatible = "regulator-fixed";
  1250. regulator-name = "vdd_3v3_sys";
  1251. regulator-min-microvolt = <3300000>;
  1252. regulator-max-microvolt = <3300000>;
  1253. regulator-always-on;
  1254. regulator-boot-on;
  1255. };
  1256. vdd_pnl: regulator-panel {
  1257. compatible = "regulator-fixed";
  1258. regulator-name = "vdd_panel";
  1259. regulator-min-microvolt = <3300000>;
  1260. regulator-max-microvolt = <3300000>;
  1261. regulator-enable-ramp-delay = <300000>;
  1262. gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
  1263. enable-active-high;
  1264. vin-supply = <&vdd_3v3_sys>;
  1265. };
  1266. vdd_3v3_sen: regulator-sensors {
  1267. compatible = "regulator-fixed";
  1268. regulator-name = "sen_3v3_en";
  1269. regulator-min-microvolt = <3300000>;
  1270. regulator-max-microvolt = <3300000>;
  1271. gpio = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>;
  1272. enable-active-high;
  1273. vin-supply = <&vdd_3v3_sys>;
  1274. };
  1275. vdd_5v0_bl: regulator-bl {
  1276. compatible = "regulator-fixed";
  1277. regulator-name = "vdd_5v0_bl";
  1278. regulator-min-microvolt = <5000000>;
  1279. regulator-max-microvolt = <5000000>;
  1280. regulator-boot-on;
  1281. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  1282. enable-active-high;
  1283. vin-supply = <&vdd_5v0_sys>;
  1284. };
  1285. hdmi_5v0_sys: regulator-hdmi {
  1286. compatible = "regulator-fixed";
  1287. regulator-name = "hdmi_5v0_sys";
  1288. regulator-min-microvolt = <5000000>;
  1289. regulator-max-microvolt = <5000000>;
  1290. gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  1291. enable-active-high;
  1292. vin-supply = <&vdd_5v0_sys>;
  1293. };
  1294. vdd_vbus_usb1: regulator-usb1 {
  1295. compatible = "regulator-fixed";
  1296. regulator-name = "vdd_vbus_micro_usb";
  1297. regulator-min-microvolt = <5000000>;
  1298. regulator-max-microvolt = <5000000>;
  1299. gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>;
  1300. enable-active-high;
  1301. vin-supply = <&vdd_5v0_sys>;
  1302. };
  1303. vdd_vbus_usb3: regulator-usb3 {
  1304. compatible = "regulator-fixed";
  1305. regulator-name = "vdd_vbus_typea_usb";
  1306. regulator-min-microvolt = <5000000>;
  1307. regulator-max-microvolt = <5000000>;
  1308. gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>;
  1309. enable-active-high;
  1310. vin-supply = <&vdd_5v0_sys>;
  1311. };
  1312. pmc@7000e400 {
  1313. status = "okay";
  1314. nvidia,invert-interrupt;
  1315. nvidia,suspend-mode = <2>;
  1316. nvidia,cpu-pwr-good-time = <2000>;
  1317. nvidia,cpu-pwr-off-time = <200>;
  1318. nvidia,core-pwr-good-time = <3845 3845>;
  1319. nvidia,core-pwr-off-time = <0>;
  1320. nvidia,core-power-req-active-high;
  1321. nvidia,sys-clock-req-active-high;
  1322. core-supply = <&vdd_core>;
  1323. /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */
  1324. i2c-thermtrip {
  1325. nvidia,i2c-controller-id = <4>;
  1326. nvidia,bus-addr = <0x2d>;
  1327. nvidia,reg-addr = <0x3f>;
  1328. nvidia,reg-data = <0x81>;
  1329. };
  1330. };
  1331. memory-controller@7000f000 {
  1332. emc-timings-0 {
  1333. /* SAMSUNG K4P8G304EB FGC1 */
  1334. nvidia,ram-code = <0>;
  1335. timing-25500000 {
  1336. clock-frequency = <25500000>;
  1337. nvidia,emem-configuration = < 0x00020001 0xc0000010
  1338. 0x00000001 0x00000001 0x00000002 0x00000000
  1339. 0x00000003 0x00000001 0x00000002 0x00000004
  1340. 0x00000001 0x00000000 0x00000002 0x00000002
  1341. 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
  1342. };
  1343. timing-51000000 {
  1344. clock-frequency = <51000000>;
  1345. nvidia,emem-configuration = < 0x00010001 0xc0000010
  1346. 0x00000001 0x00000001 0x00000002 0x00000000
  1347. 0x00000003 0x00000001 0x00000002 0x00000004
  1348. 0x00000001 0x00000000 0x00000002 0x00000002
  1349. 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
  1350. };
  1351. timing-102000000 {
  1352. clock-frequency = <102000000>;
  1353. nvidia,emem-configuration = < 0x00000001 0xc0000018
  1354. 0x00000001 0x00000001 0x00000003 0x00000001
  1355. 0x00000003 0x00000001 0x00000002 0x00000004
  1356. 0x00000001 0x00000000 0x00000002 0x00000002
  1357. 0x02020001 0x00060403 0x72430504 0x001f0000 >;
  1358. };
  1359. timing-204000000 {
  1360. clock-frequency = <204000000>;
  1361. nvidia,emem-configuration = < 0x00000003 0xc0000025
  1362. 0x00000001 0x00000001 0x00000006 0x00000003
  1363. 0x00000005 0x00000001 0x00000002 0x00000004
  1364. 0x00000001 0x00000000 0x00000003 0x00000002
  1365. 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
  1366. };
  1367. timing-400000000 {
  1368. clock-frequency = <400000000>;
  1369. nvidia,emem-configuration = < 0x00000006 0xc0000048
  1370. 0x00000002 0x00000003 0x0000000c 0x00000007
  1371. 0x00000009 0x00000001 0x00000002 0x00000006
  1372. 0x00000001 0x00000000 0x00000004 0x00000004
  1373. 0x04040001 0x000d090c 0x7026120d 0x001f0000 >;
  1374. };
  1375. };
  1376. emc-timings-1 {
  1377. /* ELPIDA EDB8132B2MA 8D_F */
  1378. nvidia,ram-code = <1>;
  1379. timing-25500000 {
  1380. clock-frequency = <25500000>;
  1381. nvidia,emem-configuration = < 0x00020001 0xc0000010
  1382. 0x00000001 0x00000001 0x00000002 0x00000000
  1383. 0x00000003 0x00000001 0x00000002 0x00000004
  1384. 0x00000001 0x00000000 0x00000002 0x00000002
  1385. 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
  1386. };
  1387. timing-51000000 {
  1388. clock-frequency = <51000000>;
  1389. nvidia,emem-configuration = < 0x00010001 0xc0000010
  1390. 0x00000001 0x00000001 0x00000002 0x00000000
  1391. 0x00000003 0x00000001 0x00000002 0x00000004
  1392. 0x00000001 0x00000000 0x00000002 0x00000002
  1393. 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
  1394. };
  1395. timing-102000000 {
  1396. clock-frequency = <102000000>;
  1397. nvidia,emem-configuration = < 0x00000001 0xc0000018
  1398. 0x00000001 0x00000001 0x00000003 0x00000001
  1399. 0x00000003 0x00000001 0x00000002 0x00000004
  1400. 0x00000001 0x00000000 0x00000002 0x00000002
  1401. 0x02020001 0x00060403 0x72430504 0x001f0000 >;
  1402. };
  1403. timing-204000000 {
  1404. clock-frequency = <204000000>;
  1405. nvidia,emem-configuration = < 0x00000003 0xc0000025
  1406. 0x00000001 0x00000001 0x00000006 0x00000003
  1407. 0x00000005 0x00000001 0x00000002 0x00000004
  1408. 0x00000001 0x00000000 0x00000003 0x00000002
  1409. 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
  1410. };
  1411. timing-400000000 {
  1412. clock-frequency = <400000000>;
  1413. nvidia,emem-configuration = < 0x00000006 0xc0000048
  1414. 0x00000002 0x00000003 0x0000000c 0x00000007
  1415. 0x00000009 0x00000001 0x00000002 0x00000006
  1416. 0x00000001 0x00000000 0x00000004 0x00000004
  1417. 0x04040001 0x000d090c 0x7026120d 0x001f0000 >;
  1418. };
  1419. };
  1420. emc-timings-2 {
  1421. /* SAMSUNG K4P8G304EB FGC2 */
  1422. nvidia,ram-code = <2>;
  1423. timing-25500000 {
  1424. clock-frequency = <25500000>;
  1425. nvidia,emem-configuration = < 0x00020001 0xc0000010
  1426. 0x00000001 0x00000001 0x00000002 0x00000000
  1427. 0x00000003 0x00000001 0x00000002 0x00000004
  1428. 0x00000001 0x00000000 0x00000002 0x00000002
  1429. 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
  1430. };
  1431. timing-51000000 {
  1432. clock-frequency = <51000000>;
  1433. nvidia,emem-configuration = < 0x00010001 0xc0000010
  1434. 0x00000001 0x00000001 0x00000002 0x00000000
  1435. 0x00000003 0x00000001 0x00000002 0x00000004
  1436. 0x00000001 0x00000000 0x00000002 0x00000002
  1437. 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
  1438. };
  1439. timing-102000000 {
  1440. clock-frequency = <102000000>;
  1441. nvidia,emem-configuration = < 0x00000001 0xc0000018
  1442. 0x00000001 0x00000001 0x00000003 0x00000001
  1443. 0x00000003 0x00000001 0x00000002 0x00000004
  1444. 0x00000001 0x00000000 0x00000002 0x00000002
  1445. 0x02020001 0x00060403 0x72430504 0x001f0000 >;
  1446. };
  1447. timing-204000000 {
  1448. clock-frequency = <204000000>;
  1449. nvidia,emem-configuration = < 0x00000003 0xc0000025
  1450. 0x00000001 0x00000001 0x00000006 0x00000003
  1451. 0x00000005 0x00000001 0x00000002 0x00000004
  1452. 0x00000001 0x00000000 0x00000003 0x00000002
  1453. 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
  1454. };
  1455. timing-533000000 {
  1456. clock-frequency = <533000000>;
  1457. nvidia,emem-configuration = < 0x00000008 0xc0000060
  1458. 0x00000003 0x00000004 0x00000010 0x0000000a
  1459. 0x0000000d 0x00000002 0x00000002 0x00000008
  1460. 0x00000002 0x00000000 0x00000004 0x00000005
  1461. 0x05040002 0x00110b10 0x70281811 0x001f0000 >;
  1462. };
  1463. };
  1464. emc-timings-3 {
  1465. /* HYNIX H9TCNNN8JDMMPR NGM */
  1466. nvidia,ram-code = <3>;
  1467. timing-25500000 {
  1468. clock-frequency = <25500000>;
  1469. nvidia,emem-configuration = < 0x00020001 0xc0000010
  1470. 0x00000001 0x00000001 0x00000002 0x00000000
  1471. 0x00000003 0x00000001 0x00000002 0x00000004
  1472. 0x00000001 0x00000000 0x00000002 0x00000002
  1473. 0x02020001 0x00060402 0x73e30303 0x001f0000 >;
  1474. };
  1475. timing-51000000 {
  1476. clock-frequency = <51000000>;
  1477. nvidia,emem-configuration = < 0x00010001 0xc0000010
  1478. 0x00000001 0x00000001 0x00000002 0x00000000
  1479. 0x00000003 0x00000001 0x00000002 0x00000004
  1480. 0x00000001 0x00000000 0x00000002 0x00000002
  1481. 0x02020001 0x00060402 0x72c30303 0x001f0000 >;
  1482. };
  1483. timing-102000000 {
  1484. clock-frequency = <102000000>;
  1485. nvidia,emem-configuration = < 0x00000001 0xc0000018
  1486. 0x00000001 0x00000001 0x00000003 0x00000001
  1487. 0x00000003 0x00000001 0x00000002 0x00000004
  1488. 0x00000001 0x00000000 0x00000002 0x00000002
  1489. 0x02020001 0x00060403 0x72430504 0x001f0000 >;
  1490. };
  1491. timing-204000000 {
  1492. clock-frequency = <204000000>;
  1493. nvidia,emem-configuration = < 0x00000003 0xc0000025
  1494. 0x00000001 0x00000001 0x00000006 0x00000003
  1495. 0x00000005 0x00000001 0x00000002 0x00000004
  1496. 0x00000001 0x00000000 0x00000003 0x00000002
  1497. 0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
  1498. };
  1499. timing-533000000 {
  1500. clock-frequency = <533000000>;
  1501. nvidia,emem-configuration = < 0x00000008 0xc0000060
  1502. 0x00000003 0x00000004 0x00000010 0x0000000a
  1503. 0x0000000d 0x00000002 0x00000002 0x00000008
  1504. 0x00000002 0x00000000 0x00000004 0x00000005
  1505. 0x05040002 0x00110b10 0x70281811 0x001f0000 >;
  1506. };
  1507. };
  1508. };
  1509. memory-controller@7000f400 {
  1510. emc-timings-0 {
  1511. /* SAMSUNG K4P8G304EB FGC1 */
  1512. nvidia,ram-code = <0>;
  1513. timing-25500000 {
  1514. clock-frequency = <25500000>;
  1515. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1516. nvidia,emc-mode-1 = <0x00010022>;
  1517. nvidia,emc-mode-2 = <0x00020001>;
  1518. nvidia,emc-mode-reset = <0x00000000>;
  1519. nvidia,emc-zcal-cnt-long = <0x00000009>;
  1520. nvidia,emc-cfg-dyn-self-ref;
  1521. nvidia,emc-cfg-periodic-qrst;
  1522. nvidia,emc-configuration = < 0x00000001
  1523. 0x00000003 0x00000002 0x00000002 0x00000004
  1524. 0x00000004 0x00000001 0x00000005 0x00000002
  1525. 0x00000002 0x00000001 0x00000001 0x00000000
  1526. 0x00000001 0x00000003 0x00000001 0x0000000b
  1527. 0x00000009 0x00000060 0x00000000 0x00000018
  1528. 0x00000001 0x00000001 0x00000002 0x00000000
  1529. 0x00000001 0x00000007 0x00000004 0x00000004
  1530. 0x00000003 0x00000008 0x00000004 0x00000004
  1531. 0x00000002 0x0000006b 0x00000004 0x00000004
  1532. 0x00000000 0x00000000 0x00004282 0x007800a4
  1533. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  1534. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  1535. 0x000fc000 0x00000000 0x00000000 0x00000000
  1536. 0x00000000 0x00000000 0x00000000 0x00000000
  1537. 0x00000000 0x00000000 0x00000000 0x00000000
  1538. 0x00000000 0x00000000 0x00000000 0x00000000
  1539. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  1540. 0x000fc000 0x00100220 0x0800201c 0x00000000
  1541. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1542. 0x08000068 0x08000000 0x00000802 0x00064000
  1543. 0x0000000a 0x00090009 0xa0f10000 0x00000000
  1544. 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
  1545. };
  1546. timing-51000000 {
  1547. clock-frequency = <51000000>;
  1548. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1549. nvidia,emc-mode-1 = <0x00010022>;
  1550. nvidia,emc-mode-2 = <0x00020001>;
  1551. nvidia,emc-mode-reset = <0x00000000>;
  1552. nvidia,emc-zcal-cnt-long = <0x00000009>;
  1553. nvidia,emc-cfg-dyn-self-ref;
  1554. nvidia,emc-cfg-periodic-qrst;
  1555. nvidia,emc-configuration = < 0x00000003
  1556. 0x00000006 0x00000002 0x00000002 0x00000004
  1557. 0x00000004 0x00000001 0x00000005 0x00000002
  1558. 0x00000002 0x00000001 0x00000001 0x00000000
  1559. 0x00000001 0x00000003 0x00000001 0x0000000b
  1560. 0x00000009 0x000000c0 0x00000000 0x00000030
  1561. 0x00000001 0x00000001 0x00000002 0x00000000
  1562. 0x00000001 0x00000007 0x00000008 0x00000008
  1563. 0x00000003 0x00000008 0x00000004 0x00000004
  1564. 0x00000002 0x000000d5 0x00000004 0x00000004
  1565. 0x00000000 0x00000000 0x00004282 0x007800a4
  1566. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  1567. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  1568. 0x000fc000 0x00000000 0x00000000 0x00000000
  1569. 0x00000000 0x00000000 0x00000000 0x00000000
  1570. 0x00000000 0x00000000 0x00000000 0x00000000
  1571. 0x00000000 0x00000000 0x00000000 0x00000000
  1572. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  1573. 0x000fc000 0x00100220 0x0800201c 0x00000000
  1574. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1575. 0x08000068 0x08000000 0x00000802 0x00064000
  1576. 0x00000013 0x00090009 0xa0f10000 0x00000000
  1577. 0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
  1578. };
  1579. timing-102000000 {
  1580. clock-frequency = <102000000>;
  1581. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1582. nvidia,emc-mode-1 = <0x00010022>;
  1583. nvidia,emc-mode-2 = <0x00020001>;
  1584. nvidia,emc-mode-reset = <0x00000000>;
  1585. nvidia,emc-zcal-cnt-long = <0x0000000a>;
  1586. nvidia,emc-cfg-dyn-self-ref;
  1587. nvidia,emc-cfg-periodic-qrst;
  1588. nvidia,emc-configuration = < 0x00000006
  1589. 0x0000000d 0x00000004 0x00000002 0x00000004
  1590. 0x00000004 0x00000001 0x00000005 0x00000002
  1591. 0x00000002 0x00000001 0x00000001 0x00000000
  1592. 0x00000001 0x00000003 0x00000001 0x0000000b
  1593. 0x00000009 0x00000181 0x00000000 0x00000060
  1594. 0x00000001 0x00000001 0x00000002 0x00000000
  1595. 0x00000001 0x00000007 0x0000000f 0x0000000f
  1596. 0x00000003 0x00000008 0x00000004 0x00000004
  1597. 0x00000002 0x000001a9 0x00000004 0x00000004
  1598. 0x00000000 0x00000000 0x00004282 0x007800a4
  1599. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  1600. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  1601. 0x000fc000 0x00000000 0x00000000 0x00000000
  1602. 0x00000000 0x00000000 0x00000000 0x00000000
  1603. 0x00000000 0x00000000 0x00000000 0x00000000
  1604. 0x00000000 0x00000000 0x00000000 0x00000000
  1605. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  1606. 0x000fc000 0x00100220 0x0800201c 0x00000000
  1607. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1608. 0x08000068 0x08000000 0x00000802 0x00064000
  1609. 0x00000025 0x00090009 0xa0f10000 0x00000000
  1610. 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
  1611. };
  1612. timing-204000000 {
  1613. clock-frequency = <204000000>;
  1614. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1615. nvidia,emc-mode-1 = <0x00010042>;
  1616. nvidia,emc-mode-2 = <0x00020001>;
  1617. nvidia,emc-mode-reset = <0x00000000>;
  1618. nvidia,emc-zcal-cnt-long = <0x00000013>;
  1619. nvidia,emc-cfg-dyn-self-ref;
  1620. nvidia,emc-cfg-periodic-qrst;
  1621. nvidia,emc-configuration = < 0x0000000c
  1622. 0x0000001a 0x00000008 0x00000003 0x00000005
  1623. 0x00000004 0x00000001 0x00000006 0x00000003
  1624. 0x00000003 0x00000002 0x00000002 0x00000000
  1625. 0x00000001 0x00000003 0x00000001 0x0000000c
  1626. 0x0000000a 0x00000303 0x00000000 0x000000c0
  1627. 0x00000001 0x00000001 0x00000003 0x00000000
  1628. 0x00000001 0x00000007 0x0000001d 0x0000001d
  1629. 0x00000004 0x0000000b 0x00000005 0x00000004
  1630. 0x00000002 0x00000351 0x00000004 0x00000006
  1631. 0x00000000 0x00000000 0x00004282 0x004400a4
  1632. 0x00008000 0x00080000 0x00080000 0x00080000
  1633. 0x00080000 0x00080000 0x00080000 0x00080000
  1634. 0x00080000 0x00000000 0x00000000 0x00000000
  1635. 0x00000000 0x00000000 0x00000000 0x00000000
  1636. 0x00000000 0x00000000 0x00000000 0x00000000
  1637. 0x00000000 0x00000000 0x00000000 0x00000000
  1638. 0x00000000 0x00080000 0x00080000 0x00080000
  1639. 0x00080000 0x000e0220 0x0800201c 0x00000000
  1640. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1641. 0x08000068 0x08000000 0x00000802 0x00064000
  1642. 0x0000004a 0x00090009 0xa0f10000 0x00000000
  1643. 0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
  1644. };
  1645. timing-400000000 {
  1646. clock-frequency = <400000000>;
  1647. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1648. nvidia,emc-mode-1 = <0x00010082>;
  1649. nvidia,emc-mode-2 = <0x00020004>;
  1650. nvidia,emc-mode-reset = <0x00000000>;
  1651. nvidia,emc-zcal-cnt-long = <0x00000024>;
  1652. nvidia,emc-cfg-periodic-qrst;
  1653. nvidia,emc-configuration = < 0x00000017
  1654. 0x00000033 0x00000010 0x00000007 0x00000007
  1655. 0x00000007 0x00000002 0x0000000a 0x00000007
  1656. 0x00000007 0x00000003 0x00000002 0x00000000
  1657. 0x00000003 0x00000007 0x00000004 0x0000000d
  1658. 0x0000000e 0x000005e9 0x00000000 0x0000017a
  1659. 0x00000002 0x00000002 0x00000007 0x00000000
  1660. 0x00000001 0x0000000c 0x00000038 0x00000038
  1661. 0x00000006 0x00000014 0x00000009 0x00000004
  1662. 0x00000002 0x00000680 0x00000000 0x00000006
  1663. 0x00000000 0x00000000 0x00006282 0x001d0084
  1664. 0x00008000 0x00034000 0x00034000 0x00034000
  1665. 0x00034000 0x00034000 0x00034000 0x00034000
  1666. 0x00034000 0x00000000 0x00000000 0x00000000
  1667. 0x00000000 0x00000000 0x00000000 0x00000000
  1668. 0x00000000 0x00000000 0x00000000 0x00000000
  1669. 0x00000000 0x00000000 0x00000000 0x00000000
  1670. 0x00000000 0x00038000 0x00038000 0x00038000
  1671. 0x00038000 0x00080220 0x0800003d 0x00000000
  1672. 0x77ffc004 0x01f1f408 0x00000000 0x00000007
  1673. 0x08000068 0x08000000 0x00000802 0x00064000
  1674. 0x00000090 0x000c000c 0xa0f10404 0x00000000
  1675. 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >;
  1676. };
  1677. };
  1678. emc-timings-1 {
  1679. /* ELPIDA EDB8132B2MA 8D_F */
  1680. nvidia,ram-code = <1>;
  1681. timing-25500000 {
  1682. clock-frequency = <25500000>;
  1683. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1684. nvidia,emc-mode-1 = <0x00010022>;
  1685. nvidia,emc-mode-2 = <0x00020001>;
  1686. nvidia,emc-mode-reset = <0x00000000>;
  1687. nvidia,emc-zcal-cnt-long = <0x00000009>;
  1688. nvidia,emc-cfg-dyn-self-ref;
  1689. nvidia,emc-cfg-periodic-qrst;
  1690. nvidia,emc-configuration = < 0x00000001
  1691. 0x00000003 0x00000002 0x00000002 0x00000004
  1692. 0x00000004 0x00000001 0x00000005 0x00000002
  1693. 0x00000002 0x00000001 0x00000001 0x00000000
  1694. 0x00000001 0x00000003 0x00000001 0x0000000b
  1695. 0x0000000a 0x00000060 0x00000000 0x00000018
  1696. 0x00000001 0x00000001 0x00000002 0x00000000
  1697. 0x00000001 0x00000007 0x00000004 0x00000004
  1698. 0x00000003 0x00000008 0x00000004 0x00000004
  1699. 0x00000002 0x0000006b 0x00000004 0x00000004
  1700. 0x00000000 0x00000000 0x00004282 0x007800a4
  1701. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  1702. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  1703. 0x000fc000 0x00000000 0x00000000 0x00000000
  1704. 0x00000000 0x00000000 0x00000000 0x00000000
  1705. 0x00000000 0x00000000 0x00000000 0x00000000
  1706. 0x00000000 0x00000000 0x00000000 0x00000000
  1707. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  1708. 0x000fc000 0x00100220 0x0800201c 0x00000000
  1709. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1710. 0x08000068 0x08000000 0x00000802 0x00064000
  1711. 0x0000000a 0x00090009 0xa0f10000 0x00000000
  1712. 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
  1713. };
  1714. timing-51000000 {
  1715. clock-frequency = <51000000>;
  1716. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1717. nvidia,emc-mode-1 = <0x00010022>;
  1718. nvidia,emc-mode-2 = <0x00020001>;
  1719. nvidia,emc-mode-reset = <0x00000000>;
  1720. nvidia,emc-zcal-cnt-long = <0x00000009>;
  1721. nvidia,emc-cfg-dyn-self-ref;
  1722. nvidia,emc-cfg-periodic-qrst;
  1723. nvidia,emc-configuration = < 0x00000003
  1724. 0x00000006 0x00000002 0x00000002 0x00000004
  1725. 0x00000004 0x00000001 0x00000005 0x00000002
  1726. 0x00000002 0x00000001 0x00000001 0x00000000
  1727. 0x00000001 0x00000003 0x00000001 0x0000000b
  1728. 0x0000000a 0x000000c0 0x00000000 0x00000030
  1729. 0x00000001 0x00000001 0x00000002 0x00000000
  1730. 0x00000001 0x00000007 0x00000008 0x00000008
  1731. 0x00000003 0x00000008 0x00000004 0x00000004
  1732. 0x00000002 0x000000d5 0x00000004 0x00000004
  1733. 0x00000000 0x00000000 0x00004282 0x007800a4
  1734. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  1735. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  1736. 0x000fc000 0x00000000 0x00000000 0x00000000
  1737. 0x00000000 0x00000000 0x00000000 0x00000000
  1738. 0x00000000 0x00000000 0x00000000 0x00000000
  1739. 0x00000000 0x00000000 0x00000000 0x00000000
  1740. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  1741. 0x000fc000 0x00100220 0x0800201c 0x00000000
  1742. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1743. 0x08000068 0x08000000 0x00000802 0x00064000
  1744. 0x00000013 0x00090009 0xa0f10000 0x00000000
  1745. 0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
  1746. };
  1747. timing-102000000 {
  1748. clock-frequency = <102000000>;
  1749. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1750. nvidia,emc-mode-1 = <0x00010022>;
  1751. nvidia,emc-mode-2 = <0x00020001>;
  1752. nvidia,emc-mode-reset = <0x00000000>;
  1753. nvidia,emc-zcal-cnt-long = <0x0000000a>;
  1754. nvidia,emc-cfg-dyn-self-ref;
  1755. nvidia,emc-cfg-periodic-qrst;
  1756. nvidia,emc-configuration = < 0x00000006
  1757. 0x0000000d 0x00000004 0x00000002 0x00000004
  1758. 0x00000004 0x00000001 0x00000005 0x00000002
  1759. 0x00000002 0x00000001 0x00000001 0x00000000
  1760. 0x00000001 0x00000003 0x00000001 0x0000000b
  1761. 0x0000000a 0x00000181 0x00000000 0x00000060
  1762. 0x00000001 0x00000001 0x00000002 0x00000000
  1763. 0x00000001 0x00000007 0x0000000f 0x0000000f
  1764. 0x00000003 0x00000008 0x00000004 0x00000004
  1765. 0x00000002 0x000001a9 0x00000004 0x00000004
  1766. 0x00000000 0x00000000 0x00004282 0x007800a4
  1767. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  1768. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  1769. 0x000fc000 0x00000000 0x00000000 0x00000000
  1770. 0x00000000 0x00000000 0x00000000 0x00000000
  1771. 0x00000000 0x00000000 0x00000000 0x00000000
  1772. 0x00000000 0x00000000 0x00000000 0x00000000
  1773. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  1774. 0x000fc000 0x00100220 0x0800201c 0x00000000
  1775. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1776. 0x08000068 0x08000000 0x00000802 0x00064000
  1777. 0x00000025 0x00090009 0xa0f10000 0x00000000
  1778. 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
  1779. };
  1780. timing-204000000 {
  1781. clock-frequency = <204000000>;
  1782. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1783. nvidia,emc-mode-1 = <0x00010042>;
  1784. nvidia,emc-mode-2 = <0x00020001>;
  1785. nvidia,emc-mode-reset = <0x00000000>;
  1786. nvidia,emc-zcal-cnt-long = <0x00000013>;
  1787. nvidia,emc-cfg-dyn-self-ref;
  1788. nvidia,emc-cfg-periodic-qrst;
  1789. nvidia,emc-configuration = < 0x0000000c
  1790. 0x0000001a 0x00000008 0x00000003 0x00000005
  1791. 0x00000004 0x00000001 0x00000006 0x00000003
  1792. 0x00000003 0x00000002 0x00000002 0x00000000
  1793. 0x00000001 0x00000003 0x00000001 0x0000000c
  1794. 0x0000000a 0x00000303 0x00000000 0x000000c0
  1795. 0x00000001 0x00000001 0x00000003 0x00000000
  1796. 0x00000001 0x00000007 0x0000001d 0x0000001d
  1797. 0x00000004 0x0000000b 0x00000005 0x00000004
  1798. 0x00000002 0x00000351 0x00000004 0x00000006
  1799. 0x00000000 0x00000000 0x00004282 0x004400a4
  1800. 0x00008000 0x00070000 0x00070000 0x00070000
  1801. 0x00070000 0x00070000 0x00070000 0x00070000
  1802. 0x00070000 0x00000000 0x00000000 0x00000000
  1803. 0x00000000 0x00000000 0x00000000 0x00000000
  1804. 0x00000000 0x00000000 0x00000000 0x00000000
  1805. 0x00000000 0x00000000 0x00000000 0x00000000
  1806. 0x00000000 0x00080000 0x00080000 0x00080000
  1807. 0x00080000 0x000e0220 0x0800201c 0x00000000
  1808. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1809. 0x08000068 0x08000000 0x00000802 0x00064000
  1810. 0x0000004a 0x00090009 0xa0f10000 0x00000000
  1811. 0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
  1812. };
  1813. timing-400000000 {
  1814. clock-frequency = <400000000>;
  1815. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1816. nvidia,emc-mode-1 = <0x00010082>;
  1817. nvidia,emc-mode-2 = <0x00020004>;
  1818. nvidia,emc-mode-reset = <0x00000000>;
  1819. nvidia,emc-zcal-cnt-long = <0x00000024>;
  1820. nvidia,emc-cfg-periodic-qrst;
  1821. nvidia,emc-configuration = < 0x00000017
  1822. 0x00000033 0x00000010 0x00000007 0x00000007
  1823. 0x00000007 0x00000002 0x0000000a 0x00000007
  1824. 0x00000007 0x00000003 0x00000002 0x00000000
  1825. 0x00000003 0x00000007 0x00000004 0x0000000d
  1826. 0x0000000e 0x000005e9 0x00000000 0x0000017a
  1827. 0x00000002 0x00000002 0x00000007 0x00000000
  1828. 0x00000001 0x0000000c 0x00000038 0x00000038
  1829. 0x00000006 0x00000014 0x00000009 0x00000004
  1830. 0x00000002 0x00000680 0x00000000 0x00000004
  1831. 0x00000000 0x00000000 0x00006282 0x001d0084
  1832. 0x00008000 0x00034000 0x00034000 0x00034000
  1833. 0x00034000 0x00034000 0x00034000 0x00034000
  1834. 0x00034000 0x00000000 0x00000000 0x00000000
  1835. 0x00000000 0x00000000 0x00000000 0x00000000
  1836. 0x00000000 0x00000000 0x00000000 0x00000000
  1837. 0x00000000 0x00000000 0x00000000 0x00000000
  1838. 0x00000000 0x00048000 0x00048000 0x00048000
  1839. 0x00048000 0x00060220 0x0800003d 0x00000000
  1840. 0x77ffc004 0x01f1f408 0x00000000 0x00000007
  1841. 0x08000068 0x08000000 0x00000802 0x00064000
  1842. 0x00000090 0x000c000c 0xa0f10000 0x00000000
  1843. 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >;
  1844. };
  1845. };
  1846. emc-timings-2 {
  1847. /* SAMSUNG K4P8G304EB FGC2 */
  1848. nvidia,ram-code = <2>;
  1849. timing-25500000 {
  1850. clock-frequency = <25500000>;
  1851. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1852. nvidia,emc-mode-1 = <0x00010022>;
  1853. nvidia,emc-mode-2 = <0x00020001>;
  1854. nvidia,emc-mode-reset = <0x00000000>;
  1855. nvidia,emc-zcal-cnt-long = <0x00000009>;
  1856. nvidia,emc-cfg-dyn-self-ref;
  1857. nvidia,emc-cfg-periodic-qrst;
  1858. nvidia,emc-configuration = < 0x00000001
  1859. 0x00000003 0x00000002 0x00000002 0x00000004
  1860. 0x00000004 0x00000001 0x00000005 0x00000002
  1861. 0x00000002 0x00000001 0x00000001 0x00000000
  1862. 0x00000001 0x00000003 0x00000001 0x0000000b
  1863. 0x0000000a 0x00000060 0x00000000 0x00000018
  1864. 0x00000001 0x00000001 0x00000002 0x00000000
  1865. 0x00000001 0x00000007 0x00000004 0x00000004
  1866. 0x00000003 0x00000008 0x00000004 0x00000004
  1867. 0x00000002 0x0000006b 0x00000004 0x00000004
  1868. 0x00000000 0x00000000 0x00004282 0x007800a4
  1869. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  1870. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  1871. 0x000fc000 0x00000000 0x00000000 0x00000000
  1872. 0x00000000 0x00000000 0x00000000 0x00000000
  1873. 0x00000000 0x00000000 0x00000000 0x00000000
  1874. 0x00000000 0x00000000 0x00000000 0x00000000
  1875. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  1876. 0x000fc000 0x00100220 0x0800201c 0x00000000
  1877. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1878. 0x08000068 0x08000000 0x00000802 0x00064000
  1879. 0x0000000a 0x00090009 0xa0f10000 0x00000000
  1880. 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
  1881. };
  1882. timing-51000000 {
  1883. clock-frequency = <51000000>;
  1884. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1885. nvidia,emc-mode-1 = <0x00010022>;
  1886. nvidia,emc-mode-2 = <0x00020001>;
  1887. nvidia,emc-mode-reset = <0x00000000>;
  1888. nvidia,emc-zcal-cnt-long = <0x00000009>;
  1889. nvidia,emc-cfg-dyn-self-ref;
  1890. nvidia,emc-cfg-periodic-qrst;
  1891. nvidia,emc-configuration = < 0x00000003
  1892. 0x00000006 0x00000002 0x00000002 0x00000004
  1893. 0x00000004 0x00000001 0x00000005 0x00000002
  1894. 0x00000002 0x00000001 0x00000001 0x00000000
  1895. 0x00000001 0x00000003 0x00000001 0x0000000b
  1896. 0x0000000a 0x000000c0 0x00000000 0x00000030
  1897. 0x00000001 0x00000001 0x00000002 0x00000000
  1898. 0x00000001 0x00000007 0x00000008 0x00000008
  1899. 0x00000003 0x00000008 0x00000004 0x00000004
  1900. 0x00000002 0x000000d5 0x00000004 0x00000004
  1901. 0x00000000 0x00000000 0x00004282 0x007800a4
  1902. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  1903. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  1904. 0x000fc000 0x00000000 0x00000000 0x00000000
  1905. 0x00000000 0x00000000 0x00000000 0x00000000
  1906. 0x00000000 0x00000000 0x00000000 0x00000000
  1907. 0x00000000 0x00000000 0x00000000 0x00000000
  1908. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  1909. 0x000fc000 0x00100220 0x0800201c 0x00000000
  1910. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1911. 0x08000068 0x08000000 0x00000802 0x00064000
  1912. 0x00000013 0x00090009 0xa0f10000 0x00000000
  1913. 0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
  1914. };
  1915. timing-102000000 {
  1916. clock-frequency = <102000000>;
  1917. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1918. nvidia,emc-mode-1 = <0x00010022>;
  1919. nvidia,emc-mode-2 = <0x00020001>;
  1920. nvidia,emc-mode-reset = <0x00000000>;
  1921. nvidia,emc-zcal-cnt-long = <0x0000000a>;
  1922. nvidia,emc-cfg-dyn-self-ref;
  1923. nvidia,emc-cfg-periodic-qrst;
  1924. nvidia,emc-configuration = < 0x00000006
  1925. 0x0000000d 0x00000004 0x00000002 0x00000004
  1926. 0x00000004 0x00000001 0x00000005 0x00000002
  1927. 0x00000002 0x00000001 0x00000001 0x00000000
  1928. 0x00000001 0x00000003 0x00000001 0x0000000b
  1929. 0x00000009 0x00000181 0x00000000 0x00000060
  1930. 0x00000001 0x00000001 0x00000002 0x00000000
  1931. 0x00000001 0x00000007 0x0000000f 0x0000000f
  1932. 0x00000003 0x00000008 0x00000004 0x00000004
  1933. 0x00000002 0x000001a9 0x00000004 0x00000004
  1934. 0x00000000 0x00000000 0x00004282 0x007800a4
  1935. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  1936. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  1937. 0x000fc000 0x00000000 0x00000000 0x00000000
  1938. 0x00000000 0x00000000 0x00000000 0x00000000
  1939. 0x00000000 0x00000000 0x00000000 0x00000000
  1940. 0x00000000 0x00000000 0x00000000 0x00000000
  1941. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  1942. 0x000fc000 0x00100220 0x0800201c 0x00000000
  1943. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1944. 0x08000068 0x08000000 0x00000802 0x00064000
  1945. 0x00000025 0x00090009 0xa0f10000 0x00000000
  1946. 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
  1947. };
  1948. timing-204000000 {
  1949. clock-frequency = <204000000>;
  1950. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1951. nvidia,emc-mode-1 = <0x00010042>;
  1952. nvidia,emc-mode-2 = <0x00020001>;
  1953. nvidia,emc-mode-reset = <0x00000000>;
  1954. nvidia,emc-zcal-cnt-long = <0x00000013>;
  1955. nvidia,emc-cfg-dyn-self-ref;
  1956. nvidia,emc-cfg-periodic-qrst;
  1957. nvidia,emc-configuration = < 0x0000000c
  1958. 0x0000001a 0x00000008 0x00000003 0x00000005
  1959. 0x00000004 0x00000001 0x00000006 0x00000003
  1960. 0x00000003 0x00000002 0x00000002 0x00000000
  1961. 0x00000001 0x00000004 0x00000001 0x0000000c
  1962. 0x0000000a 0x00000303 0x00000000 0x000000c0
  1963. 0x00000001 0x00000001 0x00000003 0x00000000
  1964. 0x00000001 0x00000007 0x0000001d 0x0000001d
  1965. 0x00000004 0x0000000b 0x00000005 0x00000004
  1966. 0x00000002 0x00000351 0x00000005 0x00000004
  1967. 0x00000000 0x00000000 0x00004282 0x004400a4
  1968. 0x00008000 0x00080000 0x00080000 0x00080000
  1969. 0x00080000 0x00080000 0x00080000 0x00080000
  1970. 0x00080000 0x00000000 0x00000000 0x00000000
  1971. 0x00000000 0x00000000 0x00000000 0x00000000
  1972. 0x00000000 0x00000000 0x00000000 0x00000000
  1973. 0x00000000 0x00000000 0x00000000 0x00000000
  1974. 0x00000000 0x00080000 0x00080000 0x00080000
  1975. 0x00080000 0x000e0220 0x0800201c 0x00000000
  1976. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  1977. 0x08000068 0x08000000 0x00000802 0x00064000
  1978. 0x0000004a 0x00090009 0xa0f10000 0x00000000
  1979. 0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
  1980. };
  1981. timing-533000000 {
  1982. clock-frequency = <533000000>;
  1983. nvidia,emc-auto-cal-interval = <0x001fffff>;
  1984. nvidia,emc-mode-1 = <0x000100c2>;
  1985. nvidia,emc-mode-2 = <0x00020006>;
  1986. nvidia,emc-mode-reset = <0x00000000>;
  1987. nvidia,emc-zcal-cnt-long = <0x00000030>;
  1988. nvidia,emc-cfg-periodic-qrst;
  1989. nvidia,emc-configuration = < 0x0000001f
  1990. 0x00000045 0x00000016 0x00000009 0x00000008
  1991. 0x00000009 0x00000003 0x0000000d 0x00000009
  1992. 0x00000009 0x00000005 0x00000003 0x00000000
  1993. 0x00000004 0x0000000a 0x00000006 0x0000000d
  1994. 0x00000010 0x000007df 0x00000000 0x000001f7
  1995. 0x00000003 0x00000003 0x00000009 0x00000000
  1996. 0x00000001 0x0000000f 0x0000004b 0x0000004b
  1997. 0x00000008 0x0000001b 0x0000000c 0x00000004
  1998. 0x00000002 0x000008aa 0x00000000 0x00000004
  1999. 0x00000000 0x00000000 0x00006282 0xf0120091
  2000. 0x00008000 0x007f8008 0x007f8008 0x007f8008
  2001. 0x007f8008 0x007f8008 0x007f8008 0x007f8008
  2002. 0x007f8008 0x00000000 0x00000000 0x00000000
  2003. 0x00000000 0x00000000 0x00000000 0x00000000
  2004. 0x00000000 0x00000000 0x00000000 0x00000000
  2005. 0x00000000 0x00000000 0x00000000 0x00000000
  2006. 0x00000000 0x0000000c 0x0000000c 0x0000000c
  2007. 0x0000000c 0x00080220 0x0200003d 0x00000000
  2008. 0x77ffc004 0x01f1f408 0x00000000 0x00000007
  2009. 0x08000068 0x08000000 0x00000802 0x00064000
  2010. 0x000000c0 0x000e000e 0xa0f10000 0x00000000
  2011. 0x00000000 0x800010d9 0xf0000000 0xff00ff88 >;
  2012. };
  2013. };
  2014. emc-timings-3 {
  2015. /* HYNIX H9TCNNN8JDMMPR NGM */
  2016. nvidia,ram-code = <3>;
  2017. timing-25500000 {
  2018. clock-frequency = <25500000>;
  2019. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2020. nvidia,emc-mode-1 = <0x00010022>;
  2021. nvidia,emc-mode-2 = <0x00020001>;
  2022. nvidia,emc-mode-reset = <0x00000000>;
  2023. nvidia,emc-zcal-cnt-long = <0x00000009>;
  2024. nvidia,emc-cfg-dyn-self-ref;
  2025. nvidia,emc-cfg-periodic-qrst;
  2026. nvidia,emc-configuration = < 0x00000001
  2027. 0x00000003 0x00000002 0x00000002 0x00000004
  2028. 0x00000004 0x00000001 0x00000005 0x00000002
  2029. 0x00000002 0x00000001 0x00000001 0x00000000
  2030. 0x00000001 0x00000003 0x00000001 0x0000000b
  2031. 0x0000000a 0x00000060 0x00000000 0x00000018
  2032. 0x00000001 0x00000001 0x00000002 0x00000000
  2033. 0x00000001 0x00000007 0x00000004 0x00000004
  2034. 0x00000003 0x00000008 0x00000004 0x00000004
  2035. 0x00000002 0x0000006b 0x00000004 0x00000004
  2036. 0x00000000 0x00000000 0x00004282 0x007800a4
  2037. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  2038. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  2039. 0x000fc000 0x00000000 0x00000000 0x00000000
  2040. 0x00000000 0x00000000 0x00000000 0x00000000
  2041. 0x00000000 0x00000000 0x00000000 0x00000000
  2042. 0x00000000 0x00000000 0x00000000 0x00000000
  2043. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  2044. 0x000fc000 0x00100220 0x0800201c 0x00000000
  2045. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  2046. 0x08000068 0x08000000 0x00000802 0x00064000
  2047. 0x0000000a 0x00090009 0xa0f10000 0x00000000
  2048. 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
  2049. };
  2050. timing-51000000 {
  2051. clock-frequency = <51000000>;
  2052. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2053. nvidia,emc-mode-1 = <0x00010022>;
  2054. nvidia,emc-mode-2 = <0x00020001>;
  2055. nvidia,emc-mode-reset = <0x00000000>;
  2056. nvidia,emc-zcal-cnt-long = <0x00000009>;
  2057. nvidia,emc-cfg-dyn-self-ref;
  2058. nvidia,emc-cfg-periodic-qrst;
  2059. nvidia,emc-configuration = < 0x00000003
  2060. 0x00000006 0x00000002 0x00000002 0x00000004
  2061. 0x00000004 0x00000001 0x00000005 0x00000002
  2062. 0x00000002 0x00000001 0x00000001 0x00000000
  2063. 0x00000001 0x00000003 0x00000001 0x0000000b
  2064. 0x0000000a 0x000000c0 0x00000000 0x00000030
  2065. 0x00000001 0x00000001 0x00000002 0x00000000
  2066. 0x00000001 0x00000007 0x00000008 0x00000008
  2067. 0x00000003 0x00000008 0x00000004 0x00000004
  2068. 0x00000002 0x000000d5 0x00000004 0x00000004
  2069. 0x00000000 0x00000000 0x00004282 0x007800a4
  2070. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  2071. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  2072. 0x000fc000 0x00000000 0x00000000 0x00000000
  2073. 0x00000000 0x00000000 0x00000000 0x00000000
  2074. 0x00000000 0x00000000 0x00000000 0x00000000
  2075. 0x00000000 0x00000000 0x00000000 0x00000000
  2076. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  2077. 0x000fc000 0x00100220 0x0800201c 0x00000000
  2078. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  2079. 0x08000068 0x08000000 0x00000802 0x00064000
  2080. 0x00000013 0x00090009 0xa0f10000 0x00000000
  2081. 0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
  2082. };
  2083. timing-102000000 {
  2084. clock-frequency = <102000000>;
  2085. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2086. nvidia,emc-mode-1 = <0x00010022>;
  2087. nvidia,emc-mode-2 = <0x00020001>;
  2088. nvidia,emc-mode-reset = <0x00000000>;
  2089. nvidia,emc-zcal-cnt-long = <0x0000000a>;
  2090. nvidia,emc-cfg-dyn-self-ref;
  2091. nvidia,emc-cfg-periodic-qrst;
  2092. nvidia,emc-configuration = < 0x00000006
  2093. 0x0000000d 0x00000004 0x00000002 0x00000004
  2094. 0x00000004 0x00000001 0x00000005 0x00000002
  2095. 0x00000002 0x00000001 0x00000001 0x00000000
  2096. 0x00000001 0x00000003 0x00000001 0x0000000b
  2097. 0x0000000a 0x00000181 0x00000000 0x00000060
  2098. 0x00000001 0x00000001 0x00000002 0x00000000
  2099. 0x00000001 0x00000007 0x0000000f 0x0000000f
  2100. 0x00000003 0x00000008 0x00000004 0x00000004
  2101. 0x00000002 0x000001a9 0x00000004 0x00000004
  2102. 0x00000000 0x00000000 0x00004282 0x007800a4
  2103. 0x00008000 0x000fc000 0x000fc000 0x000fc000
  2104. 0x000fc000 0x000fc000 0x000fc000 0x000fc000
  2105. 0x000fc000 0x00000000 0x00000000 0x00000000
  2106. 0x00000000 0x00000000 0x00000000 0x00000000
  2107. 0x00000000 0x00000000 0x00000000 0x00000000
  2108. 0x00000000 0x00000000 0x00000000 0x00000000
  2109. 0x00000000 0x000fc000 0x000fc000 0x000fc000
  2110. 0x000fc000 0x00100220 0x0800201c 0x00000000
  2111. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  2112. 0x08000068 0x08000000 0x00000802 0x00064000
  2113. 0x00000025 0x00090009 0xa0f10000 0x00000000
  2114. 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
  2115. };
  2116. timing-204000000 {
  2117. clock-frequency = <204000000>;
  2118. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2119. nvidia,emc-mode-1 = <0x00010042>;
  2120. nvidia,emc-mode-2 = <0x00020001>;
  2121. nvidia,emc-mode-reset = <0x00000000>;
  2122. nvidia,emc-zcal-cnt-long = <0x00000013>;
  2123. nvidia,emc-cfg-dyn-self-ref;
  2124. nvidia,emc-cfg-periodic-qrst;
  2125. nvidia,emc-configuration = < 0x0000000c
  2126. 0x0000001a 0x00000008 0x00000003 0x00000005
  2127. 0x00000004 0x00000001 0x00000006 0x00000003
  2128. 0x00000003 0x00000002 0x00000002 0x00000000
  2129. 0x00000001 0x00000003 0x00000001 0x0000000c
  2130. 0x0000000b 0x00000303 0x00000000 0x000000c0
  2131. 0x00000001 0x00000001 0x00000003 0x00000000
  2132. 0x00000001 0x00000007 0x0000001d 0x0000001d
  2133. 0x00000004 0x0000000b 0x00000005 0x00000004
  2134. 0x00000002 0x00000351 0x00000004 0x00000006
  2135. 0x00000000 0x00000000 0x00004282 0x004400a4
  2136. 0x00008000 0x00072000 0x00072000 0x00072000
  2137. 0x00072000 0x00072000 0x00072000 0x00072000
  2138. 0x00072000 0x00000000 0x00000000 0x00000000
  2139. 0x00000000 0x00000000 0x00000000 0x00000000
  2140. 0x00000000 0x00000000 0x00000000 0x00000000
  2141. 0x00000000 0x00000000 0x00000000 0x00000000
  2142. 0x00000000 0x00080000 0x00080000 0x00080000
  2143. 0x00080000 0x000e0220 0x0800201c 0x00000000
  2144. 0x77ffc004 0x01f1f008 0x00000000 0x00000007
  2145. 0x08000068 0x08000000 0x00000802 0x00064000
  2146. 0x0000004a 0x00090009 0xa0f10000 0x00000000
  2147. 0x00000000 0x80000713 0xd0000000 0xff00ff00 >;
  2148. };
  2149. timing-533000000 {
  2150. clock-frequency = <533000000>;
  2151. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2152. nvidia,emc-mode-1 = <0x000100c2>;
  2153. nvidia,emc-mode-2 = <0x00020006>;
  2154. nvidia,emc-mode-reset = <0x00000000>;
  2155. nvidia,emc-zcal-cnt-long = <0x00000030>;
  2156. nvidia,emc-cfg-periodic-qrst;
  2157. nvidia,emc-configuration = < 0x0000001f
  2158. 0x00000045 0x00000016 0x00000009 0x00000008
  2159. 0x00000009 0x00000003 0x0000000d 0x00000009
  2160. 0x00000009 0x00000005 0x00000003 0x00000000
  2161. 0x00000004 0x00000009 0x00000006 0x0000000d
  2162. 0x00000010 0x000007df 0x00000000 0x000001f7
  2163. 0x00000003 0x00000003 0x00000009 0x00000000
  2164. 0x00000001 0x0000000f 0x0000004b 0x0000004b
  2165. 0x00000008 0x0000001b 0x0000000c 0x00000004
  2166. 0x00000002 0x000008aa 0x00000000 0x00000006
  2167. 0x00000000 0x00000000 0x00006282 0xf0120091
  2168. 0x00008000 0x0000000a 0x0000000a 0x0000000a
  2169. 0x0000000a 0x0000000a 0x0000000a 0x0000000a
  2170. 0x0000000a 0x00000000 0x00000000 0x00000000
  2171. 0x00000000 0x00000000 0x00000000 0x00000000
  2172. 0x00000000 0x00000000 0x00000000 0x00000000
  2173. 0x00000000 0x00000000 0x00000000 0x00000000
  2174. 0x00000000 0x0000000c 0x0000000c 0x0000000c
  2175. 0x0000000c 0x000a0220 0x0800003d 0x00000000
  2176. 0x77ffc004 0x01f1f408 0x00000000 0x00000007
  2177. 0x08000068 0x08000000 0x00000802 0x00064000
  2178. 0x000000c0 0x000e000e 0xa0f10000 0x00000000
  2179. 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >;
  2180. };
  2181. };
  2182. };
  2183. hda@70030000 {
  2184. status = "okay";
  2185. };
  2186. ahub@70080000 {
  2187. i2s@70080400 { /* i2s1 */
  2188. status = "okay";
  2189. };
  2190. /* BT SCO */
  2191. i2s@70080600 { /* i2s3 */
  2192. status = "okay";
  2193. };
  2194. };
  2195. sdmmc1: mmc@78000000 {
  2196. status = "okay";
  2197. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  2198. bus-width = <4>;
  2199. vmmc-supply = <&vdd_usd>; /* ldo2 */
  2200. vqmmc-supply = <&vddio_usd>; /* ldo3 */
  2201. };
  2202. brcm_wifi_pwrseq: wifi-pwrseq {
  2203. compatible = "mmc-pwrseq-simple";
  2204. clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  2205. clock-names = "ext_clock";
  2206. reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
  2207. post-power-on-delay-ms = <300>;
  2208. power-off-delay-us = <300>;
  2209. };
  2210. sdmmc3: mmc@78000400 {
  2211. status = "okay";
  2212. #address-cells = <1>;
  2213. #size-cells = <0>;
  2214. assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
  2215. assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
  2216. assigned-clock-rates = <50000000>;
  2217. max-frequency = <50000000>;
  2218. keep-power-in-suspend;
  2219. bus-width = <4>;
  2220. non-removable;
  2221. mmc-pwrseq = <&brcm_wifi_pwrseq>;
  2222. vmmc-supply = <&vdd_3v3_sys>;
  2223. vqmmc-supply = <&vdd_1v8_vio>;
  2224. /* Azurewave AW-AH663 BCM4330B1 */
  2225. wifi@1 {
  2226. compatible = "brcm,bcm4329-fmac";
  2227. reg = <1>;
  2228. interrupt-parent = <&gpio>;
  2229. interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
  2230. interrupt-names = "host-wake";
  2231. };
  2232. };
  2233. sdmmc4: mmc@78000600 {
  2234. status = "okay";
  2235. bus-width = <8>;
  2236. vmmc-supply = <&vcore_emmc>;
  2237. vqmmc-supply = <&vdd_1v8_vio>;
  2238. non-removable;
  2239. };
  2240. usb@7d000000 {
  2241. compatible = "nvidia,tegra30-udc";
  2242. status = "okay";
  2243. dr_mode = "otg";
  2244. vbus-supply = <&vdd_vbus_usb1>;
  2245. };
  2246. usb-phy@7d000000 {
  2247. status = "okay";
  2248. dr_mode = "otg";
  2249. nvidia,hssync-start-delay = <0>;
  2250. nvidia,xcvr-lsfslew = <2>;
  2251. nvidia,xcvr-lsrslew = <2>;
  2252. };
  2253. usb@7d008000 {
  2254. status = "okay";
  2255. };
  2256. usb-phy@7d008000 {
  2257. status = "okay";
  2258. vbus-supply = <&vdd_vbus_usb3>;
  2259. };
  2260. mains: ac-adapter-detect {
  2261. compatible = "gpio-charger";
  2262. charger-type = "mains";
  2263. gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
  2264. };
  2265. backlight: backlight {
  2266. compatible = "pwm-backlight";
  2267. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  2268. power-supply = <&vdd_5v0_bl>;
  2269. pwms = <&pwm 0 5000000>;
  2270. brightness-levels = <1 255>;
  2271. num-interpolated-steps = <254>;
  2272. default-brightness-level = <15>;
  2273. };
  2274. /* PMIC has a built-in 32KHz oscillator which is used by PMC */
  2275. clk32k_in: clock-32k {
  2276. compatible = "fixed-clock";
  2277. #clock-cells = <0>;
  2278. clock-frequency = <32768>;
  2279. clock-output-names = "pmic-oscillator";
  2280. };
  2281. cpus {
  2282. cpu0: cpu@0 {
  2283. cpu-supply = <&vdd_cpu>;
  2284. operating-points-v2 = <&cpu0_opp_table>;
  2285. #cooling-cells = <2>;
  2286. };
  2287. cpu1: cpu@1 {
  2288. cpu-supply = <&vdd_cpu>;
  2289. operating-points-v2 = <&cpu0_opp_table>;
  2290. #cooling-cells = <2>;
  2291. };
  2292. cpu2: cpu@2 {
  2293. cpu-supply = <&vdd_cpu>;
  2294. operating-points-v2 = <&cpu0_opp_table>;
  2295. #cooling-cells = <2>;
  2296. };
  2297. cpu3: cpu@3 {
  2298. cpu-supply = <&vdd_cpu>;
  2299. operating-points-v2 = <&cpu0_opp_table>;
  2300. #cooling-cells = <2>;
  2301. };
  2302. };
  2303. display-panel {
  2304. compatible = "panel-lvds";
  2305. width-mm = <217>;
  2306. height-mm = <136>;
  2307. data-mapping = "jeida-24";
  2308. panel-timing {
  2309. /* 1280x800@60Hz */
  2310. clock-frequency = <68000000>;
  2311. hactive = <1280>;
  2312. vactive = <800>;
  2313. hfront-porch = <48>;
  2314. hback-porch = <18>;
  2315. hsync-len = <30>;
  2316. vsync-len = <5>;
  2317. vfront-porch = <3>;
  2318. vback-porch = <12>;
  2319. };
  2320. };
  2321. extcon-keys {
  2322. compatible = "gpio-keys";
  2323. interrupt-parent = <&gpio>;
  2324. switch-dock-insert {
  2325. label = "Chagall Dock";
  2326. gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
  2327. linux,input-type = <EV_SW>;
  2328. linux,code = <SW_DOCK>;
  2329. debounce-interval = <10>;
  2330. wakeup-event-action = <EV_ACT_ASSERTED>;
  2331. wakeup-source;
  2332. };
  2333. switch-lineout-detect {
  2334. label = "Audio dock line-out detect";
  2335. gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>;
  2336. linux,input-type = <EV_SW>;
  2337. linux,code = <SW_LINEOUT_INSERT>;
  2338. debounce-interval = <10>;
  2339. wakeup-event-action = <EV_ACT_ASSERTED>;
  2340. wakeup-source;
  2341. };
  2342. };
  2343. firmware {
  2344. trusted-foundations {
  2345. compatible = "tlm,trusted-foundations";
  2346. tlm,version-major = <2>;
  2347. tlm,version-minor = <8>;
  2348. };
  2349. };
  2350. gpio-keys {
  2351. compatible = "gpio-keys";
  2352. interrupt-parent = <&gpio>;
  2353. key-power {
  2354. label = "Power";
  2355. gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
  2356. linux,code = <KEY_POWER>;
  2357. debounce-interval = <10>;
  2358. wakeup-event-action = <EV_ACT_ASSERTED>;
  2359. wakeup-source;
  2360. };
  2361. key-volume-up {
  2362. label = "Volume Up";
  2363. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  2364. linux,code = <KEY_VOLUMEUP>;
  2365. debounce-interval = <10>;
  2366. wakeup-event-action = <EV_ACT_ASSERTED>;
  2367. wakeup-source;
  2368. };
  2369. key-volume-down {
  2370. label = "Volume Down";
  2371. gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>;
  2372. linux,code = <KEY_VOLUMEDOWN>;
  2373. debounce-interval = <10>;
  2374. wakeup-event-action = <EV_ACT_ASSERTED>;
  2375. wakeup-source;
  2376. };
  2377. };
  2378. haptic-feedback {
  2379. compatible = "gpio-vibrator";
  2380. enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
  2381. vcc-supply = <&vdd_3v3_sys>;
  2382. };
  2383. sound {
  2384. compatible = "pegatron,tegra-audio-wm8903-chagall",
  2385. "nvidia,tegra-audio-wm8903";
  2386. nvidia,model = "Pegatron Chagall WM8903";
  2387. nvidia,audio-routing =
  2388. "Headphone Jack", "HPOUTR",
  2389. "Headphone Jack", "HPOUTL",
  2390. "Int Spk", "ROP",
  2391. "Int Spk", "RON",
  2392. "Int Spk", "LOP",
  2393. "Int Spk", "LON",
  2394. "IN1R", "Mic Jack",
  2395. "DMICDAT", "Int Mic";
  2396. nvidia,i2s-controller = <&tegra_i2s1>;
  2397. nvidia,audio-codec = <&wm8903>;
  2398. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  2399. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
  2400. nvidia,headset;
  2401. clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
  2402. <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  2403. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  2404. clock-names = "pll_a", "pll_a_out0", "mclk";
  2405. assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
  2406. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  2407. assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  2408. <&tegra_car TEGRA30_CLK_EXTERN1>;
  2409. };
  2410. thermal-zones {
  2411. /*
  2412. * NCT72 has two sensors:
  2413. *
  2414. * 0: internal that monitors ambient/skin temperature
  2415. * 1: external that is connected to the CPU's diode
  2416. *
  2417. * Ideally we should use userspace thermal governor,
  2418. * but it's a much more complex solution. The "skin"
  2419. * zone exists as a simpler solution which prevents
  2420. * Chagall from getting too hot from a user's tactile
  2421. * perspective. The CPU zone is intended to protect
  2422. * silicon from damage.
  2423. */
  2424. skin-thermal {
  2425. polling-delay-passive = <1000>; /* milliseconds */
  2426. polling-delay = <5000>; /* milliseconds */
  2427. thermal-sensors = <&nct72 0>;
  2428. trips {
  2429. trip0: skin-alert {
  2430. /* throttle at 57C until temperature drops to 56.8C */
  2431. temperature = <57000>;
  2432. hysteresis = <200>;
  2433. type = "passive";
  2434. };
  2435. trip1: skin-crit {
  2436. /* shut down at 65C */
  2437. temperature = <65000>;
  2438. hysteresis = <2000>;
  2439. type = "critical";
  2440. };
  2441. };
  2442. cooling-maps {
  2443. map0 {
  2444. trip = <&trip0>;
  2445. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  2446. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  2447. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  2448. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  2449. <&actmon THERMAL_NO_LIMIT
  2450. THERMAL_NO_LIMIT>;
  2451. };
  2452. };
  2453. };
  2454. cpu-thermal {
  2455. polling-delay-passive = <1000>; /* milliseconds */
  2456. polling-delay = <5000>; /* milliseconds */
  2457. thermal-sensors = <&nct72 1>;
  2458. trips {
  2459. trip2: cpu-alert {
  2460. /* throttle at 85C until temperature drops to 84.8C */
  2461. temperature = <85000>;
  2462. hysteresis = <200>;
  2463. type = "passive";
  2464. };
  2465. trip3: cpu-crit {
  2466. /* shut down at 90C */
  2467. temperature = <90000>;
  2468. hysteresis = <2000>;
  2469. type = "critical";
  2470. };
  2471. };
  2472. cooling-maps {
  2473. map1 {
  2474. trip = <&trip2>;
  2475. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  2476. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  2477. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  2478. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  2479. <&actmon THERMAL_NO_LIMIT
  2480. THERMAL_NO_LIMIT>;
  2481. };
  2482. };
  2483. };
  2484. };
  2485. };
  2486. &emc_icc_dvfs_opp_table {
  2487. /delete-node/ opp-625000000-1200;
  2488. /delete-node/ opp-625000000-1250;
  2489. /delete-node/ opp-667000000-1200;
  2490. /delete-node/ opp-750000000-1300;
  2491. /delete-node/ opp-800000000-1300;
  2492. /delete-node/ opp-900000000-1350;
  2493. };
  2494. &emc_bw_dfs_opp_table {
  2495. /delete-node/ opp-625000000;
  2496. /delete-node/ opp-667000000;
  2497. /delete-node/ opp-750000000;
  2498. /delete-node/ opp-800000000;
  2499. /delete-node/ opp-900000000;
  2500. };