tegra30-ouya.dts 146 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/gpio-keys.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/thermal/thermal.h>
  6. #include "tegra30.dtsi"
  7. #include "tegra30-cpu-opp.dtsi"
  8. #include "tegra30-cpu-opp-microvolt.dtsi"
  9. / {
  10. model = "Ouya Game Console";
  11. compatible = "ouya,ouya", "nvidia,tegra30";
  12. aliases {
  13. mmc0 = &sdmmc4; /* eMMC */
  14. mmc1 = &sdmmc3; /* WiFi */
  15. rtc0 = &pmic;
  16. rtc1 = "/rtc@7000e000";
  17. serial0 = &uartd; /* Debug Port */
  18. serial1 = &uartc; /* Bluetooth */
  19. };
  20. chosen {
  21. stdout-path = "serial0:115200n8";
  22. };
  23. memory@80000000 {
  24. reg = <0x80000000 0x40000000>;
  25. };
  26. reserved-memory {
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. ranges;
  30. linux,cma@80000000 {
  31. compatible = "shared-dma-pool";
  32. alloc-ranges = <0x80000000 0x30000000>;
  33. size = <0x10000000>; /* 256MiB */
  34. linux,cma-default;
  35. reusable;
  36. };
  37. ramoops@bfdf0000 {
  38. compatible = "ramoops";
  39. reg = <0xbfdf0000 0x10000>; /* 64kB */
  40. console-size = <0x8000>; /* 32kB */
  41. record-size = <0x400>; /* 1kB */
  42. ecc-size = <16>;
  43. };
  44. trustzone@bfe00000 {
  45. reg = <0xbfe00000 0x200000>;
  46. no-map;
  47. };
  48. };
  49. host1x@50000000 {
  50. hdmi@54280000 {
  51. status = "okay";
  52. vdd-supply = <&vdd_vid_reg>;
  53. pll-supply = <&ldo7_reg>;
  54. hdmi-supply = <&sys_3v3_reg>;
  55. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  56. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  57. };
  58. };
  59. pinmux@70000868 {
  60. pinctrl-names = "default";
  61. pinctrl-0 = <&state_default>;
  62. state_default: pinmux {
  63. clk_32k_out_pa0 {
  64. nvidia,pins = "clk_32k_out_pa0";
  65. nvidia,function = "blink";
  66. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  67. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  68. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  69. };
  70. uart3_cts_n_pa1 {
  71. nvidia,pins = "uart3_cts_n_pa1";
  72. nvidia,function = "uartc";
  73. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  74. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  75. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  76. };
  77. dap2_fs_pa2 {
  78. nvidia,pins = "dap2_fs_pa2";
  79. nvidia,function = "i2s1";
  80. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  81. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  82. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  83. };
  84. dap2_sclk_pa3 {
  85. nvidia,pins = "dap2_sclk_pa3";
  86. nvidia,function = "i2s1";
  87. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  88. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  89. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  90. };
  91. dap2_din_pa4 {
  92. nvidia,pins = "dap2_din_pa4";
  93. nvidia,function = "i2s1";
  94. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  95. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  96. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  97. };
  98. dap2_dout_pa5 {
  99. nvidia,pins = "dap2_dout_pa5";
  100. nvidia,function = "i2s1";
  101. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  102. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  103. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  104. };
  105. sdmmc3_clk_pa6 {
  106. nvidia,pins = "sdmmc3_clk_pa6";
  107. nvidia,function = "sdmmc3";
  108. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  109. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  110. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  111. };
  112. sdmmc3_cmd_pa7 {
  113. nvidia,pins = "sdmmc3_cmd_pa7";
  114. nvidia,function = "sdmmc3";
  115. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  116. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  117. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  118. };
  119. gmi_a17_pb0 {
  120. nvidia,pins = "gmi_a17_pb0";
  121. nvidia,function = "spi4";
  122. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  123. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  124. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  125. };
  126. gmi_a18_pb1 {
  127. nvidia,pins = "gmi_a18_pb1";
  128. nvidia,function = "spi4";
  129. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  130. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  131. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  132. };
  133. lcd_pwr0_pb2 {
  134. nvidia,pins = "lcd_pwr0_pb2";
  135. nvidia,function = "displaya";
  136. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  137. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  138. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  139. };
  140. lcd_pclk_pb3 {
  141. nvidia,pins = "lcd_pclk_pb3";
  142. nvidia,function = "displaya";
  143. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  144. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  145. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  146. };
  147. sdmmc3_dat3_pb4 {
  148. nvidia,pins = "sdmmc3_dat3_pb4";
  149. nvidia,function = "sdmmc3";
  150. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  151. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  152. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  153. };
  154. sdmmc3_dat2_pb5 {
  155. nvidia,pins = "sdmmc3_dat2_pb5";
  156. nvidia,function = "sdmmc3";
  157. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  158. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  159. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  160. };
  161. sdmmc3_dat1_pb6 {
  162. nvidia,pins = "sdmmc3_dat1_pb6";
  163. nvidia,function = "sdmmc3";
  164. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  165. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  166. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  167. };
  168. sdmmc3_dat0_pb7 {
  169. nvidia,pins = "sdmmc3_dat0_pb7";
  170. nvidia,function = "sdmmc3";
  171. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  172. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  173. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  174. };
  175. uart3_rts_n_pc0 {
  176. nvidia,pins = "uart3_rts_n_pc0";
  177. nvidia,function = "uartc";
  178. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  179. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  180. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  181. };
  182. lcd_pwr1_pc1 {
  183. nvidia,pins = "lcd_pwr1_pc1";
  184. nvidia,function = "displaya";
  185. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  186. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  187. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  188. };
  189. uart2_txd_pc2 {
  190. nvidia,pins = "uart2_txd_pc2";
  191. nvidia,function = "uartb";
  192. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  193. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  194. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  195. };
  196. uart2_rxd_pc3 {
  197. nvidia,pins = "uart2_rxd_pc3";
  198. nvidia,function = "uartb";
  199. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  200. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  201. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  202. };
  203. gen1_i2c_scl_pc4 {
  204. nvidia,pins = "gen1_i2c_scl_pc4";
  205. nvidia,function = "i2c1";
  206. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  207. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  208. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  209. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  210. };
  211. gen1_i2c_sda_pc5 {
  212. nvidia,pins = "gen1_i2c_sda_pc5";
  213. nvidia,function = "i2c1";
  214. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  215. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  216. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  217. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  218. };
  219. lcd_pwr2_pc6 {
  220. nvidia,pins = "lcd_pwr2_pc6";
  221. nvidia,function = "displaya";
  222. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  223. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  224. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  225. };
  226. gmi_wp_n_pc7 {
  227. nvidia,pins = "gmi_wp_n_pc7";
  228. nvidia,function = "gmi";
  229. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  230. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  231. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  232. };
  233. sdmmc3_dat5_pd0 {
  234. nvidia,pins = "sdmmc3_dat5_pd0";
  235. nvidia,function = "sdmmc3";
  236. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  237. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  238. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  239. };
  240. sdmmc3_dat4_pd1 {
  241. nvidia,pins = "sdmmc3_dat4_pd1";
  242. nvidia,function = "sdmmc3";
  243. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  244. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  245. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  246. };
  247. lcd_dc1_pd2 {
  248. nvidia,pins = "lcd_dc1_pd2";
  249. nvidia,function = "displaya";
  250. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  251. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  252. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  253. };
  254. sdmmc3_dat6_pd3 {
  255. nvidia,pins = "sdmmc3_dat6_pd3";
  256. nvidia,function = "spi4";
  257. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  258. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  259. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  260. };
  261. sdmmc3_dat7_pd4 {
  262. nvidia,pins = "sdmmc3_dat7_pd4";
  263. nvidia,function = "spi4";
  264. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  265. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  266. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  267. };
  268. vi_d1_pd5 {
  269. nvidia,pins = "vi_d1_pd5";
  270. nvidia,function = "sdmmc2";
  271. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  272. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  273. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  274. };
  275. vi_vsync_pd6 {
  276. nvidia,pins = "vi_vsync_pd6";
  277. nvidia,function = "ddr";
  278. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  279. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  280. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  281. };
  282. vi_hsync_pd7 {
  283. nvidia,pins = "vi_hsync_pd7";
  284. nvidia,function = "ddr";
  285. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  286. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  287. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  288. };
  289. lcd_d0_pe0 {
  290. nvidia,pins = "lcd_d0_pe0";
  291. nvidia,function = "displaya";
  292. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  293. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  294. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  295. };
  296. lcd_d1_pe1 {
  297. nvidia,pins = "lcd_d1_pe1";
  298. nvidia,function = "displaya";
  299. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  300. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  301. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  302. };
  303. lcd_d2_pe2 {
  304. nvidia,pins = "lcd_d2_pe2";
  305. nvidia,function = "displaya";
  306. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  307. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  308. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  309. };
  310. lcd_d3_pe3 {
  311. nvidia,pins = "lcd_d3_pe3";
  312. nvidia,function = "displaya";
  313. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  314. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  315. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  316. };
  317. lcd_d4_pe4 {
  318. nvidia,pins = "lcd_d4_pe4";
  319. nvidia,function = "displaya";
  320. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  321. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  322. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  323. };
  324. lcd_d5_pe5 {
  325. nvidia,pins = "lcd_d5_pe5";
  326. nvidia,function = "displaya";
  327. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  328. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  329. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  330. };
  331. lcd_d6_pe6 {
  332. nvidia,pins = "lcd_d6_pe6";
  333. nvidia,function = "displaya";
  334. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  335. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  336. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  337. };
  338. lcd_d7_pe7 {
  339. nvidia,pins = "lcd_d7_pe7";
  340. nvidia,function = "displaya";
  341. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  342. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  343. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  344. };
  345. lcd_d8_pf0 {
  346. nvidia,pins = "lcd_d8_pf0";
  347. nvidia,function = "displaya";
  348. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  349. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  350. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  351. };
  352. lcd_d9_pf1 {
  353. nvidia,pins = "lcd_d9_pf1";
  354. nvidia,function = "displaya";
  355. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  356. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  357. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  358. };
  359. lcd_d10_pf2 {
  360. nvidia,pins = "lcd_d10_pf2";
  361. nvidia,function = "displaya";
  362. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  363. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  364. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  365. };
  366. lcd_d11_pf3 {
  367. nvidia,pins = "lcd_d11_pf3";
  368. nvidia,function = "displaya";
  369. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  370. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  371. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  372. };
  373. lcd_d12_pf4 {
  374. nvidia,pins = "lcd_d12_pf4";
  375. nvidia,function = "displaya";
  376. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  377. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  378. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  379. };
  380. lcd_d13_pf5 {
  381. nvidia,pins = "lcd_d13_pf5";
  382. nvidia,function = "displaya";
  383. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  384. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  385. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  386. };
  387. lcd_d14_pf6 {
  388. nvidia,pins = "lcd_d14_pf6";
  389. nvidia,function = "displaya";
  390. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  391. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  392. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  393. };
  394. lcd_d15_pf7 {
  395. nvidia,pins = "lcd_d15_pf7";
  396. nvidia,function = "displaya";
  397. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  398. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  399. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  400. };
  401. gmi_ad0_pg0 {
  402. nvidia,pins = "gmi_ad0_pg0";
  403. nvidia,function = "nand";
  404. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  405. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  406. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  407. };
  408. gmi_ad1_pg1 {
  409. nvidia,pins = "gmi_ad1_pg1";
  410. nvidia,function = "nand";
  411. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  412. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  413. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  414. };
  415. gmi_ad2_pg2 {
  416. nvidia,pins = "gmi_ad2_pg2";
  417. nvidia,function = "nand";
  418. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  419. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  420. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  421. };
  422. gmi_ad3_pg3 {
  423. nvidia,pins = "gmi_ad3_pg3";
  424. nvidia,function = "nand";
  425. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  426. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  427. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  428. };
  429. gmi_ad4_pg4 {
  430. nvidia,pins = "gmi_ad4_pg4";
  431. nvidia,function = "nand";
  432. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  433. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  434. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  435. };
  436. gmi_ad5_pg5 {
  437. nvidia,pins = "gmi_ad5_pg5";
  438. nvidia,function = "nand";
  439. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  440. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  441. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  442. };
  443. gmi_ad6_pg6 {
  444. nvidia,pins = "gmi_ad6_pg6";
  445. nvidia,function = "nand";
  446. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  447. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  448. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  449. };
  450. gmi_ad7_pg7 {
  451. nvidia,pins = "gmi_ad7_pg7";
  452. nvidia,function = "nand";
  453. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  454. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  455. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  456. };
  457. gmi_ad8_ph0 {
  458. nvidia,pins = "gmi_ad8_ph0";
  459. nvidia,function = "pwm0";
  460. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  461. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  462. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  463. };
  464. gmi_ad9_ph1 {
  465. nvidia,pins = "gmi_ad9_ph1";
  466. nvidia,function = "pwm1";
  467. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  468. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  469. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  470. };
  471. gmi_ad10_ph2 {
  472. nvidia,pins = "gmi_ad10_ph2";
  473. nvidia,function = "pwm2";
  474. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  475. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  476. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  477. };
  478. gmi_ad11_ph3 {
  479. nvidia,pins = "gmi_ad11_ph3";
  480. nvidia,function = "nand";
  481. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  482. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  483. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  484. };
  485. gmi_ad12_ph4 {
  486. nvidia,pins = "gmi_ad12_ph4";
  487. nvidia,function = "nand";
  488. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  489. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  490. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  491. };
  492. gmi_ad13_ph5 {
  493. nvidia,pins = "gmi_ad13_ph5";
  494. nvidia,function = "nand";
  495. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  496. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  497. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  498. };
  499. gmi_ad14_ph6 {
  500. nvidia,pins = "gmi_ad14_ph6";
  501. nvidia,function = "nand";
  502. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  503. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  504. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  505. };
  506. gmi_wr_n_pi0 {
  507. nvidia,pins = "gmi_wr_n_pi0";
  508. nvidia,function = "nand";
  509. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  510. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  511. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  512. };
  513. gmi_oe_n_pi1 {
  514. nvidia,pins = "gmi_oe_n_pi1";
  515. nvidia,function = "nand";
  516. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  517. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  518. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  519. };
  520. gmi_dqs_pi2 {
  521. nvidia,pins = "gmi_dqs_pi2";
  522. nvidia,function = "nand";
  523. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  524. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  525. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  526. };
  527. gmi_iordy_pi5 {
  528. nvidia,pins = "gmi_iordy_pi5";
  529. nvidia,function = "rsvd1";
  530. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  531. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  532. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  533. };
  534. gmi_cs7_n_pi6 {
  535. nvidia,pins = "gmi_cs7_n_pi6";
  536. nvidia,function = "nand";
  537. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  538. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  539. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  540. };
  541. gmi_wait_pi7 {
  542. nvidia,pins = "gmi_wait_pi7";
  543. nvidia,function = "nand";
  544. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  545. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  546. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  547. };
  548. lcd_de_pj1 {
  549. nvidia,pins = "lcd_de_pj1";
  550. nvidia,function = "displaya";
  551. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  552. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  553. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  554. };
  555. gmi_cs1_n_pj2 {
  556. nvidia,pins = "gmi_cs1_n_pj2";
  557. nvidia,function = "rsvd1";
  558. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  559. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  560. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  561. };
  562. lcd_hsync_pj3 {
  563. nvidia,pins = "lcd_hsync_pj3";
  564. nvidia,function = "displaya";
  565. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  566. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  567. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  568. };
  569. lcd_vsync_pj4 {
  570. nvidia,pins = "lcd_vsync_pj4";
  571. nvidia,function = "displaya";
  572. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  573. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  574. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  575. };
  576. uart2_cts_n_pj5 {
  577. nvidia,pins = "uart2_cts_n_pj5";
  578. nvidia,function = "uartb";
  579. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  580. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  581. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  582. };
  583. uart2_rts_n_pj6 {
  584. nvidia,pins = "uart2_rts_n_pj6";
  585. nvidia,function = "uartb";
  586. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  587. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  588. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  589. };
  590. gmi_a16_pj7 {
  591. nvidia,pins = "gmi_a16_pj7";
  592. nvidia,function = "spi4";
  593. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  594. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  595. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  596. };
  597. gmi_adv_n_pk0 {
  598. nvidia,pins = "gmi_adv_n_pk0";
  599. nvidia,function = "nand";
  600. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  601. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  602. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  603. };
  604. gmi_clk_pk1 {
  605. nvidia,pins = "gmi_clk_pk1";
  606. nvidia,function = "nand";
  607. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  608. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  609. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  610. };
  611. gmi_cs2_n_pk3 {
  612. nvidia,pins = "gmi_cs2_n_pk3";
  613. nvidia,function = "rsvd1";
  614. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  615. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  616. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  617. };
  618. gmi_cs3_n_pk4 {
  619. nvidia,pins = "gmi_cs3_n_pk4";
  620. nvidia,function = "nand";
  621. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  622. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  623. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  624. };
  625. spdif_out_pk5 {
  626. nvidia,pins = "spdif_out_pk5";
  627. nvidia,function = "spdif";
  628. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  629. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  630. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  631. };
  632. spdif_in_pk6 {
  633. nvidia,pins = "spdif_in_pk6";
  634. nvidia,function = "spdif";
  635. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  636. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  637. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  638. };
  639. gmi_a19_pk7 {
  640. nvidia,pins = "gmi_a19_pk7";
  641. nvidia,function = "spi4";
  642. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  643. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  644. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  645. };
  646. vi_d2_pl0 {
  647. nvidia,pins = "vi_d2_pl0";
  648. nvidia,function = "sdmmc2";
  649. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  650. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  651. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  652. };
  653. vi_d3_pl1 {
  654. nvidia,pins = "vi_d3_pl1";
  655. nvidia,function = "sdmmc2";
  656. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  657. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  658. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  659. };
  660. vi_d4_pl2 {
  661. nvidia,pins = "vi_d4_pl2";
  662. nvidia,function = "vi";
  663. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  664. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  665. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  666. };
  667. vi_d5_pl3 {
  668. nvidia,pins = "vi_d5_pl3";
  669. nvidia,function = "sdmmc2";
  670. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  671. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  672. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  673. };
  674. vi_d6_pl4 {
  675. nvidia,pins = "vi_d6_pl4";
  676. nvidia,function = "vi";
  677. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  678. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  679. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  680. };
  681. vi_d7_pl5 {
  682. nvidia,pins = "vi_d7_pl5";
  683. nvidia,function = "sdmmc2";
  684. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  685. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  686. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  687. };
  688. vi_d8_pl6 {
  689. nvidia,pins = "vi_d8_pl6";
  690. nvidia,function = "sdmmc2";
  691. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  692. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  693. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  694. };
  695. vi_d9_pl7 {
  696. nvidia,pins = "vi_d9_pl7";
  697. nvidia,function = "sdmmc2";
  698. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  699. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  700. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  701. };
  702. lcd_d16_pm0 {
  703. nvidia,pins = "lcd_d16_pm0";
  704. nvidia,function = "displaya";
  705. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  706. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  707. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  708. };
  709. lcd_d17_pm1 {
  710. nvidia,pins = "lcd_d17_pm1";
  711. nvidia,function = "displaya";
  712. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  713. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  714. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  715. };
  716. lcd_d18_pm2 {
  717. nvidia,pins = "lcd_d18_pm2";
  718. nvidia,function = "displaya";
  719. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  720. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  721. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  722. };
  723. lcd_d19_pm3 {
  724. nvidia,pins = "lcd_d19_pm3";
  725. nvidia,function = "displaya";
  726. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  727. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  728. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  729. };
  730. lcd_d20_pm4 {
  731. nvidia,pins = "lcd_d20_pm4";
  732. nvidia,function = "displaya";
  733. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  734. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  735. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  736. };
  737. lcd_d21_pm5 {
  738. nvidia,pins = "lcd_d21_pm5";
  739. nvidia,function = "displaya";
  740. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  741. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  742. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  743. };
  744. lcd_d22_pm6 {
  745. nvidia,pins = "lcd_d22_pm6";
  746. nvidia,function = "displaya";
  747. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  748. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  749. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  750. };
  751. lcd_d23_pm7 {
  752. nvidia,pins = "lcd_d23_pm7";
  753. nvidia,function = "displaya";
  754. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  755. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  756. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  757. };
  758. dap1_fs_pn0 {
  759. nvidia,pins = "dap1_fs_pn0";
  760. nvidia,function = "i2s0";
  761. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  762. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  763. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  764. };
  765. dap1_din_pn1 {
  766. nvidia,pins = "dap1_din_pn1";
  767. nvidia,function = "i2s0";
  768. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  769. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  770. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  771. };
  772. dap1_dout_pn2 {
  773. nvidia,pins = "dap1_dout_pn2";
  774. nvidia,function = "i2s0";
  775. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  776. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  777. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  778. };
  779. dap1_sclk_pn3 {
  780. nvidia,pins = "dap1_sclk_pn3";
  781. nvidia,function = "i2s0";
  782. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  783. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  784. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  785. };
  786. lcd_cs0_n_pn4 {
  787. nvidia,pins = "lcd_cs0_n_pn4";
  788. nvidia,function = "displaya";
  789. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  790. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  791. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  792. };
  793. lcd_sdout_pn5 {
  794. nvidia,pins = "lcd_sdout_pn5";
  795. nvidia,function = "displaya";
  796. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  797. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  798. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  799. };
  800. lcd_dc0_pn6 {
  801. nvidia,pins = "lcd_dc0_pn6";
  802. nvidia,function = "displaya";
  803. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  804. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  805. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  806. };
  807. hdmi_int_pn7 {
  808. nvidia,pins = "hdmi_int_pn7";
  809. nvidia,function = "hdmi";
  810. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  811. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  812. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  813. };
  814. ulpi_data7_po0 {
  815. nvidia,pins = "ulpi_data7_po0";
  816. nvidia,function = "uarta";
  817. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  818. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  819. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  820. };
  821. ulpi_data0_po1 {
  822. nvidia,pins = "ulpi_data0_po1";
  823. nvidia,function = "uarta";
  824. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  825. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  826. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  827. };
  828. ulpi_data1_po2 {
  829. nvidia,pins = "ulpi_data1_po2";
  830. nvidia,function = "uarta";
  831. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  832. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  833. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  834. };
  835. ulpi_data2_po3 {
  836. nvidia,pins = "ulpi_data2_po3";
  837. nvidia,function = "uarta";
  838. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  839. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  840. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  841. };
  842. ulpi_data3_po4 {
  843. nvidia,pins = "ulpi_data3_po4";
  844. nvidia,function = "uarta";
  845. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  846. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  847. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  848. };
  849. ulpi_data4_po5 {
  850. nvidia,pins = "ulpi_data4_po5";
  851. nvidia,function = "uarta";
  852. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  853. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  854. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  855. };
  856. ulpi_data5_po6 {
  857. nvidia,pins = "ulpi_data5_po6";
  858. nvidia,function = "uarta";
  859. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  860. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  861. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  862. };
  863. ulpi_data6_po7 {
  864. nvidia,pins = "ulpi_data6_po7";
  865. nvidia,function = "uarta";
  866. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  867. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  868. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  869. };
  870. dap3_fs_pp0 {
  871. nvidia,pins = "dap3_fs_pp0";
  872. nvidia,function = "i2s2";
  873. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  874. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  875. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  876. };
  877. dap3_din_pp1 {
  878. nvidia,pins = "dap3_din_pp1";
  879. nvidia,function = "i2s2";
  880. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  881. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  882. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  883. };
  884. dap3_dout_pp2 {
  885. nvidia,pins = "dap3_dout_pp2";
  886. nvidia,function = "i2s2";
  887. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  888. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  889. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  890. };
  891. dap3_sclk_pp3 {
  892. nvidia,pins = "dap3_sclk_pp3";
  893. nvidia,function = "i2s2";
  894. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  895. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  896. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  897. };
  898. dap4_fs_pp4 {
  899. nvidia,pins = "dap4_fs_pp4";
  900. nvidia,function = "i2s3";
  901. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  902. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  903. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  904. };
  905. dap4_din_pp5 {
  906. nvidia,pins = "dap4_din_pp5";
  907. nvidia,function = "i2s3";
  908. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  909. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  910. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  911. };
  912. dap4_dout_pp6 {
  913. nvidia,pins = "dap4_dout_pp6";
  914. nvidia,function = "i2s3";
  915. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  916. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  917. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  918. };
  919. dap4_sclk_pp7 {
  920. nvidia,pins = "dap4_sclk_pp7";
  921. nvidia,function = "i2s3";
  922. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  923. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  924. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  925. };
  926. kb_col0_pq0 {
  927. nvidia,pins = "kb_col0_pq0";
  928. nvidia,function = "kbc";
  929. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  930. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  931. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  932. };
  933. kb_col1_pq1 {
  934. nvidia,pins = "kb_col1_pq1";
  935. nvidia,function = "kbc";
  936. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  937. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  938. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  939. };
  940. kb_col2_pq2 {
  941. nvidia,pins = "kb_col2_pq2";
  942. nvidia,function = "kbc";
  943. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  944. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  945. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  946. };
  947. kb_col3_pq3 {
  948. nvidia,pins = "kb_col3_pq3";
  949. nvidia,function = "kbc";
  950. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  951. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  952. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  953. };
  954. kb_col4_pq4 {
  955. nvidia,pins = "kb_col4_pq4";
  956. nvidia,function = "kbc";
  957. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  958. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  959. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  960. };
  961. kb_col5_pq5 {
  962. nvidia,pins = "kb_col5_pq5";
  963. nvidia,function = "kbc";
  964. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  965. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  966. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  967. };
  968. kb_col6_pq6 {
  969. nvidia,pins = "kb_col6_pq6";
  970. nvidia,function = "kbc";
  971. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  972. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  973. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  974. };
  975. kb_col7_pq7 {
  976. nvidia,pins = "kb_col7_pq7";
  977. nvidia,function = "kbc";
  978. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  979. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  980. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  981. };
  982. kb_row0_pr0 {
  983. nvidia,pins = "kb_row0_pr0";
  984. nvidia,function = "kbc";
  985. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  986. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  987. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  988. };
  989. kb_row1_pr1 {
  990. nvidia,pins = "kb_row1_pr1";
  991. nvidia,function = "kbc";
  992. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  993. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  994. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  995. };
  996. kb_row2_pr2 {
  997. nvidia,pins = "kb_row2_pr2";
  998. nvidia,function = "kbc";
  999. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1000. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1001. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1002. };
  1003. kb_row3_pr3 {
  1004. nvidia,pins = "kb_row3_pr3";
  1005. nvidia,function = "kbc";
  1006. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1007. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1008. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1009. };
  1010. kb_row4_pr4 {
  1011. nvidia,pins = "kb_row4_pr4";
  1012. nvidia,function = "kbc";
  1013. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1014. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1015. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1016. };
  1017. kb_row5_pr5 {
  1018. nvidia,pins = "kb_row5_pr5";
  1019. nvidia,function = "kbc";
  1020. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1021. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1022. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1023. };
  1024. kb_row6_pr6 {
  1025. nvidia,pins = "kb_row6_pr6";
  1026. nvidia,function = "kbc";
  1027. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1028. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1029. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1030. };
  1031. kb_row7_pr7 {
  1032. nvidia,pins = "kb_row7_pr7";
  1033. nvidia,function = "kbc";
  1034. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1035. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1036. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1037. };
  1038. kb_row8_ps0 {
  1039. nvidia,pins = "kb_row8_ps0";
  1040. nvidia,function = "kbc";
  1041. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1042. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1043. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1044. };
  1045. kb_row9_ps1 {
  1046. nvidia,pins = "kb_row9_ps1";
  1047. nvidia,function = "kbc";
  1048. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1049. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1050. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1051. };
  1052. kb_row10_ps2 {
  1053. nvidia,pins = "kb_row10_ps2";
  1054. nvidia,function = "kbc";
  1055. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1056. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1057. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1058. };
  1059. kb_row11_ps3 {
  1060. nvidia,pins = "kb_row11_ps3";
  1061. nvidia,function = "kbc";
  1062. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1063. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1064. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1065. };
  1066. kb_row12_ps4 {
  1067. nvidia,pins = "kb_row12_ps4";
  1068. nvidia,function = "kbc";
  1069. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1070. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1071. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1072. };
  1073. kb_row13_ps5 {
  1074. nvidia,pins = "kb_row13_ps5";
  1075. nvidia,function = "kbc";
  1076. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1077. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1078. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1079. };
  1080. kb_row14_ps6 {
  1081. nvidia,pins = "kb_row14_ps6";
  1082. nvidia,function = "kbc";
  1083. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1084. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1085. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1086. };
  1087. kb_row15_ps7 {
  1088. nvidia,pins = "kb_row15_ps7";
  1089. nvidia,function = "kbc";
  1090. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1091. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1092. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1093. };
  1094. vi_pclk_pt0 {
  1095. nvidia,pins = "vi_pclk_pt0";
  1096. nvidia,function = "rsvd1";
  1097. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1098. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1099. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1100. };
  1101. vi_mclk_pt1 {
  1102. nvidia,pins = "vi_mclk_pt1";
  1103. nvidia,function = "vi";
  1104. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1105. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1106. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1107. };
  1108. vi_d10_pt2 {
  1109. nvidia,pins = "vi_d10_pt2";
  1110. nvidia,function = "ddr";
  1111. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1112. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1113. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1114. };
  1115. vi_d11_pt3 {
  1116. nvidia,pins = "vi_d11_pt3";
  1117. nvidia,function = "ddr";
  1118. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1119. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1120. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1121. };
  1122. vi_d0_pt4 {
  1123. nvidia,pins = "vi_d0_pt4";
  1124. nvidia,function = "ddr";
  1125. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1126. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1127. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1128. };
  1129. gen2_i2c_scl_pt5 {
  1130. nvidia,pins = "gen2_i2c_scl_pt5";
  1131. nvidia,function = "i2c2";
  1132. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1133. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1134. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1135. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1136. };
  1137. gen2_i2c_sda_pt6 {
  1138. nvidia,pins = "gen2_i2c_sda_pt6";
  1139. nvidia,function = "i2c2";
  1140. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1141. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1142. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1143. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1144. };
  1145. sdmmc4_cmd_pt7 {
  1146. nvidia,pins = "sdmmc4_cmd_pt7";
  1147. nvidia,function = "sdmmc4";
  1148. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1149. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1150. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1151. nvidia,io-reset = <TEGRA_PIN_DISABLE>;
  1152. };
  1153. pu0 {
  1154. nvidia,pins = "pu0";
  1155. nvidia,function = "owr";
  1156. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1157. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1158. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1159. };
  1160. pu1 {
  1161. nvidia,pins = "pu1";
  1162. nvidia,function = "rsvd1";
  1163. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1164. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1165. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1166. };
  1167. pu2 {
  1168. nvidia,pins = "pu2";
  1169. nvidia,function = "rsvd1";
  1170. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1171. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1172. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1173. };
  1174. pu3 {
  1175. nvidia,pins = "pu3";
  1176. nvidia,function = "pwm0";
  1177. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1178. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1179. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1180. };
  1181. pu4 {
  1182. nvidia,pins = "pu4";
  1183. nvidia,function = "pwm1";
  1184. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1185. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1186. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1187. };
  1188. pu5 {
  1189. nvidia,pins = "pu5";
  1190. nvidia,function = "rsvd4";
  1191. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1192. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1193. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1194. };
  1195. pu6 {
  1196. nvidia,pins = "pu6";
  1197. nvidia,function = "pwm3";
  1198. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1199. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1200. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1201. };
  1202. jtag_rtck_pu7 {
  1203. nvidia,pins = "jtag_rtck_pu7";
  1204. nvidia,function = "rtck";
  1205. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1206. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1207. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1208. };
  1209. pv0 {
  1210. nvidia,pins = "pv0";
  1211. nvidia,function = "rsvd1";
  1212. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1213. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1214. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1215. };
  1216. pv1 {
  1217. nvidia,pins = "pv1";
  1218. nvidia,function = "rsvd1";
  1219. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1220. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1221. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1222. };
  1223. pv2 {
  1224. nvidia,pins = "pv2";
  1225. nvidia,function = "owr";
  1226. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1227. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1228. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1229. };
  1230. pv3 {
  1231. nvidia,pins = "pv3";
  1232. nvidia,function = "clk_12m_out";
  1233. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1234. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1235. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1236. };
  1237. ddc_scl_pv4 {
  1238. nvidia,pins = "ddc_scl_pv4";
  1239. nvidia,function = "i2c4";
  1240. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1241. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1242. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1243. };
  1244. ddc_sda_pv5 {
  1245. nvidia,pins = "ddc_sda_pv5";
  1246. nvidia,function = "i2c4";
  1247. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1248. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1249. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1250. };
  1251. crt_hsync_pv6 {
  1252. nvidia,pins = "crt_hsync_pv6";
  1253. nvidia,function = "crt";
  1254. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1255. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1256. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1257. };
  1258. crt_vsync_pv7 {
  1259. nvidia,pins = "crt_vsync_pv7";
  1260. nvidia,function = "crt";
  1261. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1262. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1263. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1264. };
  1265. lcd_cs1_n_pw0 {
  1266. nvidia,pins = "lcd_cs1_n_pw0";
  1267. nvidia,function = "displaya";
  1268. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1269. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1270. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1271. };
  1272. lcd_m1_pw1 {
  1273. nvidia,pins = "lcd_m1_pw1";
  1274. nvidia,function = "displaya";
  1275. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1276. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1277. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1278. };
  1279. spi2_cs1_n_pw2 {
  1280. nvidia,pins = "spi2_cs1_n_pw2";
  1281. nvidia,function = "spi2";
  1282. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1283. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1284. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1285. };
  1286. clk1_out_pw4 {
  1287. nvidia,pins = "clk1_out_pw4";
  1288. nvidia,function = "extperiph1";
  1289. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1290. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1291. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1292. };
  1293. clk2_out_pw5 {
  1294. nvidia,pins = "clk2_out_pw5";
  1295. nvidia,function = "extperiph2";
  1296. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1297. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1298. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1299. };
  1300. uart3_txd_pw6 {
  1301. nvidia,pins = "uart3_txd_pw6";
  1302. nvidia,function = "uartc";
  1303. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1304. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1305. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1306. };
  1307. uart3_rxd_pw7 {
  1308. nvidia,pins = "uart3_rxd_pw7";
  1309. nvidia,function = "uartc";
  1310. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1311. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1312. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1313. };
  1314. spi2_sck_px2 {
  1315. nvidia,pins = "spi2_sck_px2";
  1316. nvidia,function = "gmi";
  1317. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1318. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1319. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1320. };
  1321. spi1_mosi_px4 {
  1322. nvidia,pins = "spi1_mosi_px4";
  1323. nvidia,function = "spi1";
  1324. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1325. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1326. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1327. };
  1328. spi1_sck_px5 {
  1329. nvidia,pins = "spi1_sck_px5";
  1330. nvidia,function = "spi1";
  1331. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1332. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1333. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1334. };
  1335. spi1_cs0_n_px6 {
  1336. nvidia,pins = "spi1_cs0_n_px6";
  1337. nvidia,function = "spi1";
  1338. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1339. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1340. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1341. };
  1342. spi1_miso_px7 {
  1343. nvidia,pins = "spi1_miso_px7";
  1344. nvidia,function = "spi1";
  1345. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1346. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1347. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1348. };
  1349. ulpi_clk_py0 {
  1350. nvidia,pins = "ulpi_clk_py0";
  1351. nvidia,function = "uartd";
  1352. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1353. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1354. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1355. };
  1356. ulpi_dir_py1 {
  1357. nvidia,pins = "ulpi_dir_py1";
  1358. nvidia,function = "uartd";
  1359. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1360. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1361. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1362. };
  1363. ulpi_nxt_py2 {
  1364. nvidia,pins = "ulpi_nxt_py2";
  1365. nvidia,function = "uartd";
  1366. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1367. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1368. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1369. };
  1370. ulpi_stp_py3 {
  1371. nvidia,pins = "ulpi_stp_py3";
  1372. nvidia,function = "uartd";
  1373. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1374. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1375. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1376. };
  1377. sdmmc1_dat3_py4 {
  1378. nvidia,pins = "sdmmc1_dat3_py4";
  1379. nvidia,function = "sdmmc1";
  1380. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1381. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1382. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1383. };
  1384. sdmmc1_dat2_py5 {
  1385. nvidia,pins = "sdmmc1_dat2_py5";
  1386. nvidia,function = "sdmmc1";
  1387. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1388. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1389. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1390. };
  1391. sdmmc1_dat1_py6 {
  1392. nvidia,pins = "sdmmc1_dat1_py6";
  1393. nvidia,function = "sdmmc1";
  1394. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1395. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1396. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1397. };
  1398. sdmmc1_dat0_py7 {
  1399. nvidia,pins = "sdmmc1_dat0_py7";
  1400. nvidia,function = "sdmmc1";
  1401. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1402. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1403. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1404. };
  1405. sdmmc1_clk_pz0 {
  1406. nvidia,pins = "sdmmc1_clk_pz0";
  1407. nvidia,function = "sdmmc1";
  1408. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1409. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1410. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1411. };
  1412. sdmmc1_cmd_pz1 {
  1413. nvidia,pins = "sdmmc1_cmd_pz1";
  1414. nvidia,function = "sdmmc1";
  1415. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1416. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1417. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1418. };
  1419. lcd_sdin_pz2 {
  1420. nvidia,pins = "lcd_sdin_pz2";
  1421. nvidia,function = "displaya";
  1422. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1423. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1424. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1425. };
  1426. lcd_wr_n_pz3 {
  1427. nvidia,pins = "lcd_wr_n_pz3";
  1428. nvidia,function = "displaya";
  1429. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1430. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1431. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1432. };
  1433. lcd_sck_pz4 {
  1434. nvidia,pins = "lcd_sck_pz4";
  1435. nvidia,function = "displaya";
  1436. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1437. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1438. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1439. };
  1440. sys_clk_req_pz5 {
  1441. nvidia,pins = "sys_clk_req_pz5";
  1442. nvidia,function = "sysclk";
  1443. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1444. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1445. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1446. };
  1447. pwr_i2c_scl_pz6 {
  1448. nvidia,pins = "pwr_i2c_scl_pz6";
  1449. nvidia,function = "i2cpwr";
  1450. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1451. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1452. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1453. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1454. };
  1455. pwr_i2c_sda_pz7 {
  1456. nvidia,pins = "pwr_i2c_sda_pz7";
  1457. nvidia,function = "i2cpwr";
  1458. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1459. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1460. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1461. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1462. };
  1463. sdmmc4_dat0_paa0 {
  1464. nvidia,pins = "sdmmc4_dat0_paa0";
  1465. nvidia,function = "sdmmc4";
  1466. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1467. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1468. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1469. nvidia,io-reset = <TEGRA_PIN_DISABLE>;
  1470. };
  1471. sdmmc4_dat1_paa1 {
  1472. nvidia,pins = "sdmmc4_dat1_paa1";
  1473. nvidia,function = "sdmmc4";
  1474. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1475. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1476. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1477. nvidia,io-reset = <TEGRA_PIN_DISABLE>;
  1478. };
  1479. sdmmc4_dat2_paa2 {
  1480. nvidia,pins = "sdmmc4_dat2_paa2";
  1481. nvidia,function = "sdmmc4";
  1482. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1483. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1484. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1485. nvidia,io-reset = <TEGRA_PIN_DISABLE>;
  1486. };
  1487. sdmmc4_dat3_paa3 {
  1488. nvidia,pins = "sdmmc4_dat3_paa3";
  1489. nvidia,function = "sdmmc4";
  1490. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1491. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1492. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1493. nvidia,io-reset = <TEGRA_PIN_DISABLE>;
  1494. };
  1495. sdmmc4_dat4_paa4 {
  1496. nvidia,pins = "sdmmc4_dat4_paa4";
  1497. nvidia,function = "sdmmc4";
  1498. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1499. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1500. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1501. nvidia,io-reset = <TEGRA_PIN_DISABLE>;
  1502. };
  1503. sdmmc4_dat5_paa5 {
  1504. nvidia,pins = "sdmmc4_dat5_paa5";
  1505. nvidia,function = "sdmmc4";
  1506. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1507. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1508. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1509. nvidia,io-reset = <TEGRA_PIN_DISABLE>;
  1510. };
  1511. sdmmc4_dat6_paa6 {
  1512. nvidia,pins = "sdmmc4_dat6_paa6";
  1513. nvidia,function = "sdmmc4";
  1514. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1515. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1516. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1517. nvidia,io-reset = <TEGRA_PIN_DISABLE>;
  1518. };
  1519. sdmmc4_dat7_paa7 {
  1520. nvidia,pins = "sdmmc4_dat7_paa7";
  1521. nvidia,function = "sdmmc4";
  1522. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1523. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1524. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1525. nvidia,io-reset = <TEGRA_PIN_DISABLE>;
  1526. };
  1527. pbb0 {
  1528. nvidia,pins = "pbb0";
  1529. nvidia,function = "i2s4";
  1530. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1531. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1532. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1533. };
  1534. cam_i2c_scl_pbb1 {
  1535. nvidia,pins = "cam_i2c_scl_pbb1";
  1536. nvidia,function = "i2c3";
  1537. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1538. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1539. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1540. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1541. };
  1542. cam_i2c_sda_pbb2 {
  1543. nvidia,pins = "cam_i2c_sda_pbb2";
  1544. nvidia,function = "i2c3";
  1545. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1546. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1547. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1548. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1549. };
  1550. pbb3 {
  1551. nvidia,pins = "pbb3";
  1552. nvidia,function = "vgp3";
  1553. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1554. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1555. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1556. };
  1557. pbb4 {
  1558. nvidia,pins = "pbb4";
  1559. nvidia,function = "vgp4";
  1560. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1561. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1562. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1563. };
  1564. pbb5 {
  1565. nvidia,pins = "pbb5";
  1566. nvidia,function = "vgp5";
  1567. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1568. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1569. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1570. };
  1571. pbb6 {
  1572. nvidia,pins = "pbb6";
  1573. nvidia,function = "vgp6";
  1574. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1575. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1576. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1577. };
  1578. pbb7 {
  1579. nvidia,pins = "pbb7";
  1580. nvidia,function = "i2s4";
  1581. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1582. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1583. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1584. };
  1585. cam_mclk_pcc0 {
  1586. nvidia,pins = "cam_mclk_pcc0";
  1587. nvidia,function = "vi_alt3";
  1588. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1589. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1590. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1591. };
  1592. pcc1 {
  1593. nvidia,pins = "pcc1";
  1594. nvidia,function = "i2s4";
  1595. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1596. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1597. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1598. };
  1599. pcc2 {
  1600. nvidia,pins = "pcc2";
  1601. nvidia,function = "i2s4";
  1602. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1603. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1604. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1605. };
  1606. sdmmc4_rst_n_pcc3 {
  1607. nvidia,pins = "sdmmc4_rst_n_pcc3";
  1608. nvidia,function = "sdmmc4";
  1609. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1610. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1611. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1612. nvidia,io-reset = <TEGRA_PIN_DISABLE>;
  1613. };
  1614. sdmmc4_clk_pcc4 {
  1615. nvidia,pins = "sdmmc4_clk_pcc4";
  1616. nvidia,function = "sdmmc4";
  1617. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1618. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1619. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1620. nvidia,io-reset = <TEGRA_PIN_DISABLE>;
  1621. };
  1622. clk2_req_pcc5 {
  1623. nvidia,pins = "clk2_req_pcc5";
  1624. nvidia,function = "dap";
  1625. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1626. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1627. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1628. };
  1629. pex_l2_rst_n_pcc6 {
  1630. nvidia,pins = "pex_l2_rst_n_pcc6";
  1631. nvidia,function = "pcie";
  1632. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1633. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1634. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1635. };
  1636. pex_l2_clkreq_n_pcc7 {
  1637. nvidia,pins = "pex_l2_clkreq_n_pcc7";
  1638. nvidia,function = "pcie";
  1639. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1640. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1641. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1642. };
  1643. pex_l0_prsnt_n_pdd0 {
  1644. nvidia,pins = "pex_l0_prsnt_n_pdd0";
  1645. nvidia,function = "pcie";
  1646. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1647. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1648. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1649. };
  1650. pex_l0_rst_n_pdd1 {
  1651. nvidia,pins = "pex_l0_rst_n_pdd1";
  1652. nvidia,function = "pcie";
  1653. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1654. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1655. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1656. };
  1657. pex_l0_clkreq_n_pdd2 {
  1658. nvidia,pins = "pex_l0_clkreq_n_pdd2";
  1659. nvidia,function = "pcie";
  1660. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1661. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1662. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1663. };
  1664. pex_wake_n_pdd3 {
  1665. nvidia,pins = "pex_wake_n_pdd3";
  1666. nvidia,function = "pcie";
  1667. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1668. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1669. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1670. };
  1671. pex_l1_prsnt_n_pdd4 {
  1672. nvidia,pins = "pex_l1_prsnt_n_pdd4";
  1673. nvidia,function = "pcie";
  1674. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1675. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1676. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1677. };
  1678. pex_l1_rst_n_pdd5 {
  1679. nvidia,pins = "pex_l1_rst_n_pdd5";
  1680. nvidia,function = "pcie";
  1681. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1682. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1683. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1684. };
  1685. pex_l1_clkreq_n_pdd6 {
  1686. nvidia,pins = "pex_l1_clkreq_n_pdd6";
  1687. nvidia,function = "pcie";
  1688. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1689. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1690. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1691. };
  1692. pex_l2_prsnt_n_pdd7 {
  1693. nvidia,pins = "pex_l2_prsnt_n_pdd7";
  1694. nvidia,function = "pcie";
  1695. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1696. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1697. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1698. };
  1699. clk3_out_pee0 {
  1700. nvidia,pins = "clk3_out_pee0";
  1701. nvidia,function = "extperiph3";
  1702. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1703. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1704. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1705. };
  1706. clk3_req_pee1 {
  1707. nvidia,pins = "clk3_req_pee1";
  1708. nvidia,function = "dev3";
  1709. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1710. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1711. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1712. };
  1713. clk1_req_pee2 {
  1714. nvidia,pins = "clk1_req_pee2";
  1715. nvidia,function = "dap";
  1716. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1717. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1718. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1719. };
  1720. hdmi_cec_pee3 {
  1721. nvidia,pins = "hdmi_cec_pee3";
  1722. nvidia,function = "cec";
  1723. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1724. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1725. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1726. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1727. };
  1728. owr {
  1729. nvidia,pins = "owr";
  1730. nvidia,function = "owr";
  1731. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1732. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1733. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1734. };
  1735. drive_groups {
  1736. nvidia,pins = "drive_gma",
  1737. "drive_gmb",
  1738. "drive_gmc",
  1739. "drive_gmd";
  1740. nvidia,pull-down-strength = <9>;
  1741. nvidia,pull-up-strength = <9>;
  1742. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  1743. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  1744. };
  1745. };
  1746. };
  1747. uartc: serial@70006200 {
  1748. compatible = "nvidia,tegra30-hsuart";
  1749. /delete-property/ reg-shift;
  1750. status = "okay";
  1751. nvidia,adjust-baud-rates = <0 9600 100>,
  1752. <9600 115200 200>,
  1753. <1000000 4000000 136>;
  1754. /* Azurewave AW-NH660 BCM4330B1 */
  1755. bluetooth {
  1756. compatible = "brcm,bcm4330-bt";
  1757. interrupt-parent = <&gpio>;
  1758. interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
  1759. interrupt-names = "host-wakeup";
  1760. max-speed = <4000000>;
  1761. clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  1762. clock-names = "txco";
  1763. vbat-supply = <&sys_3v3_reg>;
  1764. vddio-supply = <&vdd_1v8>;
  1765. shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
  1766. device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
  1767. };
  1768. };
  1769. uartd: serial@70006300 {
  1770. status = "okay";
  1771. };
  1772. hdmi_ddc: i2c@7000c700 {
  1773. status = "okay";
  1774. clock-frequency = <100000>;
  1775. };
  1776. i2c@7000d000 {
  1777. status = "okay";
  1778. clock-frequency = <400000>;
  1779. cpu_temp: nct1008@4c {
  1780. compatible = "onnn,nct1008";
  1781. reg = <0x4c>;
  1782. vcc-supply = <&sys_3v3_reg>;
  1783. interrupt-parent = <&gpio>;
  1784. interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
  1785. #thermal-sensor-cells = <1>;
  1786. };
  1787. pmic: pmic@2d {
  1788. compatible = "ti,tps65911";
  1789. reg = <0x2d>;
  1790. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  1791. #interrupt-cells = <2>;
  1792. interrupt-controller;
  1793. wakeup-source;
  1794. ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>;
  1795. ti,system-power-controller;
  1796. ti,sleep-keep-ck32k;
  1797. ti,sleep-enable;
  1798. #gpio-cells = <2>;
  1799. gpio-controller;
  1800. vcc1-supply = <&vdd_5v0_reg>;
  1801. vcc2-supply = <&vdd_5v0_reg>;
  1802. vcc3-supply = <&vdd_1v8>;
  1803. vcc4-supply = <&vdd_5v0_reg>;
  1804. vcc5-supply = <&vdd_5v0_reg>;
  1805. vcc6-supply = <&vdd2_reg>;
  1806. vcc7-supply = <&vdd_5v0_reg>;
  1807. vccio-supply = <&vdd_5v0_reg>;
  1808. regulators {
  1809. vdd1_reg: vdd1 {
  1810. regulator-name = "vddio_ddr_1v2";
  1811. regulator-min-microvolt = <1200000>;
  1812. regulator-max-microvolt = <1200000>;
  1813. regulator-always-on;
  1814. };
  1815. vdd2_reg: vdd2 {
  1816. regulator-name = "vdd_1v5_gen";
  1817. regulator-min-microvolt = <1500000>;
  1818. regulator-max-microvolt = <1500000>;
  1819. regulator-always-on;
  1820. };
  1821. vdd_cpu: vddctrl {
  1822. regulator-name = "vdd_cpu,vdd_sys";
  1823. regulator-min-microvolt = <800000>;
  1824. regulator-max-microvolt = <1270000>;
  1825. regulator-coupled-with = <&vdd_core>;
  1826. regulator-coupled-max-spread = <300000>;
  1827. regulator-max-step-microvolt = <100000>;
  1828. regulator-always-on;
  1829. nvidia,tegra-cpu-regulator;
  1830. };
  1831. vdd_1v8: vio {
  1832. regulator-name = "vdd_1v8_gen";
  1833. regulator-min-microvolt = <1800000>;
  1834. regulator-max-microvolt = <1800000>;
  1835. regulator-always-on;
  1836. };
  1837. ldo1_reg: ldo1 {
  1838. regulator-name = "vdd_pexa,vdd_pexb";
  1839. regulator-min-microvolt = <1050000>;
  1840. regulator-max-microvolt = <1050000>;
  1841. regulator-always-on;
  1842. };
  1843. ldo2_reg: ldo2 {
  1844. regulator-name = "vdd_sata,avdd_plle";
  1845. regulator-min-microvolt = <1050000>;
  1846. regulator-max-microvolt = <1050000>;
  1847. regulator-always-on;
  1848. };
  1849. /* LDO3 is not connected to anything */
  1850. ldo4_reg: ldo4 {
  1851. regulator-name = "vdd_rtc";
  1852. regulator-min-microvolt = <1200000>;
  1853. regulator-max-microvolt = <1200000>;
  1854. regulator-always-on;
  1855. };
  1856. ldo5_reg: ldo5 {
  1857. regulator-name = "vddio_sdmmc,avdd_vdac";
  1858. regulator-min-microvolt = <1800000>;
  1859. regulator-max-microvolt = <3300000>;
  1860. regulator-always-on;
  1861. };
  1862. ldo6_reg: ldo6 {
  1863. regulator-name = "avdd_dsi_csi,pwrdet_mipi";
  1864. regulator-min-microvolt = <1200000>;
  1865. regulator-max-microvolt = <1200000>;
  1866. regulator-always-on;
  1867. };
  1868. ldo7_reg: ldo7 {
  1869. regulator-name = "vdd_pllm,x,u,a_p_c_s";
  1870. regulator-min-microvolt = <1200000>;
  1871. regulator-max-microvolt = <1200000>;
  1872. regulator-always-on;
  1873. };
  1874. ldo8_reg: ldo8 {
  1875. regulator-name = "vdd_ddr_hs";
  1876. regulator-min-microvolt = <1000000>;
  1877. regulator-max-microvolt = <1000000>;
  1878. regulator-always-on;
  1879. };
  1880. };
  1881. };
  1882. vdd_core: tps62361@60 {
  1883. compatible = "ti,tps62361";
  1884. reg = <0x60>;
  1885. regulator-name = "vdd_core";
  1886. regulator-min-microvolt = <950000>;
  1887. regulator-max-microvolt = <1350000>;
  1888. regulator-coupled-with = <&vdd_cpu>;
  1889. regulator-coupled-max-spread = <300000>;
  1890. regulator-max-step-microvolt = <100000>;
  1891. regulator-boot-on;
  1892. regulator-always-on;
  1893. ti,vsel0-state-high;
  1894. ti,vsel1-state-high;
  1895. ti,enable-vout-discharge;
  1896. nvidia,tegra-core-regulator;
  1897. };
  1898. };
  1899. pmc@7000e400 {
  1900. status = "okay";
  1901. nvidia,invert-interrupt;
  1902. nvidia,suspend-mode = <1>;
  1903. nvidia,cpu-pwr-good-time = <2000>;
  1904. nvidia,cpu-pwr-off-time = <200>;
  1905. nvidia,core-pwr-good-time = <3845 3845>;
  1906. nvidia,core-pwr-off-time = <458>;
  1907. nvidia,core-power-req-active-high;
  1908. nvidia,sys-clock-req-active-high;
  1909. core-supply = <&vdd_core>;
  1910. };
  1911. memory-controller@7000f000 {
  1912. emc-timings-0 {
  1913. nvidia,ram-code = <0>; /* Samsung RAM */
  1914. timing-25500000 {
  1915. clock-frequency = <25500000>;
  1916. nvidia,emem-configuration = <
  1917. 0x00030003 /* MC_EMEM_ARB_CFG */
  1918. 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  1919. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  1920. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  1921. 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
  1922. 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
  1923. 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
  1924. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  1925. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  1926. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  1927. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  1928. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  1929. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  1930. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  1931. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  1932. 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
  1933. 0x75830303 /* MC_EMEM_ARB_MISC0 */
  1934. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  1935. >;
  1936. };
  1937. timing-51000000 {
  1938. clock-frequency = <51000000>;
  1939. nvidia,emem-configuration = <
  1940. 0x00010003 /* MC_EMEM_ARB_CFG */
  1941. 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  1942. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  1943. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  1944. 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
  1945. 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
  1946. 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
  1947. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  1948. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  1949. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  1950. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  1951. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  1952. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  1953. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  1954. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  1955. 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
  1956. 0x74630303 /* MC_EMEM_ARB_MISC0 */
  1957. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  1958. >;
  1959. };
  1960. timing-102000000 {
  1961. clock-frequency = <102000000>;
  1962. nvidia,emem-configuration = <
  1963. 0x00000003 /* MC_EMEM_ARB_CFG */
  1964. 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  1965. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  1966. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  1967. 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
  1968. 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
  1969. 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
  1970. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  1971. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  1972. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  1973. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  1974. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  1975. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  1976. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  1977. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  1978. 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
  1979. 0x73c30504 /* MC_EMEM_ARB_MISC0 */
  1980. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  1981. >;
  1982. };
  1983. timing-204000000 {
  1984. clock-frequency = <204000000>;
  1985. nvidia,emem-configuration = <
  1986. 0x00000006 /* MC_EMEM_ARB_CFG */
  1987. 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  1988. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  1989. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  1990. 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
  1991. 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
  1992. 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
  1993. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  1994. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  1995. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  1996. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  1997. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  1998. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  1999. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2000. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  2001. 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
  2002. 0x73840a06 /* MC_EMEM_ARB_MISC0 */
  2003. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2004. >;
  2005. };
  2006. timing-400000000 {
  2007. clock-frequency = <400000000>;
  2008. nvidia,emem-configuration = <
  2009. 0x0000000c /* MC_EMEM_ARB_CFG */
  2010. 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2011. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  2012. 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
  2013. 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
  2014. 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
  2015. 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
  2016. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  2017. 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2018. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2019. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2020. 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
  2021. 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
  2022. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2023. 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
  2024. 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
  2025. 0x7086120a /* MC_EMEM_ARB_MISC0 */
  2026. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2027. >;
  2028. };
  2029. timing-800000000 {
  2030. clock-frequency = <800000000>;
  2031. nvidia,emem-configuration = <
  2032. 0x00000018 /* MC_EMEM_ARB_CFG */
  2033. 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2034. 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
  2035. 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
  2036. 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
  2037. 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
  2038. 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
  2039. 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
  2040. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2041. 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2042. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2043. 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
  2044. 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
  2045. 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
  2046. 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
  2047. 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
  2048. 0x712c2414 /* MC_EMEM_ARB_MISC0 */
  2049. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2050. >;
  2051. };
  2052. };
  2053. emc-timings-1 {
  2054. nvidia,ram-code = <1>; /* Hynix M RAM */
  2055. timing-25500000 {
  2056. clock-frequency = <25500000>;
  2057. nvidia,emem-configuration = <
  2058. 0x00030003 /* MC_EMEM_ARB_CFG */
  2059. 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2060. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  2061. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  2062. 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
  2063. 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
  2064. 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
  2065. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  2066. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2067. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2068. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2069. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  2070. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  2071. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2072. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  2073. 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
  2074. 0x75830303 /* MC_EMEM_ARB_MISC0 */
  2075. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2076. >;
  2077. };
  2078. timing-51000000 {
  2079. clock-frequency = <51000000>;
  2080. nvidia,emem-configuration = <
  2081. 0x00010003 /* MC_EMEM_ARB_CFG */
  2082. 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2083. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  2084. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  2085. 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
  2086. 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
  2087. 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
  2088. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  2089. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2090. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2091. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2092. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  2093. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  2094. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2095. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  2096. 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
  2097. 0x74630303 /* MC_EMEM_ARB_MISC0 */
  2098. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2099. >;
  2100. };
  2101. timing-102000000 {
  2102. clock-frequency = <102000000>;
  2103. nvidia,emem-configuration = <
  2104. 0x00000003 /* MC_EMEM_ARB_CFG */
  2105. 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2106. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  2107. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  2108. 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
  2109. 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
  2110. 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
  2111. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  2112. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2113. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2114. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2115. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  2116. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  2117. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2118. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  2119. 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
  2120. 0x73c30504 /* MC_EMEM_ARB_MISC0 */
  2121. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2122. >;
  2123. };
  2124. timing-204000000 {
  2125. clock-frequency = <204000000>;
  2126. nvidia,emem-configuration = <
  2127. 0x00000006 /* MC_EMEM_ARB_CFG */
  2128. 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2129. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  2130. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  2131. 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
  2132. 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
  2133. 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
  2134. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  2135. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2136. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2137. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2138. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  2139. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  2140. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2141. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  2142. 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
  2143. 0x73840a06 /* MC_EMEM_ARB_MISC0 */
  2144. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2145. >;
  2146. };
  2147. timing-400000000 {
  2148. clock-frequency = <400000000>;
  2149. nvidia,emem-configuration = <
  2150. 0x0000000c /* MC_EMEM_ARB_CFG */
  2151. 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2152. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  2153. 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
  2154. 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
  2155. 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
  2156. 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
  2157. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  2158. 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2159. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2160. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2161. 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
  2162. 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
  2163. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2164. 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
  2165. 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
  2166. 0x7086120a /* MC_EMEM_ARB_MISC0 */
  2167. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2168. >;
  2169. };
  2170. timing-800000000 {
  2171. clock-frequency = <800000000>;
  2172. nvidia,emem-configuration = <
  2173. 0x00000018 /* MC_EMEM_ARB_CFG */
  2174. 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2175. 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
  2176. 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
  2177. 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
  2178. 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
  2179. 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
  2180. 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
  2181. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2182. 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2183. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2184. 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
  2185. 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
  2186. 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
  2187. 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
  2188. 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
  2189. 0x712c2414 /* MC_EMEM_ARB_MISC0 */
  2190. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2191. >;
  2192. };
  2193. };
  2194. emc-timings-2 {
  2195. nvidia,ram-code = <2>; /* Hynix A RAM */
  2196. timing-25500000 {
  2197. clock-frequency = <25500000>;
  2198. nvidia,emem-configuration = <
  2199. 0x00030003 /* MC_EMEM_ARB_CFG */
  2200. 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2201. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  2202. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  2203. 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
  2204. 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
  2205. 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
  2206. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  2207. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2208. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2209. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2210. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  2211. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  2212. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2213. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  2214. 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
  2215. 0x75e30303 /* MC_EMEM_ARB_MISC0 */
  2216. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2217. >;
  2218. };
  2219. timing-51000000 {
  2220. clock-frequency = <51000000>;
  2221. nvidia,emem-configuration = <
  2222. 0x00010003 /* MC_EMEM_ARB_CFG */
  2223. 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2224. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  2225. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  2226. 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
  2227. 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
  2228. 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
  2229. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  2230. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2231. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2232. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2233. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  2234. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  2235. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2236. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  2237. 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
  2238. 0x74e30303 /* MC_EMEM_ARB_MISC0 */
  2239. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2240. >;
  2241. };
  2242. timing-102000000 {
  2243. clock-frequency = <102000000>;
  2244. nvidia,emem-configuration = <
  2245. 0x00000003 /* MC_EMEM_ARB_CFG */
  2246. 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2247. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  2248. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  2249. 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
  2250. 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
  2251. 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
  2252. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  2253. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2254. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2255. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2256. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  2257. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  2258. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2259. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  2260. 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
  2261. 0x74430504 /* MC_EMEM_ARB_MISC0 */
  2262. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2263. >;
  2264. };
  2265. timing-204000000 {
  2266. clock-frequency = <204000000>;
  2267. nvidia,emem-configuration = <
  2268. 0x00000006 /* MC_EMEM_ARB_CFG */
  2269. 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2270. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  2271. 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
  2272. 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
  2273. 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
  2274. 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
  2275. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  2276. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2277. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2278. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2279. 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
  2280. 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
  2281. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2282. 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
  2283. 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
  2284. 0x74040a06 /* MC_EMEM_ARB_MISC0 */
  2285. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2286. >;
  2287. };
  2288. timing-400000000 {
  2289. clock-frequency = <400000000>;
  2290. nvidia,emem-configuration = <
  2291. 0x0000000c /* MC_EMEM_ARB_CFG */
  2292. 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2293. 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
  2294. 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
  2295. 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
  2296. 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
  2297. 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
  2298. 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
  2299. 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2300. 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2301. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2302. 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
  2303. 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
  2304. 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
  2305. 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
  2306. 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
  2307. 0x7086120a /* MC_EMEM_ARB_MISC0 */
  2308. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2309. >;
  2310. };
  2311. timing-800000000 {
  2312. clock-frequency = <800000000>;
  2313. nvidia,emem-configuration = <
  2314. 0x00000018 /* MC_EMEM_ARB_CFG */
  2315. 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
  2316. 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
  2317. 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
  2318. 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
  2319. 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
  2320. 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
  2321. 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
  2322. 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
  2323. 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
  2324. 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
  2325. 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
  2326. 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
  2327. 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
  2328. 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
  2329. 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
  2330. 0x712c2414 /* MC_EMEM_ARB_MISC0 */
  2331. 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
  2332. >;
  2333. };
  2334. };
  2335. };
  2336. memory-controller@7000f400 {
  2337. emc-timings-0 {
  2338. nvidia,ram-code = <0>; /* Samsung RAM */
  2339. timing-25500000 {
  2340. clock-frequency = <25500000>;
  2341. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2342. nvidia,emc-mode-1 = <0x80100003>;
  2343. nvidia,emc-mode-2 = <0x80200008>;
  2344. nvidia,emc-mode-reset = <0x80001221>;
  2345. nvidia,emc-zcal-cnt-long = <0x00000040>;
  2346. nvidia,emc-cfg-periodic-qrst;
  2347. nvidia,emc-cfg-dyn-self-ref;
  2348. nvidia,emc-configuration = <
  2349. 0x00000001 /* EMC_RC */
  2350. 0x00000006 /* EMC_RFC */
  2351. 0x00000000 /* EMC_RAS */
  2352. 0x00000000 /* EMC_RP */
  2353. 0x00000002 /* EMC_R2W */
  2354. 0x0000000a /* EMC_W2R */
  2355. 0x00000005 /* EMC_R2P */
  2356. 0x0000000b /* EMC_W2P */
  2357. 0x00000000 /* EMC_RD_RCD */
  2358. 0x00000000 /* EMC_WR_RCD */
  2359. 0x00000003 /* EMC_RRD */
  2360. 0x00000001 /* EMC_REXT */
  2361. 0x00000000 /* EMC_WEXT */
  2362. 0x00000005 /* EMC_WDV */
  2363. 0x00000005 /* EMC_QUSE */
  2364. 0x00000004 /* EMC_QRST */
  2365. 0x0000000a /* EMC_QSAFE */
  2366. 0x0000000b /* EMC_RDV */
  2367. 0x000000c0 /* EMC_REFRESH */
  2368. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  2369. 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
  2370. 0x00000002 /* EMC_PDEX2WR */
  2371. 0x00000002 /* EMC_PDEX2RD */
  2372. 0x00000001 /* EMC_PCHG2PDEN */
  2373. 0x00000000 /* EMC_ACT2PDEN */
  2374. 0x00000007 /* EMC_AR2PDEN */
  2375. 0x0000000f /* EMC_RW2PDEN */
  2376. 0x00000007 /* EMC_TXSR */
  2377. 0x00000007 /* EMC_TXSRDLL */
  2378. 0x00000004 /* EMC_TCKE */
  2379. 0x00000002 /* EMC_TFAW */
  2380. 0x00000000 /* EMC_TRPAB */
  2381. 0x00000004 /* EMC_TCLKSTABLE */
  2382. 0x00000005 /* EMC_TCLKSTOP */
  2383. 0x000000c7 /* EMC_TREFBW */
  2384. 0x00000006 /* EMC_QUSE_EXTRA */
  2385. 0x00000004 /* EMC_FBIO_CFG6 */
  2386. 0x00000000 /* EMC_ODT_WRITE */
  2387. 0x00000000 /* EMC_ODT_READ */
  2388. 0x00004288 /* EMC_FBIO_CFG5 */
  2389. 0x007800a4 /* EMC_CFG_DIG_DLL */
  2390. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  2391. 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
  2392. 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
  2393. 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
  2394. 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
  2395. 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
  2396. 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
  2397. 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
  2398. 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
  2399. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  2400. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  2401. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  2402. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  2403. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  2404. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  2405. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  2406. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  2407. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  2408. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  2409. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  2410. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  2411. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  2412. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  2413. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  2414. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  2415. 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
  2416. 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
  2417. 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
  2418. 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
  2419. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  2420. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  2421. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  2422. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  2423. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  2424. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  2425. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  2426. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  2427. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  2428. 0x00000802 /* EMC_CTT_TERM_CTRL */
  2429. 0x00000000 /* EMC_ZCAL_INTERVAL */
  2430. 0x00000040 /* EMC_ZCAL_WAIT_CNT */
  2431. 0x000c000c /* EMC_MRS_WAIT_CNT */
  2432. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  2433. 0x00000000 /* EMC_CTT */
  2434. 0x00000000 /* EMC_CTT_DURATION */
  2435. 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
  2436. 0xe8000000 /* EMC_FBIO_SPARE */
  2437. 0xff00ff00 /* EMC_CFG_RSV */
  2438. >;
  2439. };
  2440. timing-51000000 {
  2441. clock-frequency = <51000000>;
  2442. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2443. nvidia,emc-mode-1 = <0x80100003>;
  2444. nvidia,emc-mode-2 = <0x80200008>;
  2445. nvidia,emc-mode-reset = <0x80001221>;
  2446. nvidia,emc-zcal-cnt-long = <0x00000040>;
  2447. nvidia,emc-cfg-periodic-qrst;
  2448. nvidia,emc-cfg-dyn-self-ref;
  2449. nvidia,emc-configuration = <
  2450. 0x00000002 /* EMC_RC */
  2451. 0x0000000d /* EMC_RFC */
  2452. 0x00000001 /* EMC_RAS */
  2453. 0x00000000 /* EMC_RP */
  2454. 0x00000002 /* EMC_R2W */
  2455. 0x0000000a /* EMC_W2R */
  2456. 0x00000005 /* EMC_R2P */
  2457. 0x0000000b /* EMC_W2P */
  2458. 0x00000000 /* EMC_RD_RCD */
  2459. 0x00000000 /* EMC_WR_RCD */
  2460. 0x00000003 /* EMC_RRD */
  2461. 0x00000001 /* EMC_REXT */
  2462. 0x00000000 /* EMC_WEXT */
  2463. 0x00000005 /* EMC_WDV */
  2464. 0x00000005 /* EMC_QUSE */
  2465. 0x00000004 /* EMC_QRST */
  2466. 0x0000000a /* EMC_QSAFE */
  2467. 0x0000000b /* EMC_RDV */
  2468. 0x00000181 /* EMC_REFRESH */
  2469. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  2470. 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
  2471. 0x00000002 /* EMC_PDEX2WR */
  2472. 0x00000002 /* EMC_PDEX2RD */
  2473. 0x00000001 /* EMC_PCHG2PDEN */
  2474. 0x00000000 /* EMC_ACT2PDEN */
  2475. 0x00000007 /* EMC_AR2PDEN */
  2476. 0x0000000f /* EMC_RW2PDEN */
  2477. 0x0000000e /* EMC_TXSR */
  2478. 0x0000000e /* EMC_TXSRDLL */
  2479. 0x00000004 /* EMC_TCKE */
  2480. 0x00000003 /* EMC_TFAW */
  2481. 0x00000000 /* EMC_TRPAB */
  2482. 0x00000004 /* EMC_TCLKSTABLE */
  2483. 0x00000005 /* EMC_TCLKSTOP */
  2484. 0x0000018e /* EMC_TREFBW */
  2485. 0x00000006 /* EMC_QUSE_EXTRA */
  2486. 0x00000004 /* EMC_FBIO_CFG6 */
  2487. 0x00000000 /* EMC_ODT_WRITE */
  2488. 0x00000000 /* EMC_ODT_READ */
  2489. 0x00004288 /* EMC_FBIO_CFG5 */
  2490. 0x007800a4 /* EMC_CFG_DIG_DLL */
  2491. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  2492. 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
  2493. 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
  2494. 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
  2495. 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
  2496. 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
  2497. 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
  2498. 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
  2499. 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
  2500. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  2501. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  2502. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  2503. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  2504. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  2505. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  2506. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  2507. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  2508. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  2509. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  2510. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  2511. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  2512. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  2513. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  2514. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  2515. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  2516. 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
  2517. 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
  2518. 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
  2519. 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
  2520. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  2521. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  2522. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  2523. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  2524. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  2525. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  2526. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  2527. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  2528. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  2529. 0x00000802 /* EMC_CTT_TERM_CTRL */
  2530. 0x00000000 /* EMC_ZCAL_INTERVAL */
  2531. 0x00000040 /* EMC_ZCAL_WAIT_CNT */
  2532. 0x000c000c /* EMC_MRS_WAIT_CNT */
  2533. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  2534. 0x00000000 /* EMC_CTT */
  2535. 0x00000000 /* EMC_CTT_DURATION */
  2536. 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
  2537. 0xe8000000 /* EMC_FBIO_SPARE */
  2538. 0xff00ff00 /* EMC_CFG_RSV */
  2539. >;
  2540. };
  2541. timing-102000000 {
  2542. clock-frequency = <102000000>;
  2543. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2544. nvidia,emc-mode-1 = <0x80100003>;
  2545. nvidia,emc-mode-2 = <0x80200008>;
  2546. nvidia,emc-mode-reset = <0x80001221>;
  2547. nvidia,emc-zcal-cnt-long = <0x00000040>;
  2548. nvidia,emc-cfg-periodic-qrst;
  2549. nvidia,emc-cfg-dyn-self-ref;
  2550. nvidia,emc-configuration = <
  2551. 0x00000004 /* EMC_RC */
  2552. 0x0000001a /* EMC_RFC */
  2553. 0x00000003 /* EMC_RAS */
  2554. 0x00000001 /* EMC_RP */
  2555. 0x00000002 /* EMC_R2W */
  2556. 0x0000000a /* EMC_W2R */
  2557. 0x00000005 /* EMC_R2P */
  2558. 0x0000000b /* EMC_W2P */
  2559. 0x00000001 /* EMC_RD_RCD */
  2560. 0x00000001 /* EMC_WR_RCD */
  2561. 0x00000003 /* EMC_RRD */
  2562. 0x00000001 /* EMC_REXT */
  2563. 0x00000000 /* EMC_WEXT */
  2564. 0x00000005 /* EMC_WDV */
  2565. 0x00000005 /* EMC_QUSE */
  2566. 0x00000004 /* EMC_QRST */
  2567. 0x0000000a /* EMC_QSAFE */
  2568. 0x0000000b /* EMC_RDV */
  2569. 0x00000303 /* EMC_REFRESH */
  2570. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  2571. 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
  2572. 0x00000002 /* EMC_PDEX2WR */
  2573. 0x00000002 /* EMC_PDEX2RD */
  2574. 0x00000001 /* EMC_PCHG2PDEN */
  2575. 0x00000000 /* EMC_ACT2PDEN */
  2576. 0x00000007 /* EMC_AR2PDEN */
  2577. 0x0000000f /* EMC_RW2PDEN */
  2578. 0x0000001c /* EMC_TXSR */
  2579. 0x0000001c /* EMC_TXSRDLL */
  2580. 0x00000004 /* EMC_TCKE */
  2581. 0x00000005 /* EMC_TFAW */
  2582. 0x00000000 /* EMC_TRPAB */
  2583. 0x00000004 /* EMC_TCLKSTABLE */
  2584. 0x00000005 /* EMC_TCLKSTOP */
  2585. 0x0000031c /* EMC_TREFBW */
  2586. 0x00000006 /* EMC_QUSE_EXTRA */
  2587. 0x00000004 /* EMC_FBIO_CFG6 */
  2588. 0x00000000 /* EMC_ODT_WRITE */
  2589. 0x00000000 /* EMC_ODT_READ */
  2590. 0x00004288 /* EMC_FBIO_CFG5 */
  2591. 0x007800a4 /* EMC_CFG_DIG_DLL */
  2592. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  2593. 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
  2594. 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
  2595. 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
  2596. 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
  2597. 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
  2598. 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
  2599. 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
  2600. 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
  2601. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  2602. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  2603. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  2604. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  2605. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  2606. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  2607. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  2608. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  2609. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  2610. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  2611. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  2612. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  2613. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  2614. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  2615. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  2616. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  2617. 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
  2618. 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
  2619. 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
  2620. 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
  2621. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  2622. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  2623. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  2624. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  2625. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  2626. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  2627. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  2628. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  2629. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  2630. 0x00000802 /* EMC_CTT_TERM_CTRL */
  2631. 0x00000000 /* EMC_ZCAL_INTERVAL */
  2632. 0x00000040 /* EMC_ZCAL_WAIT_CNT */
  2633. 0x000c000c /* EMC_MRS_WAIT_CNT */
  2634. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  2635. 0x00000000 /* EMC_CTT */
  2636. 0x00000000 /* EMC_CTT_DURATION */
  2637. 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
  2638. 0xe8000000 /* EMC_FBIO_SPARE */
  2639. 0xff00ff00 /* EMC_CFG_RSV */
  2640. >;
  2641. };
  2642. timing-204000000 {
  2643. clock-frequency = <204000000>;
  2644. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2645. nvidia,emc-mode-1 = <0x80100003>;
  2646. nvidia,emc-mode-2 = <0x80200008>;
  2647. nvidia,emc-mode-reset = <0x80001221>;
  2648. nvidia,emc-zcal-cnt-long = <0x00000040>;
  2649. nvidia,emc-cfg-periodic-qrst;
  2650. nvidia,emc-cfg-dyn-self-ref;
  2651. nvidia,emc-configuration = <
  2652. 0x00000009 /* EMC_RC */
  2653. 0x00000035 /* EMC_RFC */
  2654. 0x00000007 /* EMC_RAS */
  2655. 0x00000002 /* EMC_RP */
  2656. 0x00000002 /* EMC_R2W */
  2657. 0x0000000a /* EMC_W2R */
  2658. 0x00000005 /* EMC_R2P */
  2659. 0x0000000b /* EMC_W2P */
  2660. 0x00000002 /* EMC_RD_RCD */
  2661. 0x00000002 /* EMC_WR_RCD */
  2662. 0x00000003 /* EMC_RRD */
  2663. 0x00000001 /* EMC_REXT */
  2664. 0x00000000 /* EMC_WEXT */
  2665. 0x00000005 /* EMC_WDV */
  2666. 0x00000005 /* EMC_QUSE */
  2667. 0x00000004 /* EMC_QRST */
  2668. 0x0000000a /* EMC_QSAFE */
  2669. 0x0000000b /* EMC_RDV */
  2670. 0x00000607 /* EMC_REFRESH */
  2671. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  2672. 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
  2673. 0x00000002 /* EMC_PDEX2WR */
  2674. 0x00000002 /* EMC_PDEX2RD */
  2675. 0x00000001 /* EMC_PCHG2PDEN */
  2676. 0x00000000 /* EMC_ACT2PDEN */
  2677. 0x00000007 /* EMC_AR2PDEN */
  2678. 0x0000000f /* EMC_RW2PDEN */
  2679. 0x00000038 /* EMC_TXSR */
  2680. 0x00000038 /* EMC_TXSRDLL */
  2681. 0x00000004 /* EMC_TCKE */
  2682. 0x00000009 /* EMC_TFAW */
  2683. 0x00000000 /* EMC_TRPAB */
  2684. 0x00000004 /* EMC_TCLKSTABLE */
  2685. 0x00000005 /* EMC_TCLKSTOP */
  2686. 0x00000638 /* EMC_TREFBW */
  2687. 0x00000006 /* EMC_QUSE_EXTRA */
  2688. 0x00000006 /* EMC_FBIO_CFG6 */
  2689. 0x00000000 /* EMC_ODT_WRITE */
  2690. 0x00000000 /* EMC_ODT_READ */
  2691. 0x00004288 /* EMC_FBIO_CFG5 */
  2692. 0x004400a4 /* EMC_CFG_DIG_DLL */
  2693. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  2694. 0x00080000 /* EMC_DLL_XFORM_DQS0 */
  2695. 0x00080000 /* EMC_DLL_XFORM_DQS1 */
  2696. 0x00080000 /* EMC_DLL_XFORM_DQS2 */
  2697. 0x00080000 /* EMC_DLL_XFORM_DQS3 */
  2698. 0x00080000 /* EMC_DLL_XFORM_DQS4 */
  2699. 0x00080000 /* EMC_DLL_XFORM_DQS5 */
  2700. 0x00080000 /* EMC_DLL_XFORM_DQS6 */
  2701. 0x00080000 /* EMC_DLL_XFORM_DQS7 */
  2702. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  2703. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  2704. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  2705. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  2706. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  2707. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  2708. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  2709. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  2710. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  2711. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  2712. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  2713. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  2714. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  2715. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  2716. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  2717. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  2718. 0x00080000 /* EMC_DLL_XFORM_DQ0 */
  2719. 0x00080000 /* EMC_DLL_XFORM_DQ1 */
  2720. 0x00080000 /* EMC_DLL_XFORM_DQ2 */
  2721. 0x00080000 /* EMC_DLL_XFORM_DQ3 */
  2722. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  2723. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  2724. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  2725. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  2726. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  2727. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  2728. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  2729. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  2730. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  2731. 0x00000802 /* EMC_CTT_TERM_CTRL */
  2732. 0x00020000 /* EMC_ZCAL_INTERVAL */
  2733. 0x00000100 /* EMC_ZCAL_WAIT_CNT */
  2734. 0x000c000c /* EMC_MRS_WAIT_CNT */
  2735. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  2736. 0x00000000 /* EMC_CTT */
  2737. 0x00000000 /* EMC_CTT_DURATION */
  2738. 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
  2739. 0xe8000000 /* EMC_FBIO_SPARE */
  2740. 0xff00ff00 /* EMC_CFG_RSV */
  2741. >;
  2742. };
  2743. timing-400000000 {
  2744. clock-frequency = <400000000>;
  2745. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2746. nvidia,emc-mode-1 = <0x80100002>;
  2747. nvidia,emc-mode-2 = <0x80200000>;
  2748. nvidia,emc-mode-reset = <0x80000521>;
  2749. nvidia,emc-zcal-cnt-long = <0x00000040>;
  2750. nvidia,emc-configuration = <
  2751. 0x00000012 /* EMC_RC */
  2752. 0x00000066 /* EMC_RFC */
  2753. 0x0000000c /* EMC_RAS */
  2754. 0x00000004 /* EMC_RP */
  2755. 0x00000003 /* EMC_R2W */
  2756. 0x00000008 /* EMC_W2R */
  2757. 0x00000002 /* EMC_R2P */
  2758. 0x0000000a /* EMC_W2P */
  2759. 0x00000004 /* EMC_RD_RCD */
  2760. 0x00000004 /* EMC_WR_RCD */
  2761. 0x00000002 /* EMC_RRD */
  2762. 0x00000001 /* EMC_REXT */
  2763. 0x00000000 /* EMC_WEXT */
  2764. 0x00000004 /* EMC_WDV */
  2765. 0x00000006 /* EMC_QUSE */
  2766. 0x00000004 /* EMC_QRST */
  2767. 0x0000000a /* EMC_QSAFE */
  2768. 0x0000000c /* EMC_RDV */
  2769. 0x00000bf0 /* EMC_REFRESH */
  2770. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  2771. 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
  2772. 0x00000001 /* EMC_PDEX2WR */
  2773. 0x00000008 /* EMC_PDEX2RD */
  2774. 0x00000001 /* EMC_PCHG2PDEN */
  2775. 0x00000000 /* EMC_ACT2PDEN */
  2776. 0x00000008 /* EMC_AR2PDEN */
  2777. 0x0000000f /* EMC_RW2PDEN */
  2778. 0x0000006c /* EMC_TXSR */
  2779. 0x00000200 /* EMC_TXSRDLL */
  2780. 0x00000004 /* EMC_TCKE */
  2781. 0x00000010 /* EMC_TFAW */
  2782. 0x00000000 /* EMC_TRPAB */
  2783. 0x00000004 /* EMC_TCLKSTABLE */
  2784. 0x00000005 /* EMC_TCLKSTOP */
  2785. 0x00000c30 /* EMC_TREFBW */
  2786. 0x00000000 /* EMC_QUSE_EXTRA */
  2787. 0x00000004 /* EMC_FBIO_CFG6 */
  2788. 0x00000000 /* EMC_ODT_WRITE */
  2789. 0x00000000 /* EMC_ODT_READ */
  2790. 0x00007088 /* EMC_FBIO_CFG5 */
  2791. 0x001d0084 /* EMC_CFG_DIG_DLL */
  2792. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  2793. 0x0003c000 /* EMC_DLL_XFORM_DQS0 */
  2794. 0x0003c000 /* EMC_DLL_XFORM_DQS1 */
  2795. 0x0003c000 /* EMC_DLL_XFORM_DQS2 */
  2796. 0x0003c000 /* EMC_DLL_XFORM_DQS3 */
  2797. 0x0003c000 /* EMC_DLL_XFORM_DQS4 */
  2798. 0x0003c000 /* EMC_DLL_XFORM_DQS5 */
  2799. 0x0003c000 /* EMC_DLL_XFORM_DQS6 */
  2800. 0x0003c000 /* EMC_DLL_XFORM_DQS7 */
  2801. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  2802. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  2803. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  2804. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  2805. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  2806. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  2807. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  2808. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  2809. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  2810. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  2811. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  2812. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  2813. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  2814. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  2815. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  2816. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  2817. 0x00048000 /* EMC_DLL_XFORM_DQ0 */
  2818. 0x00048000 /* EMC_DLL_XFORM_DQ1 */
  2819. 0x00048000 /* EMC_DLL_XFORM_DQ2 */
  2820. 0x00048000 /* EMC_DLL_XFORM_DQ3 */
  2821. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  2822. 0x0800013d /* EMC_XM2DQSPADCTRL2 */
  2823. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  2824. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  2825. 0x01f1f508 /* EMC_XM2COMPPADCTRL */
  2826. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  2827. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  2828. 0x080001e8 /* EMC_XM2QUSEPADCTRL */
  2829. 0x08000021 /* EMC_XM2DQSPADCTRL3 */
  2830. 0x00000802 /* EMC_CTT_TERM_CTRL */
  2831. 0x00020000 /* EMC_ZCAL_INTERVAL */
  2832. 0x00000100 /* EMC_ZCAL_WAIT_CNT */
  2833. 0x0158000c /* EMC_MRS_WAIT_CNT */
  2834. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  2835. 0x00000000 /* EMC_CTT */
  2836. 0x00000000 /* EMC_CTT_DURATION */
  2837. 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
  2838. 0xe8000000 /* EMC_FBIO_SPARE */
  2839. 0xff00ff89 /* EMC_CFG_RSV */
  2840. >;
  2841. };
  2842. timing-800000000 {
  2843. clock-frequency = <800000000>;
  2844. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2845. nvidia,emc-mode-1 = <0x80100002>;
  2846. nvidia,emc-mode-2 = <0x80200018>;
  2847. nvidia,emc-mode-reset = <0x80000d71>;
  2848. nvidia,emc-zcal-cnt-long = <0x00000040>;
  2849. nvidia,emc-cfg-periodic-qrst;
  2850. nvidia,emc-configuration = <
  2851. 0x00000025 /* EMC_RC */
  2852. 0x000000ce /* EMC_RFC */
  2853. 0x0000001a /* EMC_RAS */
  2854. 0x00000009 /* EMC_RP */
  2855. 0x00000005 /* EMC_R2W */
  2856. 0x0000000d /* EMC_W2R */
  2857. 0x00000004 /* EMC_R2P */
  2858. 0x00000013 /* EMC_W2P */
  2859. 0x00000009 /* EMC_RD_RCD */
  2860. 0x00000009 /* EMC_WR_RCD */
  2861. 0x00000004 /* EMC_RRD */
  2862. 0x00000001 /* EMC_REXT */
  2863. 0x00000000 /* EMC_WEXT */
  2864. 0x00000007 /* EMC_WDV */
  2865. 0x0000000a /* EMC_QUSE */
  2866. 0x00000009 /* EMC_QRST */
  2867. 0x0000000b /* EMC_QSAFE */
  2868. 0x00000011 /* EMC_RDV */
  2869. 0x00001820 /* EMC_REFRESH */
  2870. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  2871. 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
  2872. 0x00000003 /* EMC_PDEX2WR */
  2873. 0x00000012 /* EMC_PDEX2RD */
  2874. 0x00000001 /* EMC_PCHG2PDEN */
  2875. 0x00000000 /* EMC_ACT2PDEN */
  2876. 0x0000000f /* EMC_AR2PDEN */
  2877. 0x00000018 /* EMC_RW2PDEN */
  2878. 0x000000d8 /* EMC_TXSR */
  2879. 0x00000200 /* EMC_TXSRDLL */
  2880. 0x00000005 /* EMC_TCKE */
  2881. 0x00000020 /* EMC_TFAW */
  2882. 0x00000000 /* EMC_TRPAB */
  2883. 0x00000007 /* EMC_TCLKSTABLE */
  2884. 0x00000008 /* EMC_TCLKSTOP */
  2885. 0x00001860 /* EMC_TREFBW */
  2886. 0x0000000b /* EMC_QUSE_EXTRA */
  2887. 0x00000006 /* EMC_FBIO_CFG6 */
  2888. 0x00000000 /* EMC_ODT_WRITE */
  2889. 0x00000000 /* EMC_ODT_READ */
  2890. 0x00005088 /* EMC_FBIO_CFG5 */
  2891. 0xf0070191 /* EMC_CFG_DIG_DLL */
  2892. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  2893. 0x0000800a /* EMC_DLL_XFORM_DQS0 */
  2894. 0x0000000a /* EMC_DLL_XFORM_DQS1 */
  2895. 0x0000000a /* EMC_DLL_XFORM_DQS2 */
  2896. 0x0000000a /* EMC_DLL_XFORM_DQS3 */
  2897. 0x0000000a /* EMC_DLL_XFORM_DQS4 */
  2898. 0x0000000a /* EMC_DLL_XFORM_DQS5 */
  2899. 0x0000000a /* EMC_DLL_XFORM_DQS6 */
  2900. 0x0000000a /* EMC_DLL_XFORM_DQS7 */
  2901. 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
  2902. 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
  2903. 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
  2904. 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
  2905. 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
  2906. 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
  2907. 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
  2908. 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
  2909. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  2910. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  2911. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  2912. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  2913. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  2914. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  2915. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  2916. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  2917. 0x0000000a /* EMC_DLL_XFORM_DQ0 */
  2918. 0x0000000a /* EMC_DLL_XFORM_DQ1 */
  2919. 0x0000000a /* EMC_DLL_XFORM_DQ2 */
  2920. 0x0000000a /* EMC_DLL_XFORM_DQ3 */
  2921. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  2922. 0x0600013d /* EMC_XM2DQSPADCTRL2 */
  2923. 0x22220000 /* EMC_XM2DQPADCTRL2 */
  2924. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  2925. 0x01f1f501 /* EMC_XM2COMPPADCTRL */
  2926. 0x07077404 /* EMC_XM2VTTGENPADCTRL */
  2927. 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
  2928. 0x080001e8 /* EMC_XM2QUSEPADCTRL */
  2929. 0x08000021 /* EMC_XM2DQSPADCTRL3 */
  2930. 0x00000802 /* EMC_CTT_TERM_CTRL */
  2931. 0x00020000 /* EMC_ZCAL_INTERVAL */
  2932. 0x00000100 /* EMC_ZCAL_WAIT_CNT */
  2933. 0x00f0000c /* EMC_MRS_WAIT_CNT */
  2934. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  2935. 0x00000000 /* EMC_CTT */
  2936. 0x00000000 /* EMC_CTT_DURATION */
  2937. 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
  2938. 0xe8000000 /* EMC_FBIO_SPARE */
  2939. 0xff00ff49 /* EMC_CFG_RSV */
  2940. >;
  2941. };
  2942. };
  2943. emc-timings-1 {
  2944. nvidia,ram-code = <1>; /* Hynix M RAM */
  2945. timing-25500000 {
  2946. clock-frequency = <25500000>;
  2947. nvidia,emc-auto-cal-interval = <0x001fffff>;
  2948. nvidia,emc-mode-1 = <0x80100003>;
  2949. nvidia,emc-mode-2 = <0x80200008>;
  2950. nvidia,emc-mode-reset = <0x80001221>;
  2951. nvidia,emc-zcal-cnt-long = <0x00000040>;
  2952. nvidia,emc-cfg-periodic-qrst;
  2953. nvidia,emc-cfg-dyn-self-ref;
  2954. nvidia,emc-configuration = <
  2955. 0x00000001 /* EMC_RC */
  2956. 0x00000006 /* EMC_RFC */
  2957. 0x00000000 /* EMC_RAS */
  2958. 0x00000000 /* EMC_RP */
  2959. 0x00000002 /* EMC_R2W */
  2960. 0x0000000a /* EMC_W2R */
  2961. 0x00000005 /* EMC_R2P */
  2962. 0x0000000b /* EMC_W2P */
  2963. 0x00000000 /* EMC_RD_RCD */
  2964. 0x00000000 /* EMC_WR_RCD */
  2965. 0x00000003 /* EMC_RRD */
  2966. 0x00000001 /* EMC_REXT */
  2967. 0x00000000 /* EMC_WEXT */
  2968. 0x00000005 /* EMC_WDV */
  2969. 0x00000005 /* EMC_QUSE */
  2970. 0x00000004 /* EMC_QRST */
  2971. 0x0000000a /* EMC_QSAFE */
  2972. 0x0000000b /* EMC_RDV */
  2973. 0x000000c0 /* EMC_REFRESH */
  2974. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  2975. 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
  2976. 0x00000002 /* EMC_PDEX2WR */
  2977. 0x00000002 /* EMC_PDEX2RD */
  2978. 0x00000001 /* EMC_PCHG2PDEN */
  2979. 0x00000000 /* EMC_ACT2PDEN */
  2980. 0x00000007 /* EMC_AR2PDEN */
  2981. 0x0000000f /* EMC_RW2PDEN */
  2982. 0x00000007 /* EMC_TXSR */
  2983. 0x00000007 /* EMC_TXSRDLL */
  2984. 0x00000004 /* EMC_TCKE */
  2985. 0x00000002 /* EMC_TFAW */
  2986. 0x00000000 /* EMC_TRPAB */
  2987. 0x00000004 /* EMC_TCLKSTABLE */
  2988. 0x00000005 /* EMC_TCLKSTOP */
  2989. 0x000000c7 /* EMC_TREFBW */
  2990. 0x00000006 /* EMC_QUSE_EXTRA */
  2991. 0x00000004 /* EMC_FBIO_CFG6 */
  2992. 0x00000000 /* EMC_ODT_WRITE */
  2993. 0x00000000 /* EMC_ODT_READ */
  2994. 0x00004288 /* EMC_FBIO_CFG5 */
  2995. 0x007800a4 /* EMC_CFG_DIG_DLL */
  2996. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  2997. 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
  2998. 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
  2999. 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
  3000. 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
  3001. 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
  3002. 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
  3003. 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
  3004. 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
  3005. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  3006. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  3007. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  3008. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  3009. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  3010. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  3011. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  3012. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  3013. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  3014. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  3015. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  3016. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  3017. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  3018. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  3019. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  3020. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  3021. 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
  3022. 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
  3023. 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
  3024. 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
  3025. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  3026. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  3027. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  3028. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  3029. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  3030. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  3031. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  3032. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  3033. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  3034. 0x00000802 /* EMC_CTT_TERM_CTRL */
  3035. 0x00000000 /* EMC_ZCAL_INTERVAL */
  3036. 0x00000040 /* EMC_ZCAL_WAIT_CNT */
  3037. 0x000c000c /* EMC_MRS_WAIT_CNT */
  3038. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  3039. 0x00000000 /* EMC_CTT */
  3040. 0x00000000 /* EMC_CTT_DURATION */
  3041. 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
  3042. 0xe8000000 /* EMC_FBIO_SPARE */
  3043. 0xff00ff00 /* EMC_CFG_RSV */
  3044. >;
  3045. };
  3046. timing-51000000 {
  3047. clock-frequency = <51000000>;
  3048. nvidia,emc-auto-cal-interval = <0x001fffff>;
  3049. nvidia,emc-mode-1 = <0x80100003>;
  3050. nvidia,emc-mode-2 = <0x80200008>;
  3051. nvidia,emc-mode-reset = <0x80001221>;
  3052. nvidia,emc-zcal-cnt-long = <0x00000040>;
  3053. nvidia,emc-cfg-periodic-qrst;
  3054. nvidia,emc-cfg-dyn-self-ref;
  3055. nvidia,emc-configuration = <
  3056. 0x00000002 /* EMC_RC */
  3057. 0x0000000d /* EMC_RFC */
  3058. 0x00000001 /* EMC_RAS */
  3059. 0x00000000 /* EMC_RP */
  3060. 0x00000002 /* EMC_R2W */
  3061. 0x0000000a /* EMC_W2R */
  3062. 0x00000005 /* EMC_R2P */
  3063. 0x0000000b /* EMC_W2P */
  3064. 0x00000000 /* EMC_RD_RCD */
  3065. 0x00000000 /* EMC_WR_RCD */
  3066. 0x00000003 /* EMC_RRD */
  3067. 0x00000001 /* EMC_REXT */
  3068. 0x00000000 /* EMC_WEXT */
  3069. 0x00000005 /* EMC_WDV */
  3070. 0x00000005 /* EMC_QUSE */
  3071. 0x00000004 /* EMC_QRST */
  3072. 0x0000000a /* EMC_QSAFE */
  3073. 0x0000000b /* EMC_RDV */
  3074. 0x00000181 /* EMC_REFRESH */
  3075. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  3076. 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
  3077. 0x00000002 /* EMC_PDEX2WR */
  3078. 0x00000002 /* EMC_PDEX2RD */
  3079. 0x00000001 /* EMC_PCHG2PDEN */
  3080. 0x00000000 /* EMC_ACT2PDEN */
  3081. 0x00000007 /* EMC_AR2PDEN */
  3082. 0x0000000f /* EMC_RW2PDEN */
  3083. 0x0000000e /* EMC_TXSR */
  3084. 0x0000000e /* EMC_TXSRDLL */
  3085. 0x00000004 /* EMC_TCKE */
  3086. 0x00000003 /* EMC_TFAW */
  3087. 0x00000000 /* EMC_TRPAB */
  3088. 0x00000004 /* EMC_TCLKSTABLE */
  3089. 0x00000005 /* EMC_TCLKSTOP */
  3090. 0x0000018e /* EMC_TREFBW */
  3091. 0x00000006 /* EMC_QUSE_EXTRA */
  3092. 0x00000004 /* EMC_FBIO_CFG6 */
  3093. 0x00000000 /* EMC_ODT_WRITE */
  3094. 0x00000000 /* EMC_ODT_READ */
  3095. 0x00004288 /* EMC_FBIO_CFG5 */
  3096. 0x007800a4 /* EMC_CFG_DIG_DLL */
  3097. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  3098. 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
  3099. 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
  3100. 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
  3101. 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
  3102. 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
  3103. 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
  3104. 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
  3105. 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
  3106. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  3107. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  3108. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  3109. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  3110. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  3111. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  3112. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  3113. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  3114. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  3115. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  3116. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  3117. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  3118. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  3119. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  3120. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  3121. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  3122. 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
  3123. 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
  3124. 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
  3125. 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
  3126. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  3127. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  3128. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  3129. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  3130. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  3131. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  3132. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  3133. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  3134. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  3135. 0x00000802 /* EMC_CTT_TERM_CTRL */
  3136. 0x00000000 /* EMC_ZCAL_INTERVAL */
  3137. 0x00000040 /* EMC_ZCAL_WAIT_CNT */
  3138. 0x000c000c /* EMC_MRS_WAIT_CNT */
  3139. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  3140. 0x00000000 /* EMC_CTT */
  3141. 0x00000000 /* EMC_CTT_DURATION */
  3142. 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
  3143. 0xe8000000 /* EMC_FBIO_SPARE */
  3144. 0xff00ff00 /* EMC_CFG_RSV */
  3145. >;
  3146. };
  3147. timing-102000000 {
  3148. clock-frequency = <102000000>;
  3149. nvidia,emc-auto-cal-interval = <0x001fffff>;
  3150. nvidia,emc-mode-1 = <0x80100003>;
  3151. nvidia,emc-mode-2 = <0x80200008>;
  3152. nvidia,emc-mode-reset = <0x80001221>;
  3153. nvidia,emc-zcal-cnt-long = <0x00000040>;
  3154. nvidia,emc-cfg-periodic-qrst;
  3155. nvidia,emc-cfg-dyn-self-ref;
  3156. nvidia,emc-configuration = <
  3157. 0x00000004 /* EMC_RC */
  3158. 0x0000001a /* EMC_RFC */
  3159. 0x00000003 /* EMC_RAS */
  3160. 0x00000001 /* EMC_RP */
  3161. 0x00000002 /* EMC_R2W */
  3162. 0x0000000a /* EMC_W2R */
  3163. 0x00000005 /* EMC_R2P */
  3164. 0x0000000b /* EMC_W2P */
  3165. 0x00000001 /* EMC_RD_RCD */
  3166. 0x00000001 /* EMC_WR_RCD */
  3167. 0x00000003 /* EMC_RRD */
  3168. 0x00000001 /* EMC_REXT */
  3169. 0x00000000 /* EMC_WEXT */
  3170. 0x00000005 /* EMC_WDV */
  3171. 0x00000005 /* EMC_QUSE */
  3172. 0x00000004 /* EMC_QRST */
  3173. 0x0000000a /* EMC_QSAFE */
  3174. 0x0000000b /* EMC_RDV */
  3175. 0x00000303 /* EMC_REFRESH */
  3176. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  3177. 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
  3178. 0x00000002 /* EMC_PDEX2WR */
  3179. 0x00000002 /* EMC_PDEX2RD */
  3180. 0x00000001 /* EMC_PCHG2PDEN */
  3181. 0x00000000 /* EMC_ACT2PDEN */
  3182. 0x00000007 /* EMC_AR2PDEN */
  3183. 0x0000000f /* EMC_RW2PDEN */
  3184. 0x0000001c /* EMC_TXSR */
  3185. 0x0000001c /* EMC_TXSRDLL */
  3186. 0x00000004 /* EMC_TCKE */
  3187. 0x00000005 /* EMC_TFAW */
  3188. 0x00000000 /* EMC_TRPAB */
  3189. 0x00000004 /* EMC_TCLKSTABLE */
  3190. 0x00000005 /* EMC_TCLKSTOP */
  3191. 0x0000031c /* EMC_TREFBW */
  3192. 0x00000006 /* EMC_QUSE_EXTRA */
  3193. 0x00000004 /* EMC_FBIO_CFG6 */
  3194. 0x00000000 /* EMC_ODT_WRITE */
  3195. 0x00000000 /* EMC_ODT_READ */
  3196. 0x00004288 /* EMC_FBIO_CFG5 */
  3197. 0x007800a4 /* EMC_CFG_DIG_DLL */
  3198. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  3199. 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
  3200. 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
  3201. 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
  3202. 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
  3203. 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
  3204. 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
  3205. 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
  3206. 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
  3207. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  3208. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  3209. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  3210. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  3211. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  3212. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  3213. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  3214. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  3215. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  3216. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  3217. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  3218. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  3219. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  3220. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  3221. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  3222. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  3223. 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
  3224. 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
  3225. 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
  3226. 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
  3227. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  3228. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  3229. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  3230. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  3231. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  3232. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  3233. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  3234. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  3235. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  3236. 0x00000802 /* EMC_CTT_TERM_CTRL */
  3237. 0x00000000 /* EMC_ZCAL_INTERVAL */
  3238. 0x00000040 /* EMC_ZCAL_WAIT_CNT */
  3239. 0x000c000c /* EMC_MRS_WAIT_CNT */
  3240. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  3241. 0x00000000 /* EMC_CTT */
  3242. 0x00000000 /* EMC_CTT_DURATION */
  3243. 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
  3244. 0xe8000000 /* EMC_FBIO_SPARE */
  3245. 0xff00ff00 /* EMC_CFG_RSV */
  3246. >;
  3247. };
  3248. timing-204000000 {
  3249. clock-frequency = <204000000>;
  3250. nvidia,emc-auto-cal-interval = <0x001fffff>;
  3251. nvidia,emc-mode-1 = <0x80100003>;
  3252. nvidia,emc-mode-2 = <0x80200008>;
  3253. nvidia,emc-mode-reset = <0x80001221>;
  3254. nvidia,emc-zcal-cnt-long = <0x00000040>;
  3255. nvidia,emc-cfg-periodic-qrst;
  3256. nvidia,emc-cfg-dyn-self-ref;
  3257. nvidia,emc-configuration = <
  3258. 0x00000009 /* EMC_RC */
  3259. 0x00000035 /* EMC_RFC */
  3260. 0x00000007 /* EMC_RAS */
  3261. 0x00000002 /* EMC_RP */
  3262. 0x00000002 /* EMC_R2W */
  3263. 0x0000000a /* EMC_W2R */
  3264. 0x00000005 /* EMC_R2P */
  3265. 0x0000000b /* EMC_W2P */
  3266. 0x00000002 /* EMC_RD_RCD */
  3267. 0x00000002 /* EMC_WR_RCD */
  3268. 0x00000003 /* EMC_RRD */
  3269. 0x00000001 /* EMC_REXT */
  3270. 0x00000000 /* EMC_WEXT */
  3271. 0x00000005 /* EMC_WDV */
  3272. 0x00000005 /* EMC_QUSE */
  3273. 0x00000004 /* EMC_QRST */
  3274. 0x0000000a /* EMC_QSAFE */
  3275. 0x0000000b /* EMC_RDV */
  3276. 0x00000607 /* EMC_REFRESH */
  3277. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  3278. 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
  3279. 0x00000002 /* EMC_PDEX2WR */
  3280. 0x00000002 /* EMC_PDEX2RD */
  3281. 0x00000001 /* EMC_PCHG2PDEN */
  3282. 0x00000000 /* EMC_ACT2PDEN */
  3283. 0x00000007 /* EMC_AR2PDEN */
  3284. 0x0000000f /* EMC_RW2PDEN */
  3285. 0x00000038 /* EMC_TXSR */
  3286. 0x00000038 /* EMC_TXSRDLL */
  3287. 0x00000004 /* EMC_TCKE */
  3288. 0x00000009 /* EMC_TFAW */
  3289. 0x00000000 /* EMC_TRPAB */
  3290. 0x00000004 /* EMC_TCLKSTABLE */
  3291. 0x00000005 /* EMC_TCLKSTOP */
  3292. 0x00000638 /* EMC_TREFBW */
  3293. 0x00000006 /* EMC_QUSE_EXTRA */
  3294. 0x00000006 /* EMC_FBIO_CFG6 */
  3295. 0x00000000 /* EMC_ODT_WRITE */
  3296. 0x00000000 /* EMC_ODT_READ */
  3297. 0x00004288 /* EMC_FBIO_CFG5 */
  3298. 0x004400a4 /* EMC_CFG_DIG_DLL */
  3299. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  3300. 0x00080000 /* EMC_DLL_XFORM_DQS0 */
  3301. 0x00080000 /* EMC_DLL_XFORM_DQS1 */
  3302. 0x00080000 /* EMC_DLL_XFORM_DQS2 */
  3303. 0x00080000 /* EMC_DLL_XFORM_DQS3 */
  3304. 0x00080000 /* EMC_DLL_XFORM_DQS4 */
  3305. 0x00080000 /* EMC_DLL_XFORM_DQS5 */
  3306. 0x00080000 /* EMC_DLL_XFORM_DQS6 */
  3307. 0x00080000 /* EMC_DLL_XFORM_DQS7 */
  3308. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  3309. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  3310. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  3311. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  3312. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  3313. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  3314. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  3315. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  3316. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  3317. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  3318. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  3319. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  3320. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  3321. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  3322. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  3323. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  3324. 0x00080000 /* EMC_DLL_XFORM_DQ0 */
  3325. 0x00080000 /* EMC_DLL_XFORM_DQ1 */
  3326. 0x00080000 /* EMC_DLL_XFORM_DQ2 */
  3327. 0x00080000 /* EMC_DLL_XFORM_DQ3 */
  3328. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  3329. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  3330. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  3331. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  3332. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  3333. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  3334. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  3335. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  3336. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  3337. 0x00000802 /* EMC_CTT_TERM_CTRL */
  3338. 0x00020000 /* EMC_ZCAL_INTERVAL */
  3339. 0x00000100 /* EMC_ZCAL_WAIT_CNT */
  3340. 0x000c000c /* EMC_MRS_WAIT_CNT */
  3341. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  3342. 0x00000000 /* EMC_CTT */
  3343. 0x00000000 /* EMC_CTT_DURATION */
  3344. 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
  3345. 0xe8000000 /* EMC_FBIO_SPARE */
  3346. 0xff00ff00 /* EMC_CFG_RSV */
  3347. >;
  3348. };
  3349. timing-400000000 {
  3350. clock-frequency = <400000000>;
  3351. nvidia,emc-auto-cal-interval = <0x001fffff>;
  3352. nvidia,emc-mode-1 = <0x80100002>;
  3353. nvidia,emc-mode-2 = <0x80200000>;
  3354. nvidia,emc-mode-reset = <0x80000521>;
  3355. nvidia,emc-zcal-cnt-long = <0x00000040>;
  3356. nvidia,emc-configuration = <
  3357. 0x00000012 /* EMC_RC */
  3358. 0x00000066 /* EMC_RFC */
  3359. 0x0000000c /* EMC_RAS */
  3360. 0x00000004 /* EMC_RP */
  3361. 0x00000003 /* EMC_R2W */
  3362. 0x00000008 /* EMC_W2R */
  3363. 0x00000002 /* EMC_R2P */
  3364. 0x0000000a /* EMC_W2P */
  3365. 0x00000004 /* EMC_RD_RCD */
  3366. 0x00000004 /* EMC_WR_RCD */
  3367. 0x00000002 /* EMC_RRD */
  3368. 0x00000001 /* EMC_REXT */
  3369. 0x00000000 /* EMC_WEXT */
  3370. 0x00000004 /* EMC_WDV */
  3371. 0x00000006 /* EMC_QUSE */
  3372. 0x00000004 /* EMC_QRST */
  3373. 0x0000000a /* EMC_QSAFE */
  3374. 0x0000000c /* EMC_RDV */
  3375. 0x00000bf0 /* EMC_REFRESH */
  3376. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  3377. 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
  3378. 0x00000001 /* EMC_PDEX2WR */
  3379. 0x00000008 /* EMC_PDEX2RD */
  3380. 0x00000001 /* EMC_PCHG2PDEN */
  3381. 0x00000000 /* EMC_ACT2PDEN */
  3382. 0x00000008 /* EMC_AR2PDEN */
  3383. 0x0000000f /* EMC_RW2PDEN */
  3384. 0x0000006c /* EMC_TXSR */
  3385. 0x00000200 /* EMC_TXSRDLL */
  3386. 0x00000004 /* EMC_TCKE */
  3387. 0x00000010 /* EMC_TFAW */
  3388. 0x00000000 /* EMC_TRPAB */
  3389. 0x00000004 /* EMC_TCLKSTABLE */
  3390. 0x00000005 /* EMC_TCLKSTOP */
  3391. 0x00000c30 /* EMC_TREFBW */
  3392. 0x00000000 /* EMC_QUSE_EXTRA */
  3393. 0x00000004 /* EMC_FBIO_CFG6 */
  3394. 0x00000000 /* EMC_ODT_WRITE */
  3395. 0x00000000 /* EMC_ODT_READ */
  3396. 0x00007088 /* EMC_FBIO_CFG5 */
  3397. 0x001d0084 /* EMC_CFG_DIG_DLL */
  3398. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  3399. 0x0003c000 /* EMC_DLL_XFORM_DQS0 */
  3400. 0x0003c000 /* EMC_DLL_XFORM_DQS1 */
  3401. 0x0003c000 /* EMC_DLL_XFORM_DQS2 */
  3402. 0x0003c000 /* EMC_DLL_XFORM_DQS3 */
  3403. 0x0003c000 /* EMC_DLL_XFORM_DQS4 */
  3404. 0x0003c000 /* EMC_DLL_XFORM_DQS5 */
  3405. 0x0003c000 /* EMC_DLL_XFORM_DQS6 */
  3406. 0x0003c000 /* EMC_DLL_XFORM_DQS7 */
  3407. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  3408. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  3409. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  3410. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  3411. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  3412. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  3413. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  3414. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  3415. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  3416. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  3417. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  3418. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  3419. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  3420. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  3421. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  3422. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  3423. 0x00048000 /* EMC_DLL_XFORM_DQ0 */
  3424. 0x00048000 /* EMC_DLL_XFORM_DQ1 */
  3425. 0x00048000 /* EMC_DLL_XFORM_DQ2 */
  3426. 0x00048000 /* EMC_DLL_XFORM_DQ3 */
  3427. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  3428. 0x0800013d /* EMC_XM2DQSPADCTRL2 */
  3429. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  3430. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  3431. 0x01f1f508 /* EMC_XM2COMPPADCTRL */
  3432. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  3433. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  3434. 0x080001e8 /* EMC_XM2QUSEPADCTRL */
  3435. 0x08000021 /* EMC_XM2DQSPADCTRL3 */
  3436. 0x00000802 /* EMC_CTT_TERM_CTRL */
  3437. 0x00020000 /* EMC_ZCAL_INTERVAL */
  3438. 0x00000100 /* EMC_ZCAL_WAIT_CNT */
  3439. 0x0158000c /* EMC_MRS_WAIT_CNT */
  3440. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  3441. 0x00000000 /* EMC_CTT */
  3442. 0x00000000 /* EMC_CTT_DURATION */
  3443. 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
  3444. 0xe8000000 /* EMC_FBIO_SPARE */
  3445. 0xff00ff89 /* EMC_CFG_RSV */
  3446. >;
  3447. };
  3448. timing-800000000 {
  3449. clock-frequency = <800000000>;
  3450. nvidia,emc-auto-cal-interval = <0x001fffff>;
  3451. nvidia,emc-mode-1 = <0x80100002>;
  3452. nvidia,emc-mode-2 = <0x80200018>;
  3453. nvidia,emc-mode-reset = <0x80000d71>;
  3454. nvidia,emc-zcal-cnt-long = <0x00000040>;
  3455. nvidia,emc-cfg-periodic-qrst;
  3456. nvidia,emc-configuration = <
  3457. 0x00000025 /* EMC_RC */
  3458. 0x000000ce /* EMC_RFC */
  3459. 0x0000001a /* EMC_RAS */
  3460. 0x00000009 /* EMC_RP */
  3461. 0x00000005 /* EMC_R2W */
  3462. 0x0000000d /* EMC_W2R */
  3463. 0x00000004 /* EMC_R2P */
  3464. 0x00000013 /* EMC_W2P */
  3465. 0x00000009 /* EMC_RD_RCD */
  3466. 0x00000009 /* EMC_WR_RCD */
  3467. 0x00000004 /* EMC_RRD */
  3468. 0x00000001 /* EMC_REXT */
  3469. 0x00000000 /* EMC_WEXT */
  3470. 0x00000007 /* EMC_WDV */
  3471. 0x0000000a /* EMC_QUSE */
  3472. 0x00000009 /* EMC_QRST */
  3473. 0x0000000b /* EMC_QSAFE */
  3474. 0x00000011 /* EMC_RDV */
  3475. 0x00001820 /* EMC_REFRESH */
  3476. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  3477. 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
  3478. 0x00000003 /* EMC_PDEX2WR */
  3479. 0x00000012 /* EMC_PDEX2RD */
  3480. 0x00000001 /* EMC_PCHG2PDEN */
  3481. 0x00000000 /* EMC_ACT2PDEN */
  3482. 0x0000000f /* EMC_AR2PDEN */
  3483. 0x00000018 /* EMC_RW2PDEN */
  3484. 0x000000d8 /* EMC_TXSR */
  3485. 0x00000200 /* EMC_TXSRDLL */
  3486. 0x00000005 /* EMC_TCKE */
  3487. 0x00000020 /* EMC_TFAW */
  3488. 0x00000000 /* EMC_TRPAB */
  3489. 0x00000007 /* EMC_TCLKSTABLE */
  3490. 0x00000008 /* EMC_TCLKSTOP */
  3491. 0x00001860 /* EMC_TREFBW */
  3492. 0x0000000b /* EMC_QUSE_EXTRA */
  3493. 0x00000006 /* EMC_FBIO_CFG6 */
  3494. 0x00000000 /* EMC_ODT_WRITE */
  3495. 0x00000000 /* EMC_ODT_READ */
  3496. 0x00005088 /* EMC_FBIO_CFG5 */
  3497. 0xf0070191 /* EMC_CFG_DIG_DLL */
  3498. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  3499. 0x0000800a /* EMC_DLL_XFORM_DQS0 */
  3500. 0x0000000a /* EMC_DLL_XFORM_DQS1 */
  3501. 0x0000000a /* EMC_DLL_XFORM_DQS2 */
  3502. 0x0000000a /* EMC_DLL_XFORM_DQS3 */
  3503. 0x0000000a /* EMC_DLL_XFORM_DQS4 */
  3504. 0x0000000a /* EMC_DLL_XFORM_DQS5 */
  3505. 0x0000000a /* EMC_DLL_XFORM_DQS6 */
  3506. 0x0000000a /* EMC_DLL_XFORM_DQS7 */
  3507. 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
  3508. 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
  3509. 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
  3510. 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
  3511. 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
  3512. 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
  3513. 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
  3514. 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
  3515. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  3516. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  3517. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  3518. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  3519. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  3520. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  3521. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  3522. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  3523. 0x0000000a /* EMC_DLL_XFORM_DQ0 */
  3524. 0x0000000a /* EMC_DLL_XFORM_DQ1 */
  3525. 0x0000000a /* EMC_DLL_XFORM_DQ2 */
  3526. 0x0000000a /* EMC_DLL_XFORM_DQ3 */
  3527. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  3528. 0x0600013d /* EMC_XM2DQSPADCTRL2 */
  3529. 0x22220000 /* EMC_XM2DQPADCTRL2 */
  3530. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  3531. 0x01f1f501 /* EMC_XM2COMPPADCTRL */
  3532. 0x07077404 /* EMC_XM2VTTGENPADCTRL */
  3533. 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
  3534. 0x080001e8 /* EMC_XM2QUSEPADCTRL */
  3535. 0x08000021 /* EMC_XM2DQSPADCTRL3 */
  3536. 0x00000802 /* EMC_CTT_TERM_CTRL */
  3537. 0x00020000 /* EMC_ZCAL_INTERVAL */
  3538. 0x00000100 /* EMC_ZCAL_WAIT_CNT */
  3539. 0x00f0000c /* EMC_MRS_WAIT_CNT */
  3540. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  3541. 0x00000000 /* EMC_CTT */
  3542. 0x00000000 /* EMC_CTT_DURATION */
  3543. 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
  3544. 0xe8000000 /* EMC_FBIO_SPARE */
  3545. 0xff00ff49 /* EMC_CFG_RSV */
  3546. >;
  3547. };
  3548. };
  3549. emc-timings-2 {
  3550. nvidia,ram-code = <2>; /* Hynix A RAM */
  3551. timing-25500000 {
  3552. clock-frequency = <25500000>;
  3553. nvidia,emc-auto-cal-interval = <0x001fffff>;
  3554. nvidia,emc-mode-1 = <0x80100003>;
  3555. nvidia,emc-mode-2 = <0x80200008>;
  3556. nvidia,emc-mode-reset = <0x80001221>;
  3557. nvidia,emc-zcal-cnt-long = <0x00000040>;
  3558. nvidia,emc-cfg-periodic-qrst;
  3559. nvidia,emc-cfg-dyn-self-ref;
  3560. nvidia,emc-configuration = <
  3561. 0x00000001 /* EMC_RC */
  3562. 0x00000007 /* EMC_RFC */
  3563. 0x00000000 /* EMC_RAS */
  3564. 0x00000000 /* EMC_RP */
  3565. 0x00000002 /* EMC_R2W */
  3566. 0x0000000a /* EMC_W2R */
  3567. 0x00000005 /* EMC_R2P */
  3568. 0x0000000b /* EMC_W2P */
  3569. 0x00000000 /* EMC_RD_RCD */
  3570. 0x00000000 /* EMC_WR_RCD */
  3571. 0x00000003 /* EMC_RRD */
  3572. 0x00000001 /* EMC_REXT */
  3573. 0x00000000 /* EMC_WEXT */
  3574. 0x00000005 /* EMC_WDV */
  3575. 0x00000005 /* EMC_QUSE */
  3576. 0x00000004 /* EMC_QRST */
  3577. 0x0000000a /* EMC_QSAFE */
  3578. 0x0000000b /* EMC_RDV */
  3579. 0x000000c0 /* EMC_REFRESH */
  3580. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  3581. 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
  3582. 0x00000002 /* EMC_PDEX2WR */
  3583. 0x00000002 /* EMC_PDEX2RD */
  3584. 0x00000001 /* EMC_PCHG2PDEN */
  3585. 0x00000000 /* EMC_ACT2PDEN */
  3586. 0x00000007 /* EMC_AR2PDEN */
  3587. 0x0000000f /* EMC_RW2PDEN */
  3588. 0x00000008 /* EMC_TXSR */
  3589. 0x00000008 /* EMC_TXSRDLL */
  3590. 0x00000004 /* EMC_TCKE */
  3591. 0x00000002 /* EMC_TFAW */
  3592. 0x00000000 /* EMC_TRPAB */
  3593. 0x00000004 /* EMC_TCLKSTABLE */
  3594. 0x00000005 /* EMC_TCLKSTOP */
  3595. 0x000000c7 /* EMC_TREFBW */
  3596. 0x00000006 /* EMC_QUSE_EXTRA */
  3597. 0x00000004 /* EMC_FBIO_CFG6 */
  3598. 0x00000000 /* EMC_ODT_WRITE */
  3599. 0x00000000 /* EMC_ODT_READ */
  3600. 0x00004288 /* EMC_FBIO_CFG5 */
  3601. 0x007800a4 /* EMC_CFG_DIG_DLL */
  3602. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  3603. 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
  3604. 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
  3605. 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
  3606. 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
  3607. 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
  3608. 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
  3609. 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
  3610. 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
  3611. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  3612. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  3613. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  3614. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  3615. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  3616. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  3617. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  3618. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  3619. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  3620. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  3621. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  3622. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  3623. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  3624. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  3625. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  3626. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  3627. 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
  3628. 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
  3629. 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
  3630. 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
  3631. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  3632. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  3633. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  3634. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  3635. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  3636. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  3637. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  3638. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  3639. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  3640. 0x00000802 /* EMC_CTT_TERM_CTRL */
  3641. 0x00000000 /* EMC_ZCAL_INTERVAL */
  3642. 0x00000040 /* EMC_ZCAL_WAIT_CNT */
  3643. 0x000c000c /* EMC_MRS_WAIT_CNT */
  3644. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  3645. 0x00000000 /* EMC_CTT */
  3646. 0x00000000 /* EMC_CTT_DURATION */
  3647. 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
  3648. 0xe8000000 /* EMC_FBIO_SPARE */
  3649. 0xff00ff00 /* EMC_CFG_RSV */
  3650. >;
  3651. };
  3652. timing-51000000 {
  3653. clock-frequency = <51000000>;
  3654. nvidia,emc-auto-cal-interval = <0x001fffff>;
  3655. nvidia,emc-mode-1 = <0x80100003>;
  3656. nvidia,emc-mode-2 = <0x80200008>;
  3657. nvidia,emc-mode-reset = <0x80001221>;
  3658. nvidia,emc-zcal-cnt-long = <0x00000040>;
  3659. nvidia,emc-cfg-periodic-qrst;
  3660. nvidia,emc-cfg-dyn-self-ref;
  3661. nvidia,emc-configuration = <
  3662. 0x00000002 /* EMC_RC */
  3663. 0x0000000f /* EMC_RFC */
  3664. 0x00000001 /* EMC_RAS */
  3665. 0x00000000 /* EMC_RP */
  3666. 0x00000002 /* EMC_R2W */
  3667. 0x0000000a /* EMC_W2R */
  3668. 0x00000005 /* EMC_R2P */
  3669. 0x0000000b /* EMC_W2P */
  3670. 0x00000000 /* EMC_RD_RCD */
  3671. 0x00000000 /* EMC_WR_RCD */
  3672. 0x00000003 /* EMC_RRD */
  3673. 0x00000001 /* EMC_REXT */
  3674. 0x00000000 /* EMC_WEXT */
  3675. 0x00000005 /* EMC_WDV */
  3676. 0x00000005 /* EMC_QUSE */
  3677. 0x00000004 /* EMC_QRST */
  3678. 0x0000000a /* EMC_QSAFE */
  3679. 0x0000000b /* EMC_RDV */
  3680. 0x00000181 /* EMC_REFRESH */
  3681. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  3682. 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
  3683. 0x00000002 /* EMC_PDEX2WR */
  3684. 0x00000002 /* EMC_PDEX2RD */
  3685. 0x00000001 /* EMC_PCHG2PDEN */
  3686. 0x00000000 /* EMC_ACT2PDEN */
  3687. 0x00000007 /* EMC_AR2PDEN */
  3688. 0x0000000f /* EMC_RW2PDEN */
  3689. 0x00000010 /* EMC_TXSR */
  3690. 0x00000010 /* EMC_TXSRDLL */
  3691. 0x00000004 /* EMC_TCKE */
  3692. 0x00000003 /* EMC_TFAW */
  3693. 0x00000000 /* EMC_TRPAB */
  3694. 0x00000004 /* EMC_TCLKSTABLE */
  3695. 0x00000005 /* EMC_TCLKSTOP */
  3696. 0x0000018e /* EMC_TREFBW */
  3697. 0x00000006 /* EMC_QUSE_EXTRA */
  3698. 0x00000004 /* EMC_FBIO_CFG6 */
  3699. 0x00000000 /* EMC_ODT_WRITE */
  3700. 0x00000000 /* EMC_ODT_READ */
  3701. 0x00004288 /* EMC_FBIO_CFG5 */
  3702. 0x007800a4 /* EMC_CFG_DIG_DLL */
  3703. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  3704. 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
  3705. 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
  3706. 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
  3707. 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
  3708. 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
  3709. 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
  3710. 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
  3711. 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
  3712. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  3713. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  3714. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  3715. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  3716. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  3717. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  3718. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  3719. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  3720. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  3721. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  3722. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  3723. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  3724. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  3725. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  3726. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  3727. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  3728. 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
  3729. 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
  3730. 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
  3731. 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
  3732. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  3733. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  3734. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  3735. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  3736. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  3737. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  3738. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  3739. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  3740. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  3741. 0x00000802 /* EMC_CTT_TERM_CTRL */
  3742. 0x00000000 /* EMC_ZCAL_INTERVAL */
  3743. 0x00000040 /* EMC_ZCAL_WAIT_CNT */
  3744. 0x000c000c /* EMC_MRS_WAIT_CNT */
  3745. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  3746. 0x00000000 /* EMC_CTT */
  3747. 0x00000000 /* EMC_CTT_DURATION */
  3748. 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
  3749. 0xe8000000 /* EMC_FBIO_SPARE */
  3750. 0xff00ff00 /* EMC_CFG_RSV */
  3751. >;
  3752. };
  3753. timing-102000000 {
  3754. clock-frequency = <102000000>;
  3755. nvidia,emc-auto-cal-interval = <0x001fffff>;
  3756. nvidia,emc-mode-1 = <0x80100003>;
  3757. nvidia,emc-mode-2 = <0x80200008>;
  3758. nvidia,emc-mode-reset = <0x80001221>;
  3759. nvidia,emc-zcal-cnt-long = <0x00000040>;
  3760. nvidia,emc-cfg-periodic-qrst;
  3761. nvidia,emc-cfg-dyn-self-ref;
  3762. nvidia,emc-configuration = <
  3763. 0x00000004 /* EMC_RC */
  3764. 0x0000001e /* EMC_RFC */
  3765. 0x00000003 /* EMC_RAS */
  3766. 0x00000001 /* EMC_RP */
  3767. 0x00000002 /* EMC_R2W */
  3768. 0x0000000a /* EMC_W2R */
  3769. 0x00000005 /* EMC_R2P */
  3770. 0x0000000b /* EMC_W2P */
  3771. 0x00000001 /* EMC_RD_RCD */
  3772. 0x00000001 /* EMC_WR_RCD */
  3773. 0x00000003 /* EMC_RRD */
  3774. 0x00000001 /* EMC_REXT */
  3775. 0x00000000 /* EMC_WEXT */
  3776. 0x00000005 /* EMC_WDV */
  3777. 0x00000005 /* EMC_QUSE */
  3778. 0x00000004 /* EMC_QRST */
  3779. 0x0000000a /* EMC_QSAFE */
  3780. 0x0000000b /* EMC_RDV */
  3781. 0x00000303 /* EMC_REFRESH */
  3782. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  3783. 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
  3784. 0x00000002 /* EMC_PDEX2WR */
  3785. 0x00000002 /* EMC_PDEX2RD */
  3786. 0x00000001 /* EMC_PCHG2PDEN */
  3787. 0x00000000 /* EMC_ACT2PDEN */
  3788. 0x00000007 /* EMC_AR2PDEN */
  3789. 0x0000000f /* EMC_RW2PDEN */
  3790. 0x00000020 /* EMC_TXSR */
  3791. 0x00000020 /* EMC_TXSRDLL */
  3792. 0x00000004 /* EMC_TCKE */
  3793. 0x00000005 /* EMC_TFAW */
  3794. 0x00000000 /* EMC_TRPAB */
  3795. 0x00000004 /* EMC_TCLKSTABLE */
  3796. 0x00000005 /* EMC_TCLKSTOP */
  3797. 0x0000031c /* EMC_TREFBW */
  3798. 0x00000006 /* EMC_QUSE_EXTRA */
  3799. 0x00000004 /* EMC_FBIO_CFG6 */
  3800. 0x00000000 /* EMC_ODT_WRITE */
  3801. 0x00000000 /* EMC_ODT_READ */
  3802. 0x00004288 /* EMC_FBIO_CFG5 */
  3803. 0x007800a4 /* EMC_CFG_DIG_DLL */
  3804. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  3805. 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
  3806. 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
  3807. 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
  3808. 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
  3809. 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
  3810. 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
  3811. 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
  3812. 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
  3813. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  3814. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  3815. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  3816. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  3817. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  3818. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  3819. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  3820. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  3821. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  3822. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  3823. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  3824. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  3825. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  3826. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  3827. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  3828. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  3829. 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
  3830. 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
  3831. 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
  3832. 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
  3833. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  3834. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  3835. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  3836. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  3837. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  3838. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  3839. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  3840. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  3841. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  3842. 0x00000802 /* EMC_CTT_TERM_CTRL */
  3843. 0x00000000 /* EMC_ZCAL_INTERVAL */
  3844. 0x00000040 /* EMC_ZCAL_WAIT_CNT */
  3845. 0x000c000c /* EMC_MRS_WAIT_CNT */
  3846. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  3847. 0x00000000 /* EMC_CTT */
  3848. 0x00000000 /* EMC_CTT_DURATION */
  3849. 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
  3850. 0xe8000000 /* EMC_FBIO_SPARE */
  3851. 0xff00ff00 /* EMC_CFG_RSV */
  3852. >;
  3853. };
  3854. timing-204000000 {
  3855. clock-frequency = <204000000>;
  3856. nvidia,emc-auto-cal-interval = <0x001fffff>;
  3857. nvidia,emc-mode-1 = <0x80100003>;
  3858. nvidia,emc-mode-2 = <0x80200008>;
  3859. nvidia,emc-mode-reset = <0x80001221>;
  3860. nvidia,emc-zcal-cnt-long = <0x00000040>;
  3861. nvidia,emc-cfg-periodic-qrst;
  3862. nvidia,emc-cfg-dyn-self-ref;
  3863. nvidia,emc-configuration = <
  3864. 0x00000009 /* EMC_RC */
  3865. 0x0000003d /* EMC_RFC */
  3866. 0x00000007 /* EMC_RAS */
  3867. 0x00000002 /* EMC_RP */
  3868. 0x00000002 /* EMC_R2W */
  3869. 0x0000000a /* EMC_W2R */
  3870. 0x00000005 /* EMC_R2P */
  3871. 0x0000000b /* EMC_W2P */
  3872. 0x00000002 /* EMC_RD_RCD */
  3873. 0x00000002 /* EMC_WR_RCD */
  3874. 0x00000003 /* EMC_RRD */
  3875. 0x00000001 /* EMC_REXT */
  3876. 0x00000000 /* EMC_WEXT */
  3877. 0x00000005 /* EMC_WDV */
  3878. 0x00000005 /* EMC_QUSE */
  3879. 0x00000004 /* EMC_QRST */
  3880. 0x0000000a /* EMC_QSAFE */
  3881. 0x0000000b /* EMC_RDV */
  3882. 0x00000607 /* EMC_REFRESH */
  3883. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  3884. 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
  3885. 0x00000002 /* EMC_PDEX2WR */
  3886. 0x00000002 /* EMC_PDEX2RD */
  3887. 0x00000001 /* EMC_PCHG2PDEN */
  3888. 0x00000000 /* EMC_ACT2PDEN */
  3889. 0x00000007 /* EMC_AR2PDEN */
  3890. 0x0000000f /* EMC_RW2PDEN */
  3891. 0x00000040 /* EMC_TXSR */
  3892. 0x00000040 /* EMC_TXSRDLL */
  3893. 0x00000004 /* EMC_TCKE */
  3894. 0x00000009 /* EMC_TFAW */
  3895. 0x00000000 /* EMC_TRPAB */
  3896. 0x00000004 /* EMC_TCLKSTABLE */
  3897. 0x00000005 /* EMC_TCLKSTOP */
  3898. 0x00000638 /* EMC_TREFBW */
  3899. 0x00000006 /* EMC_QUSE_EXTRA */
  3900. 0x00000006 /* EMC_FBIO_CFG6 */
  3901. 0x00000000 /* EMC_ODT_WRITE */
  3902. 0x00000000 /* EMC_ODT_READ */
  3903. 0x00004288 /* EMC_FBIO_CFG5 */
  3904. 0x004400a4 /* EMC_CFG_DIG_DLL */
  3905. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  3906. 0x00080000 /* EMC_DLL_XFORM_DQS0 */
  3907. 0x00080000 /* EMC_DLL_XFORM_DQS1 */
  3908. 0x00080000 /* EMC_DLL_XFORM_DQS2 */
  3909. 0x00080000 /* EMC_DLL_XFORM_DQS3 */
  3910. 0x00080000 /* EMC_DLL_XFORM_DQS4 */
  3911. 0x00080000 /* EMC_DLL_XFORM_DQS5 */
  3912. 0x00080000 /* EMC_DLL_XFORM_DQS6 */
  3913. 0x00080000 /* EMC_DLL_XFORM_DQS7 */
  3914. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  3915. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  3916. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  3917. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  3918. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  3919. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  3920. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  3921. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  3922. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  3923. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  3924. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  3925. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  3926. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  3927. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  3928. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  3929. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  3930. 0x00080000 /* EMC_DLL_XFORM_DQ0 */
  3931. 0x00080000 /* EMC_DLL_XFORM_DQ1 */
  3932. 0x00080000 /* EMC_DLL_XFORM_DQ2 */
  3933. 0x00080000 /* EMC_DLL_XFORM_DQ3 */
  3934. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  3935. 0x0800211c /* EMC_XM2DQSPADCTRL2 */
  3936. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  3937. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  3938. 0x01f1f108 /* EMC_XM2COMPPADCTRL */
  3939. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  3940. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  3941. 0x08000168 /* EMC_XM2QUSEPADCTRL */
  3942. 0x08000000 /* EMC_XM2DQSPADCTRL3 */
  3943. 0x00000802 /* EMC_CTT_TERM_CTRL */
  3944. 0x00020000 /* EMC_ZCAL_INTERVAL */
  3945. 0x00000100 /* EMC_ZCAL_WAIT_CNT */
  3946. 0x000c000c /* EMC_MRS_WAIT_CNT */
  3947. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  3948. 0x00000000 /* EMC_CTT */
  3949. 0x00000000 /* EMC_CTT_DURATION */
  3950. 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
  3951. 0xe8000000 /* EMC_FBIO_SPARE */
  3952. 0xff00ff00 /* EMC_CFG_RSV */
  3953. >;
  3954. };
  3955. timing-400000000 {
  3956. clock-frequency = <400000000>;
  3957. nvidia,emc-auto-cal-interval = <0x001fffff>;
  3958. nvidia,emc-mode-1 = <0x80100002>;
  3959. nvidia,emc-mode-2 = <0x80200000>;
  3960. nvidia,emc-mode-reset = <0x80000521>;
  3961. nvidia,emc-zcal-cnt-long = <0x00000040>;
  3962. nvidia,emc-configuration = <
  3963. 0x00000012 /* EMC_RC */
  3964. 0x00000076 /* EMC_RFC */
  3965. 0x0000000c /* EMC_RAS */
  3966. 0x00000004 /* EMC_RP */
  3967. 0x00000003 /* EMC_R2W */
  3968. 0x00000008 /* EMC_W2R */
  3969. 0x00000002 /* EMC_R2P */
  3970. 0x0000000a /* EMC_W2P */
  3971. 0x00000004 /* EMC_RD_RCD */
  3972. 0x00000004 /* EMC_WR_RCD */
  3973. 0x00000002 /* EMC_RRD */
  3974. 0x00000001 /* EMC_REXT */
  3975. 0x00000000 /* EMC_WEXT */
  3976. 0x00000004 /* EMC_WDV */
  3977. 0x00000006 /* EMC_QUSE */
  3978. 0x00000004 /* EMC_QRST */
  3979. 0x0000000a /* EMC_QSAFE */
  3980. 0x0000000c /* EMC_RDV */
  3981. 0x00000bf0 /* EMC_REFRESH */
  3982. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  3983. 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
  3984. 0x00000001 /* EMC_PDEX2WR */
  3985. 0x00000008 /* EMC_PDEX2RD */
  3986. 0x00000001 /* EMC_PCHG2PDEN */
  3987. 0x00000000 /* EMC_ACT2PDEN */
  3988. 0x00000008 /* EMC_AR2PDEN */
  3989. 0x0000000f /* EMC_RW2PDEN */
  3990. 0x0000007c /* EMC_TXSR */
  3991. 0x00000200 /* EMC_TXSRDLL */
  3992. 0x00000004 /* EMC_TCKE */
  3993. 0x00000010 /* EMC_TFAW */
  3994. 0x00000000 /* EMC_TRPAB */
  3995. 0x00000004 /* EMC_TCLKSTABLE */
  3996. 0x00000005 /* EMC_TCLKSTOP */
  3997. 0x00000c30 /* EMC_TREFBW */
  3998. 0x00000000 /* EMC_QUSE_EXTRA */
  3999. 0x00000004 /* EMC_FBIO_CFG6 */
  4000. 0x00000000 /* EMC_ODT_WRITE */
  4001. 0x00000000 /* EMC_ODT_READ */
  4002. 0x00007088 /* EMC_FBIO_CFG5 */
  4003. 0x001d0084 /* EMC_CFG_DIG_DLL */
  4004. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  4005. 0x00044000 /* EMC_DLL_XFORM_DQS0 */
  4006. 0x00044000 /* EMC_DLL_XFORM_DQS1 */
  4007. 0x00044000 /* EMC_DLL_XFORM_DQS2 */
  4008. 0x00044000 /* EMC_DLL_XFORM_DQS3 */
  4009. 0x00044000 /* EMC_DLL_XFORM_DQS4 */
  4010. 0x00044000 /* EMC_DLL_XFORM_DQS5 */
  4011. 0x00044000 /* EMC_DLL_XFORM_DQS6 */
  4012. 0x00044000 /* EMC_DLL_XFORM_DQS7 */
  4013. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  4014. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  4015. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  4016. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  4017. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  4018. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  4019. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  4020. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  4021. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  4022. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  4023. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  4024. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  4025. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  4026. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  4027. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  4028. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  4029. 0x00058000 /* EMC_DLL_XFORM_DQ0 */
  4030. 0x00058000 /* EMC_DLL_XFORM_DQ1 */
  4031. 0x00058000 /* EMC_DLL_XFORM_DQ2 */
  4032. 0x00058000 /* EMC_DLL_XFORM_DQ3 */
  4033. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  4034. 0x0800013d /* EMC_XM2DQSPADCTRL2 */
  4035. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  4036. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  4037. 0x01f1f508 /* EMC_XM2COMPPADCTRL */
  4038. 0x05057404 /* EMC_XM2VTTGENPADCTRL */
  4039. 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
  4040. 0x080001e8 /* EMC_XM2QUSEPADCTRL */
  4041. 0x08000021 /* EMC_XM2DQSPADCTRL3 */
  4042. 0x00000802 /* EMC_CTT_TERM_CTRL */
  4043. 0x00020000 /* EMC_ZCAL_INTERVAL */
  4044. 0x00000100 /* EMC_ZCAL_WAIT_CNT */
  4045. 0x0148000c /* EMC_MRS_WAIT_CNT */
  4046. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  4047. 0x00000000 /* EMC_CTT */
  4048. 0x00000000 /* EMC_CTT_DURATION */
  4049. 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
  4050. 0xe8000000 /* EMC_FBIO_SPARE */
  4051. 0xff00ff89 /* EMC_CFG_RSV */
  4052. >;
  4053. };
  4054. timing-800000000 {
  4055. clock-frequency = <800000000>;
  4056. nvidia,emc-auto-cal-interval = <0x001fffff>;
  4057. nvidia,emc-mode-1 = <0x80100002>;
  4058. nvidia,emc-mode-2 = <0x80200018>;
  4059. nvidia,emc-mode-reset = <0x80000d71>;
  4060. nvidia,emc-zcal-cnt-long = <0x00000040>;
  4061. nvidia,emc-cfg-periodic-qrst;
  4062. nvidia,emc-configuration = <
  4063. 0x00000025 /* EMC_RC */
  4064. 0x000000ee /* EMC_RFC */
  4065. 0x0000001a /* EMC_RAS */
  4066. 0x00000009 /* EMC_RP */
  4067. 0x00000005 /* EMC_R2W */
  4068. 0x0000000d /* EMC_W2R */
  4069. 0x00000004 /* EMC_R2P */
  4070. 0x00000013 /* EMC_W2P */
  4071. 0x00000009 /* EMC_RD_RCD */
  4072. 0x00000009 /* EMC_WR_RCD */
  4073. 0x00000003 /* EMC_RRD */
  4074. 0x00000001 /* EMC_REXT */
  4075. 0x00000000 /* EMC_WEXT */
  4076. 0x00000007 /* EMC_WDV */
  4077. 0x0000000a /* EMC_QUSE */
  4078. 0x00000009 /* EMC_QRST */
  4079. 0x0000000b /* EMC_QSAFE */
  4080. 0x00000011 /* EMC_RDV */
  4081. 0x00001820 /* EMC_REFRESH */
  4082. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  4083. 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
  4084. 0x00000003 /* EMC_PDEX2WR */
  4085. 0x00000012 /* EMC_PDEX2RD */
  4086. 0x00000001 /* EMC_PCHG2PDEN */
  4087. 0x00000000 /* EMC_ACT2PDEN */
  4088. 0x0000000f /* EMC_AR2PDEN */
  4089. 0x00000018 /* EMC_RW2PDEN */
  4090. 0x000000f8 /* EMC_TXSR */
  4091. 0x00000200 /* EMC_TXSRDLL */
  4092. 0x00000005 /* EMC_TCKE */
  4093. 0x00000020 /* EMC_TFAW */
  4094. 0x00000000 /* EMC_TRPAB */
  4095. 0x00000007 /* EMC_TCLKSTABLE */
  4096. 0x00000008 /* EMC_TCLKSTOP */
  4097. 0x00001860 /* EMC_TREFBW */
  4098. 0x0000000b /* EMC_QUSE_EXTRA */
  4099. 0x00000006 /* EMC_FBIO_CFG6 */
  4100. 0x00000000 /* EMC_ODT_WRITE */
  4101. 0x00000000 /* EMC_ODT_READ */
  4102. 0x00005088 /* EMC_FBIO_CFG5 */
  4103. 0xf0070191 /* EMC_CFG_DIG_DLL */
  4104. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  4105. 0x0000000c /* EMC_DLL_XFORM_DQS0 */
  4106. 0x007fc00a /* EMC_DLL_XFORM_DQS1 */
  4107. 0x00000008 /* EMC_DLL_XFORM_DQS2 */
  4108. 0x0000000a /* EMC_DLL_XFORM_DQS3 */
  4109. 0x0000000a /* EMC_DLL_XFORM_DQS4 */
  4110. 0x0000000a /* EMC_DLL_XFORM_DQS5 */
  4111. 0x0000000a /* EMC_DLL_XFORM_DQS6 */
  4112. 0x0000000a /* EMC_DLL_XFORM_DQS7 */
  4113. 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
  4114. 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
  4115. 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
  4116. 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
  4117. 0x00018000 /* EMC_DLL_XFORM_QUSE4 */
  4118. 0x00018000 /* EMC_DLL_XFORM_QUSE5 */
  4119. 0x00018000 /* EMC_DLL_XFORM_QUSE6 */
  4120. 0x00018000 /* EMC_DLL_XFORM_QUSE7 */
  4121. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  4122. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  4123. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  4124. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  4125. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  4126. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  4127. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  4128. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  4129. 0x0000000a /* EMC_DLL_XFORM_DQ0 */
  4130. 0x0000000c /* EMC_DLL_XFORM_DQ1 */
  4131. 0x0000000a /* EMC_DLL_XFORM_DQ2 */
  4132. 0x0000000a /* EMC_DLL_XFORM_DQ3 */
  4133. 0x000002a0 /* EMC_XM2CMDPADCTRL */
  4134. 0x0600013d /* EMC_XM2DQSPADCTRL2 */
  4135. 0x22220000 /* EMC_XM2DQPADCTRL2 */
  4136. 0x77fff884 /* EMC_XM2CLKPADCTRL */
  4137. 0x01f1f501 /* EMC_XM2COMPPADCTRL */
  4138. 0x07077404 /* EMC_XM2VTTGENPADCTRL */
  4139. 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
  4140. 0x080001e8 /* EMC_XM2QUSEPADCTRL */
  4141. 0x0a000021 /* EMC_XM2DQSPADCTRL3 */
  4142. 0x00000802 /* EMC_CTT_TERM_CTRL */
  4143. 0x00020000 /* EMC_ZCAL_INTERVAL */
  4144. 0x00000100 /* EMC_ZCAL_WAIT_CNT */
  4145. 0x00d0000c /* EMC_MRS_WAIT_CNT */
  4146. 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
  4147. 0x00000000 /* EMC_CTT */
  4148. 0x00000000 /* EMC_CTT_DURATION */
  4149. 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
  4150. 0xe8000000 /* EMC_FBIO_SPARE */
  4151. 0xff00ff49 /* EMC_CFG_RSV */
  4152. >;
  4153. };
  4154. };
  4155. };
  4156. hda@70030000 {
  4157. status = "okay";
  4158. };
  4159. wifi_pwrseq: wifi_pwrseq {
  4160. compatible = "mmc-pwrseq-simple";
  4161. clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  4162. clock-names = "ext_clock";
  4163. reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
  4164. post-power-on-delay-ms = <300>;
  4165. power-off-delay-us = <300>;
  4166. };
  4167. sdmmc3: mmc@78000400 {
  4168. status = "okay";
  4169. #address-cells = <1>;
  4170. #size-cells = <0>;
  4171. assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
  4172. assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
  4173. assigned-clock-rates = <50000000>;
  4174. max-frequency = <50000000>;
  4175. keep-power-in-suspend;
  4176. bus-width = <4>;
  4177. non-removable;
  4178. mmc-pwrseq = <&wifi_pwrseq>;
  4179. vmmc-supply = <&sdmmc_3v3_reg>;
  4180. vqmmc-supply = <&vdd_1v8>;
  4181. /* Azurewave AW-NH660 BCM4330 */
  4182. brcmf: wifi@1 {
  4183. reg = <1>;
  4184. compatible = "brcm,bcm4329-fmac";
  4185. interrupt-parent = <&gpio>;
  4186. interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
  4187. interrupt-names = "host-wake";
  4188. };
  4189. };
  4190. sdmmc4: mmc@78000600 {
  4191. status = "okay";
  4192. keep-power-in-suspend;
  4193. bus-width = <8>;
  4194. non-removable;
  4195. vmmc-supply = <&sys_3v3_reg>;
  4196. vqmmc-supply = <&vdd_1v8>;
  4197. nvidia,default-tap = <0x0F>;
  4198. max-frequency = <25500000>;
  4199. };
  4200. usb@7d000000 {
  4201. compatible = "nvidia,tegra30-udc";
  4202. status = "okay";
  4203. };
  4204. usb-phy@7d000000 {
  4205. status = "okay";
  4206. dr_mode = "peripheral";
  4207. };
  4208. usb@7d004000 {
  4209. status = "okay";
  4210. #address-cells = <1>;
  4211. #size-cells = <0>;
  4212. ethernet@2 { /* SMSC 10/100T Ethernet Controller */
  4213. compatible = "usb424,9e00";
  4214. reg = <2>;
  4215. local-mac-address = [00 11 22 33 44 55];
  4216. };
  4217. };
  4218. usb-phy@7d004000 {
  4219. vbus-supply = <&vdd_smsc>;
  4220. status = "okay";
  4221. };
  4222. usb@7d008000 {
  4223. status = "okay";
  4224. };
  4225. usb-phy@7d008000 {
  4226. vbus-supply = <&usb3_vbus_reg>;
  4227. status = "okay";
  4228. };
  4229. /* PMIC has a built-in 32KHz oscillator which is used by PMC */
  4230. clk32k_in: clock {
  4231. compatible = "fixed-clock";
  4232. #clock-cells = <0>;
  4233. clock-frequency = <32768>;
  4234. clock-output-names = "pmic-oscillator";
  4235. };
  4236. cpus {
  4237. cpu0: cpu@0 {
  4238. operating-points-v2 = <&cpu0_opp_table>;
  4239. cpu-supply = <&vdd_cpu>;
  4240. #cooling-cells = <2>;
  4241. };
  4242. cpu1: cpu@1 {
  4243. operating-points-v2 = <&cpu0_opp_table>;
  4244. cpu-supply = <&vdd_cpu>;
  4245. #cooling-cells = <2>;
  4246. };
  4247. cpu2: cpu@2 {
  4248. operating-points-v2 = <&cpu0_opp_table>;
  4249. cpu-supply = <&vdd_cpu>;
  4250. #cooling-cells = <2>;
  4251. };
  4252. cpu3: cpu@3 {
  4253. operating-points-v2 = <&cpu0_opp_table>;
  4254. cpu-supply = <&vdd_cpu>;
  4255. #cooling-cells = <2>;
  4256. };
  4257. };
  4258. firmware {
  4259. trusted-foundations {
  4260. compatible = "tlm,trusted-foundations";
  4261. tlm,version-major = <0x0>;
  4262. tlm,version-minor = <0x0>;
  4263. };
  4264. };
  4265. fan: gpio_fan {
  4266. compatible = "gpio-fan";
  4267. gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
  4268. gpio-fan,speed-map = <0 0
  4269. 4500 1>;
  4270. #cooling-cells = <2>;
  4271. };
  4272. thermal-zones {
  4273. cpu_thermal: cpu-thermal {
  4274. polling-delay = <5000>;
  4275. polling-delay-passive = <5000>;
  4276. thermal-sensors = <&cpu_temp 1>;
  4277. trips {
  4278. cpu_alert0: cpu-alert0 {
  4279. temperature = <50000>;
  4280. hysteresis = <10000>;
  4281. type = "active";
  4282. };
  4283. cpu_alert1: cpu-alert1 {
  4284. temperature = <70000>;
  4285. hysteresis = <5000>;
  4286. type = "passive";
  4287. };
  4288. cpu_crit: cpu-crit {
  4289. temperature = <90000>;
  4290. hysteresis = <2000>;
  4291. type = "critical";
  4292. };
  4293. };
  4294. cooling-maps {
  4295. map0 {
  4296. trip = <&cpu_alert0>;
  4297. cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  4298. };
  4299. map1 {
  4300. trip = <&cpu_alert1>;
  4301. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  4302. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  4303. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  4304. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  4305. <&actmon THERMAL_NO_LIMIT
  4306. THERMAL_NO_LIMIT>;
  4307. };
  4308. };
  4309. };
  4310. };
  4311. vdd_12v_in: vdd_12v_in {
  4312. compatible = "regulator-fixed";
  4313. regulator-name = "vdd_12v_in";
  4314. regulator-min-microvolt = <12000000>;
  4315. regulator-max-microvolt = <12000000>;
  4316. regulator-always-on;
  4317. };
  4318. sdmmc_3v3_reg: sdmmc_3v3_reg {
  4319. compatible = "regulator-fixed";
  4320. regulator-name = "sdmmc_3v3";
  4321. regulator-min-microvolt = <3300000>;
  4322. regulator-max-microvolt = <3300000>;
  4323. enable-active-high;
  4324. regulator-always-on;
  4325. gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
  4326. vin-supply = <&sys_3v3_reg>;
  4327. };
  4328. vdd_fuse_3v3_reg: vdd_fuse_3v3_reg {
  4329. compatible = "regulator-fixed";
  4330. regulator-name = "vdd_fuse_3v3";
  4331. regulator-min-microvolt = <3300000>;
  4332. regulator-max-microvolt = <3300000>;
  4333. enable-active-high;
  4334. gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
  4335. vin-supply = <&sys_3v3_reg>;
  4336. regulator-always-on;
  4337. };
  4338. vdd_vid_reg: vdd_vid_reg {
  4339. compatible = "regulator-fixed";
  4340. regulator-name = "vddio_vid";
  4341. regulator-min-microvolt = <5000000>;
  4342. regulator-max-microvolt = <5000000>;
  4343. enable-active-high;
  4344. gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
  4345. vin-supply = <&vdd_5v0_reg>;
  4346. regulator-boot-on;
  4347. };
  4348. ddr_reg: ddr_reg {
  4349. compatible = "regulator-fixed";
  4350. regulator-name = "vdd_ddr";
  4351. regulator-min-microvolt = <1500000>;
  4352. regulator-max-microvolt = <1500000>;
  4353. regulator-always-on;
  4354. enable-active-high;
  4355. gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
  4356. regulator-boot-on;
  4357. vin-supply = <&vdd_12v_in>;
  4358. };
  4359. sys_3v3_reg: sys_3v3_reg {
  4360. compatible = "regulator-fixed";
  4361. regulator-name = "sys_3v3";
  4362. regulator-min-microvolt = <3300000>;
  4363. regulator-max-microvolt = <3300000>;
  4364. enable-active-high;
  4365. gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
  4366. regulator-always-on;
  4367. regulator-boot-on;
  4368. vin-supply = <&vdd_12v_in>;
  4369. };
  4370. vdd_5v0_reg: vdd_5v0_reg {
  4371. compatible = "regulator-fixed";
  4372. regulator-name = "vdd_5v0";
  4373. regulator-min-microvolt = <5000000>;
  4374. regulator-max-microvolt = <5000000>;
  4375. enable-active-high;
  4376. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  4377. regulator-always-on;
  4378. regulator-boot-on;
  4379. vin-supply = <&vdd_12v_in>;
  4380. };
  4381. vdd_smsc: vdd_smsc {
  4382. compatible = "regulator-fixed";
  4383. regulator-name = "vdd_smsc";
  4384. enable-active-high;
  4385. gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>;
  4386. };
  4387. usb3_vbus_reg: usb3_vbus_reg {
  4388. compatible = "regulator-fixed";
  4389. regulator-name = "usb3_vbus";
  4390. regulator-min-microvolt = <5000000>;
  4391. regulator-max-microvolt = <5000000>;
  4392. enable-active-high;
  4393. gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
  4394. vin-supply = <&vdd_5v0_reg>;
  4395. };
  4396. gpio-keys {
  4397. compatible = "gpio-keys";
  4398. key-power {
  4399. gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
  4400. debounce-interval = <10>;
  4401. linux,code = <KEY_POWER>;
  4402. wakeup-event-action = <EV_ACT_ASSERTED>;
  4403. wakeup-source;
  4404. };
  4405. };
  4406. leds {
  4407. compatible = "gpio-leds";
  4408. led-power {
  4409. label = "power-led";
  4410. gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  4411. default-state = "on";
  4412. linux,default-trigger = "heartbeat";
  4413. retain-state-suspended;
  4414. };
  4415. };
  4416. };
  4417. &emc_icc_dvfs_opp_table {
  4418. /delete-node/ opp-900000000-1350;
  4419. };
  4420. &emc_bw_dfs_opp_table {
  4421. /delete-node/ opp-900000000;
  4422. };