tegra30-cardhu.dtsi 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711
  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/thermal/thermal.h>
  4. #include "tegra30.dtsi"
  5. #include "tegra30-cpu-opp.dtsi"
  6. #include "tegra30-cpu-opp-microvolt.dtsi"
  7. /**
  8. * This file contains common DT entry for all fab version of Cardhu.
  9. * There is multiple fab version of Cardhu starting from A01 to A07.
  10. * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
  11. * A02 will have different sets of GPIOs for fixed regulator compare to
  12. * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
  13. * compatible with fab version A04. Based on Cardhu fab version, the
  14. * related dts file need to be chosen like for Cardhu fab version A02,
  15. * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
  16. * tegra30-cardhu-a04.dts.
  17. * The identification of board is done in two ways, by looking the sticker
  18. * on PCB and by reading board id eeprom.
  19. * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
  20. * number is the fab version like here it is 002 and hence fab version A02.
  21. * The (downstream internal) U-Boot of Cardhu display the board-id as
  22. * follows:
  23. * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
  24. * In this Fab version is 02 i.e. A02.
  25. * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
  26. * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
  27. * wide.
  28. */
  29. / {
  30. model = "NVIDIA Tegra30 Cardhu evaluation board";
  31. compatible = "nvidia,cardhu", "nvidia,tegra30";
  32. aliases {
  33. rtc0 = "/i2c@7000d000/tps65911@2d";
  34. rtc1 = "/rtc@7000e000";
  35. serial0 = &uarta;
  36. serial1 = &uartc;
  37. };
  38. chosen {
  39. stdout-path = "serial0:115200n8";
  40. };
  41. memory@80000000 {
  42. reg = <0x80000000 0x40000000>;
  43. };
  44. pcie@3000 {
  45. status = "okay";
  46. /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
  47. avdd-pexb-supply = <&ldo1_reg>;
  48. vdd-pexb-supply = <&ldo1_reg>;
  49. avdd-pex-pll-supply = <&ldo1_reg>;
  50. hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
  51. vddio-pex-ctl-supply = <&sys_3v3_reg>;
  52. avdd-plle-supply = <&ldo2_reg>;
  53. pci@1,0 {
  54. nvidia,num-lanes = <4>;
  55. };
  56. pci@2,0 {
  57. nvidia,num-lanes = <1>;
  58. };
  59. pci@3,0 {
  60. status = "okay";
  61. nvidia,num-lanes = <1>;
  62. };
  63. };
  64. host1x@50000000 {
  65. dc@54200000 {
  66. rgb {
  67. status = "okay";
  68. nvidia,panel = <&panel>;
  69. };
  70. };
  71. };
  72. pinmux@70000868 {
  73. pinctrl-names = "default";
  74. pinctrl-0 = <&state_default>;
  75. state_default: pinmux {
  76. sdmmc1_clk_pz0 {
  77. nvidia,pins = "sdmmc1_clk_pz0";
  78. nvidia,function = "sdmmc1";
  79. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  80. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  81. };
  82. sdmmc1_cmd_pz1 {
  83. nvidia,pins = "sdmmc1_cmd_pz1",
  84. "sdmmc1_dat0_py7",
  85. "sdmmc1_dat1_py6",
  86. "sdmmc1_dat2_py5",
  87. "sdmmc1_dat3_py4";
  88. nvidia,function = "sdmmc1";
  89. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  90. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  91. };
  92. sdmmc3_clk_pa6 {
  93. nvidia,pins = "sdmmc3_clk_pa6";
  94. nvidia,function = "sdmmc3";
  95. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  96. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  97. };
  98. sdmmc3_cmd_pa7 {
  99. nvidia,pins = "sdmmc3_cmd_pa7",
  100. "sdmmc3_dat0_pb7",
  101. "sdmmc3_dat1_pb6",
  102. "sdmmc3_dat2_pb5",
  103. "sdmmc3_dat3_pb4";
  104. nvidia,function = "sdmmc3";
  105. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  106. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  107. };
  108. sdmmc4_clk_pcc4 {
  109. nvidia,pins = "sdmmc4_clk_pcc4",
  110. "sdmmc4_rst_n_pcc3";
  111. nvidia,function = "sdmmc4";
  112. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  113. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  114. };
  115. sdmmc4_dat0_paa0 {
  116. nvidia,pins = "sdmmc4_dat0_paa0",
  117. "sdmmc4_dat1_paa1",
  118. "sdmmc4_dat2_paa2",
  119. "sdmmc4_dat3_paa3",
  120. "sdmmc4_dat4_paa4",
  121. "sdmmc4_dat5_paa5",
  122. "sdmmc4_dat6_paa6",
  123. "sdmmc4_dat7_paa7";
  124. nvidia,function = "sdmmc4";
  125. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  126. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  127. };
  128. dap2_fs_pa2 {
  129. nvidia,pins = "dap2_fs_pa2",
  130. "dap2_sclk_pa3",
  131. "dap2_din_pa4",
  132. "dap2_dout_pa5";
  133. nvidia,function = "i2s1";
  134. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  135. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  136. };
  137. sdio3 {
  138. nvidia,pins = "drive_sdio3";
  139. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  140. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  141. nvidia,pull-down-strength = <46>;
  142. nvidia,pull-up-strength = <42>;
  143. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
  144. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
  145. };
  146. uart3_txd_pw6 {
  147. nvidia,pins = "uart3_txd_pw6",
  148. "uart3_cts_n_pa1",
  149. "uart3_rts_n_pc0",
  150. "uart3_rxd_pw7";
  151. nvidia,function = "uartc";
  152. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  153. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  154. };
  155. };
  156. };
  157. serial@70006000 {
  158. status = "okay";
  159. };
  160. serial@70006200 {
  161. compatible = "nvidia,tegra30-hsuart";
  162. /delete-property/ reg-shift;
  163. status = "okay";
  164. };
  165. pwm@7000a000 {
  166. status = "okay";
  167. };
  168. panelddc: i2c@7000c000 {
  169. status = "okay";
  170. clock-frequency = <100000>;
  171. };
  172. i2c@7000c400 {
  173. status = "okay";
  174. clock-frequency = <100000>;
  175. };
  176. i2c@7000c500 {
  177. status = "okay";
  178. clock-frequency = <100000>;
  179. /* ALS and Proximity sensor */
  180. isl29028@44 {
  181. compatible = "isil,isl29028";
  182. reg = <0x44>;
  183. interrupt-parent = <&gpio>;
  184. interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
  185. };
  186. i2cmux@70 {
  187. compatible = "nxp,pca9546";
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. reg = <0x70>;
  191. reset-gpios = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>;
  192. };
  193. };
  194. i2c@7000c700 {
  195. status = "okay";
  196. clock-frequency = <100000>;
  197. };
  198. i2c@7000d000 {
  199. status = "okay";
  200. clock-frequency = <100000>;
  201. wm8903: wm8903@1a {
  202. compatible = "wlf,wm8903";
  203. reg = <0x1a>;
  204. interrupt-parent = <&gpio>;
  205. interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
  206. gpio-controller;
  207. #gpio-cells = <2>;
  208. micdet-cfg = <0>;
  209. micdet-delay = <100>;
  210. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  211. };
  212. pmic: tps65911@2d {
  213. compatible = "ti,tps65911";
  214. reg = <0x2d>;
  215. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  216. #interrupt-cells = <2>;
  217. interrupt-controller;
  218. wakeup-source;
  219. ti,system-power-controller;
  220. #gpio-cells = <2>;
  221. gpio-controller;
  222. vcc1-supply = <&vdd_ac_bat_reg>;
  223. vcc2-supply = <&vdd_ac_bat_reg>;
  224. vcc3-supply = <&vio_reg>;
  225. vcc4-supply = <&vdd_5v0_reg>;
  226. vcc5-supply = <&vdd_ac_bat_reg>;
  227. vcc6-supply = <&vdd2_reg>;
  228. vcc7-supply = <&vdd_ac_bat_reg>;
  229. vccio-supply = <&vdd_ac_bat_reg>;
  230. regulators {
  231. vdd1_reg: vdd1 {
  232. regulator-name = "vddio_ddr_1v2";
  233. regulator-min-microvolt = <1200000>;
  234. regulator-max-microvolt = <1200000>;
  235. regulator-always-on;
  236. };
  237. vdd2_reg: vdd2 {
  238. regulator-name = "vdd_1v5_gen";
  239. regulator-min-microvolt = <1500000>;
  240. regulator-max-microvolt = <1500000>;
  241. regulator-always-on;
  242. };
  243. vddctrl_reg: vddctrl {
  244. regulator-name = "vdd_cpu,vdd_sys";
  245. regulator-min-microvolt = <800000>;
  246. regulator-max-microvolt = <1250000>;
  247. regulator-coupled-with = <&vdd_core>;
  248. regulator-coupled-max-spread = <300000>;
  249. regulator-max-step-microvolt = <100000>;
  250. regulator-always-on;
  251. nvidia,tegra-cpu-regulator;
  252. };
  253. vio_reg: vio {
  254. regulator-name = "vdd_1v8_gen";
  255. regulator-min-microvolt = <1800000>;
  256. regulator-max-microvolt = <1800000>;
  257. regulator-always-on;
  258. };
  259. ldo1_reg: ldo1 {
  260. regulator-name = "vdd_pexa,vdd_pexb";
  261. regulator-min-microvolt = <1050000>;
  262. regulator-max-microvolt = <1050000>;
  263. };
  264. ldo2_reg: ldo2 {
  265. regulator-name = "vdd_sata,avdd_plle";
  266. regulator-min-microvolt = <1050000>;
  267. regulator-max-microvolt = <1050000>;
  268. };
  269. /* LDO3 is not connected to anything */
  270. ldo4_reg: ldo4 {
  271. regulator-name = "vdd_rtc";
  272. regulator-min-microvolt = <1200000>;
  273. regulator-max-microvolt = <1200000>;
  274. regulator-always-on;
  275. };
  276. ldo5_reg: ldo5 {
  277. regulator-name = "vddio_sdmmc,avdd_vdac";
  278. regulator-min-microvolt = <3300000>;
  279. regulator-max-microvolt = <3300000>;
  280. regulator-always-on;
  281. };
  282. ldo6_reg: ldo6 {
  283. regulator-name = "avdd_dsi_csi,pwrdet_mipi";
  284. regulator-min-microvolt = <1200000>;
  285. regulator-max-microvolt = <1200000>;
  286. };
  287. ldo7_reg: ldo7 {
  288. regulator-name = "vdd_pllm,x,u,a_p_c_s";
  289. regulator-min-microvolt = <1200000>;
  290. regulator-max-microvolt = <1200000>;
  291. regulator-always-on;
  292. };
  293. ldo8_reg: ldo8 {
  294. regulator-name = "vdd_ddr_hs";
  295. regulator-min-microvolt = <1000000>;
  296. regulator-max-microvolt = <1000000>;
  297. regulator-always-on;
  298. };
  299. };
  300. };
  301. nct1008: temperature-sensor@4c {
  302. compatible = "onnn,nct1008";
  303. reg = <0x4c>;
  304. vcc-supply = <&sys_3v3_reg>;
  305. interrupt-parent = <&gpio>;
  306. interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
  307. #thermal-sensor-cells = <1>;
  308. };
  309. vdd_core: tps62361@60 {
  310. compatible = "ti,tps62361";
  311. reg = <0x60>;
  312. regulator-name = "tps62361-vout";
  313. regulator-min-microvolt = <500000>;
  314. regulator-max-microvolt = <1500000>;
  315. regulator-coupled-with = <&vddctrl_reg>;
  316. regulator-coupled-max-spread = <300000>;
  317. regulator-max-step-microvolt = <100000>;
  318. regulator-boot-on;
  319. regulator-always-on;
  320. ti,vsel0-state-high;
  321. ti,vsel1-state-high;
  322. nvidia,tegra-core-regulator;
  323. };
  324. };
  325. spi@7000da00 {
  326. status = "okay";
  327. spi-max-frequency = <25000000>;
  328. flash@1 {
  329. compatible = "winbond,w25q32", "jedec,spi-nor";
  330. reg = <1>;
  331. spi-max-frequency = <20000000>;
  332. };
  333. };
  334. pmc@7000e400 {
  335. status = "okay";
  336. nvidia,invert-interrupt;
  337. nvidia,suspend-mode = <1>;
  338. nvidia,cpu-pwr-good-time = <2000>;
  339. nvidia,cpu-pwr-off-time = <200>;
  340. nvidia,core-pwr-good-time = <3845 3845>;
  341. nvidia,core-pwr-off-time = <0>;
  342. nvidia,core-power-req-active-high;
  343. nvidia,sys-clock-req-active-high;
  344. core-supply = <&vdd_core>;
  345. };
  346. ahub@70080000 {
  347. i2s@70080400 {
  348. status = "okay";
  349. };
  350. };
  351. mmc@78000000 {
  352. status = "okay";
  353. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  354. wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
  355. power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
  356. bus-width = <4>;
  357. };
  358. mmc@78000600 {
  359. status = "okay";
  360. bus-width = <8>;
  361. non-removable;
  362. };
  363. usb@7d008000 {
  364. status = "okay";
  365. };
  366. usb-phy@7d008000 {
  367. vbus-supply = <&usb3_vbus_reg>;
  368. status = "okay";
  369. };
  370. backlight: backlight {
  371. compatible = "pwm-backlight";
  372. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  373. power-supply = <&vdd_bl_reg>;
  374. pwms = <&pwm 0 5000000>;
  375. brightness-levels = <0 4 8 16 32 64 128 255>;
  376. default-brightness-level = <6>;
  377. };
  378. clk32k_in: clock-32k {
  379. compatible = "fixed-clock";
  380. clock-frequency = <32768>;
  381. #clock-cells = <0>;
  382. };
  383. cpus {
  384. cpu0: cpu@0 {
  385. cpu-supply = <&vddctrl_reg>;
  386. operating-points-v2 = <&cpu0_opp_table>;
  387. #cooling-cells = <2>;
  388. };
  389. cpu1: cpu@1 {
  390. cpu-supply = <&vddctrl_reg>;
  391. operating-points-v2 = <&cpu0_opp_table>;
  392. #cooling-cells = <2>;
  393. };
  394. cpu2: cpu@2 {
  395. cpu-supply = <&vddctrl_reg>;
  396. operating-points-v2 = <&cpu0_opp_table>;
  397. #cooling-cells = <2>;
  398. };
  399. cpu3: cpu@3 {
  400. cpu-supply = <&vddctrl_reg>;
  401. operating-points-v2 = <&cpu0_opp_table>;
  402. #cooling-cells = <2>;
  403. };
  404. };
  405. panel: panel {
  406. compatible = "chunghwa,claa101wb01";
  407. ddc-i2c-bus = <&panelddc>;
  408. power-supply = <&vdd_pnl1_reg>;
  409. enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
  410. backlight = <&backlight>;
  411. };
  412. vdd_ac_bat_reg: regulator-acbat {
  413. compatible = "regulator-fixed";
  414. regulator-name = "vdd_ac_bat";
  415. regulator-min-microvolt = <5000000>;
  416. regulator-max-microvolt = <5000000>;
  417. regulator-always-on;
  418. };
  419. cam_1v8_reg: regulator-cam {
  420. compatible = "regulator-fixed";
  421. regulator-name = "cam_1v8";
  422. regulator-min-microvolt = <1800000>;
  423. regulator-max-microvolt = <1800000>;
  424. enable-active-high;
  425. gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
  426. vin-supply = <&vio_reg>;
  427. };
  428. cp_5v_reg: regulator-5v0cp {
  429. compatible = "regulator-fixed";
  430. regulator-name = "cp_5v";
  431. regulator-min-microvolt = <5000000>;
  432. regulator-max-microvolt = <5000000>;
  433. regulator-boot-on;
  434. regulator-always-on;
  435. enable-active-high;
  436. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  437. };
  438. emmc_3v3_reg: regulator-emmc {
  439. compatible = "regulator-fixed";
  440. regulator-name = "emmc_3v3";
  441. regulator-min-microvolt = <3300000>;
  442. regulator-max-microvolt = <3300000>;
  443. regulator-always-on;
  444. regulator-boot-on;
  445. enable-active-high;
  446. gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
  447. vin-supply = <&sys_3v3_reg>;
  448. };
  449. modem_3v3_reg: regulator-modem {
  450. compatible = "regulator-fixed";
  451. regulator-name = "modem_3v3";
  452. regulator-min-microvolt = <3300000>;
  453. regulator-max-microvolt = <3300000>;
  454. enable-active-high;
  455. gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
  456. };
  457. pex_hvdd_3v3_reg: regulator-pex {
  458. compatible = "regulator-fixed";
  459. regulator-name = "pex_hvdd_3v3";
  460. regulator-min-microvolt = <3300000>;
  461. regulator-max-microvolt = <3300000>;
  462. enable-active-high;
  463. gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
  464. vin-supply = <&sys_3v3_reg>;
  465. };
  466. vdd_cam1_ldo_reg: regulator-cam1 {
  467. compatible = "regulator-fixed";
  468. regulator-name = "vdd_cam1_ldo";
  469. regulator-min-microvolt = <2800000>;
  470. regulator-max-microvolt = <2800000>;
  471. enable-active-high;
  472. gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
  473. vin-supply = <&sys_3v3_reg>;
  474. };
  475. vdd_cam2_ldo_reg: regulator-cam2 {
  476. compatible = "regulator-fixed";
  477. regulator-name = "vdd_cam2_ldo";
  478. regulator-min-microvolt = <2800000>;
  479. regulator-max-microvolt = <2800000>;
  480. enable-active-high;
  481. gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
  482. vin-supply = <&sys_3v3_reg>;
  483. };
  484. vdd_cam3_ldo_reg: regulator-cam3 {
  485. compatible = "regulator-fixed";
  486. regulator-name = "vdd_cam3_ldo";
  487. regulator-min-microvolt = <3300000>;
  488. regulator-max-microvolt = <3300000>;
  489. enable-active-high;
  490. gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
  491. vin-supply = <&sys_3v3_reg>;
  492. };
  493. vdd_com_reg: regulator-com {
  494. compatible = "regulator-fixed";
  495. regulator-name = "vdd_com";
  496. regulator-min-microvolt = <3300000>;
  497. regulator-max-microvolt = <3300000>;
  498. regulator-always-on;
  499. regulator-boot-on;
  500. enable-active-high;
  501. gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
  502. vin-supply = <&sys_3v3_reg>;
  503. };
  504. vdd_fuse_3v3_reg: regulator-fuse {
  505. compatible = "regulator-fixed";
  506. regulator-name = "vdd_fuse_3v3";
  507. regulator-min-microvolt = <3300000>;
  508. regulator-max-microvolt = <3300000>;
  509. enable-active-high;
  510. gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
  511. vin-supply = <&sys_3v3_reg>;
  512. };
  513. vdd_pnl1_reg: regulator-pnl1 {
  514. compatible = "regulator-fixed";
  515. regulator-name = "vdd_pnl1";
  516. regulator-min-microvolt = <3300000>;
  517. regulator-max-microvolt = <3300000>;
  518. regulator-always-on;
  519. regulator-boot-on;
  520. enable-active-high;
  521. gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
  522. vin-supply = <&sys_3v3_reg>;
  523. };
  524. vdd_vid_reg: regulator-vid {
  525. compatible = "regulator-fixed";
  526. regulator-name = "vddio_vid";
  527. regulator-min-microvolt = <5000000>;
  528. regulator-max-microvolt = <5000000>;
  529. enable-active-high;
  530. gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
  531. gpio-open-drain;
  532. vin-supply = <&vdd_5v0_reg>;
  533. };
  534. sound {
  535. compatible = "nvidia,tegra-audio-wm8903-cardhu",
  536. "nvidia,tegra-audio-wm8903";
  537. nvidia,model = "NVIDIA Tegra Cardhu";
  538. nvidia,audio-routing =
  539. "Headphone Jack", "HPOUTR",
  540. "Headphone Jack", "HPOUTL",
  541. "Int Spk", "ROP",
  542. "Int Spk", "RON",
  543. "Int Spk", "LOP",
  544. "Int Spk", "LON",
  545. "Mic Jack", "MICBIAS",
  546. "IN1L", "Mic Jack";
  547. nvidia,i2s-controller = <&tegra_i2s1>;
  548. nvidia,audio-codec = <&wm8903>;
  549. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  550. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  551. GPIO_ACTIVE_LOW>;
  552. clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
  553. <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  554. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  555. clock-names = "pll_a", "pll_a_out0", "mclk";
  556. assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
  557. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  558. assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  559. <&tegra_car TEGRA30_CLK_EXTERN1>;
  560. };
  561. thermal-zones {
  562. cpu-thermal {
  563. polling-delay-passive = <1000>; /* milliseconds */
  564. polling-delay = <5000>; /* milliseconds */
  565. thermal-sensors = <&nct1008 1>;
  566. trips {
  567. trip0: cpu-alert0 {
  568. /* throttle at 57C until temperature drops to 56.8C */
  569. temperature = <57000>;
  570. hysteresis = <200>;
  571. type = "passive";
  572. };
  573. trip1: cpu-crit {
  574. /* shut down at 60C */
  575. temperature = <60000>;
  576. hysteresis = <2000>;
  577. type = "critical";
  578. };
  579. };
  580. cooling-maps {
  581. map0 {
  582. trip = <&trip0>;
  583. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  584. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  585. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  586. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  587. };
  588. };
  589. };
  590. };
  591. gpio-keys {
  592. compatible = "gpio-keys";
  593. key-power {
  594. label = "Power";
  595. interrupt-parent = <&pmic>;
  596. interrupts = <2 0>;
  597. linux,code = <KEY_POWER>;
  598. debounce-interval = <100>;
  599. wakeup-source;
  600. };
  601. key-volume-down {
  602. label = "Volume Down";
  603. gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
  604. linux,code = <KEY_VOLUMEDOWN>;
  605. debounce-interval = <10>;
  606. };
  607. key-volume-up {
  608. label = "Volume Up";
  609. gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
  610. linux,code = <KEY_VOLUMEUP>;
  611. debounce-interval = <10>;
  612. };
  613. };
  614. };