tegra30-beaver.dts 61 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include "tegra30.dtsi"
  4. #include "tegra30-cpu-opp.dtsi"
  5. #include "tegra30-cpu-opp-microvolt.dtsi"
  6. / {
  7. model = "NVIDIA Tegra30 Beaver evaluation board";
  8. compatible = "nvidia,beaver", "nvidia,tegra30";
  9. aliases {
  10. rtc0 = "/i2c@7000d000/tps65911@2d";
  11. rtc1 = "/rtc@7000e000";
  12. serial0 = &uarta;
  13. };
  14. chosen {
  15. stdout-path = "serial0:115200n8";
  16. };
  17. memory@80000000 {
  18. reg = <0x80000000 0x7ff00000>;
  19. };
  20. pcie@3000 {
  21. status = "okay";
  22. avdd-pexa-supply = <&ldo1_reg>;
  23. vdd-pexa-supply = <&ldo1_reg>;
  24. avdd-pexb-supply = <&ldo1_reg>;
  25. vdd-pexb-supply = <&ldo1_reg>;
  26. avdd-pex-pll-supply = <&ldo1_reg>;
  27. avdd-plle-supply = <&ldo1_reg>;
  28. vddio-pex-ctl-supply = <&sys_3v3_reg>;
  29. hvdd-pex-supply = <&sys_3v3_pexs_reg>;
  30. pci@1,0 {
  31. status = "okay";
  32. nvidia,num-lanes = <2>;
  33. };
  34. pci@2,0 {
  35. nvidia,num-lanes = <2>;
  36. };
  37. pci@3,0 {
  38. status = "okay";
  39. nvidia,num-lanes = <2>;
  40. };
  41. };
  42. host1x@50000000 {
  43. hdmi@54280000 {
  44. status = "okay";
  45. hdmi-supply = <&vdd_5v0_hdmi>;
  46. vdd-supply = <&sys_3v3_reg>;
  47. pll-supply = <&vio_reg>;
  48. nvidia,hpd-gpio =
  49. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  50. nvidia,ddc-i2c-bus = <&hdmiddc>;
  51. };
  52. };
  53. pinmux@70000868 {
  54. pinctrl-names = "default";
  55. pinctrl-0 = <&state_default>;
  56. state_default: pinmux {
  57. clk_32k_out_pa0 {
  58. nvidia,pins = "clk_32k_out_pa0";
  59. nvidia,function = "blink";
  60. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  61. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  62. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  63. };
  64. uart3_cts_n_pa1 {
  65. nvidia,pins = "uart3_cts_n_pa1";
  66. nvidia,function = "uartc";
  67. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  68. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  69. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  70. };
  71. dap2_fs_pa2 {
  72. nvidia,pins = "dap2_fs_pa2";
  73. nvidia,function = "i2s1";
  74. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  75. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  76. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  77. };
  78. dap2_sclk_pa3 {
  79. nvidia,pins = "dap2_sclk_pa3";
  80. nvidia,function = "i2s1";
  81. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  82. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  83. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  84. };
  85. dap2_din_pa4 {
  86. nvidia,pins = "dap2_din_pa4";
  87. nvidia,function = "i2s1";
  88. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  89. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  90. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  91. };
  92. dap2_dout_pa5 {
  93. nvidia,pins = "dap2_dout_pa5";
  94. nvidia,function = "i2s1";
  95. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  96. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  97. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  98. };
  99. sdmmc3_clk_pa6 {
  100. nvidia,pins = "sdmmc3_clk_pa6";
  101. nvidia,function = "sdmmc3";
  102. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  103. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  104. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  105. };
  106. sdmmc3_cmd_pa7 {
  107. nvidia,pins = "sdmmc3_cmd_pa7";
  108. nvidia,function = "sdmmc3";
  109. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  110. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  111. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  112. };
  113. gmi_a17_pb0 {
  114. nvidia,pins = "gmi_a17_pb0";
  115. nvidia,function = "spi4";
  116. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  117. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  118. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  119. };
  120. gmi_a18_pb1 {
  121. nvidia,pins = "gmi_a18_pb1";
  122. nvidia,function = "spi4";
  123. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  124. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  125. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  126. };
  127. lcd_pwr0_pb2 {
  128. nvidia,pins = "lcd_pwr0_pb2";
  129. nvidia,function = "displaya";
  130. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  131. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  132. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  133. };
  134. lcd_pclk_pb3 {
  135. nvidia,pins = "lcd_pclk_pb3";
  136. nvidia,function = "displaya";
  137. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  138. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  139. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  140. };
  141. sdmmc3_dat3_pb4 {
  142. nvidia,pins = "sdmmc3_dat3_pb4";
  143. nvidia,function = "sdmmc3";
  144. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  145. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  146. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  147. };
  148. sdmmc3_dat2_pb5 {
  149. nvidia,pins = "sdmmc3_dat2_pb5";
  150. nvidia,function = "sdmmc3";
  151. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  152. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  153. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  154. };
  155. sdmmc3_dat1_pb6 {
  156. nvidia,pins = "sdmmc3_dat1_pb6";
  157. nvidia,function = "sdmmc3";
  158. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  159. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  160. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  161. };
  162. sdmmc3_dat0_pb7 {
  163. nvidia,pins = "sdmmc3_dat0_pb7";
  164. nvidia,function = "sdmmc3";
  165. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  166. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  167. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  168. };
  169. uart3_rts_n_pc0 {
  170. nvidia,pins = "uart3_rts_n_pc0";
  171. nvidia,function = "uartc";
  172. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  173. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  174. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  175. };
  176. lcd_pwr1_pc1 {
  177. nvidia,pins = "lcd_pwr1_pc1";
  178. nvidia,function = "displaya";
  179. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  180. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  181. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  182. };
  183. uart2_txd_pc2 {
  184. nvidia,pins = "uart2_txd_pc2";
  185. nvidia,function = "uartb";
  186. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  187. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  188. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  189. };
  190. uart2_rxd_pc3 {
  191. nvidia,pins = "uart2_rxd_pc3";
  192. nvidia,function = "uartb";
  193. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  194. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  195. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  196. };
  197. gen1_i2c_scl_pc4 {
  198. nvidia,pins = "gen1_i2c_scl_pc4";
  199. nvidia,function = "i2c1";
  200. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  201. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  202. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  203. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  204. };
  205. gen1_i2c_sda_pc5 {
  206. nvidia,pins = "gen1_i2c_sda_pc5";
  207. nvidia,function = "i2c1";
  208. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  209. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  210. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  211. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  212. };
  213. lcd_pwr2_pc6 {
  214. nvidia,pins = "lcd_pwr2_pc6";
  215. nvidia,function = "displaya";
  216. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  217. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  218. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  219. };
  220. gmi_wp_n_pc7 {
  221. nvidia,pins = "gmi_wp_n_pc7";
  222. nvidia,function = "gmi";
  223. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  224. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  225. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  226. };
  227. sdmmc3_dat5_pd0 {
  228. nvidia,pins = "sdmmc3_dat5_pd0";
  229. nvidia,function = "sdmmc3";
  230. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  231. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  232. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  233. };
  234. sdmmc3_dat4_pd1 {
  235. nvidia,pins = "sdmmc3_dat4_pd1";
  236. nvidia,function = "sdmmc3";
  237. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  238. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  239. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  240. };
  241. lcd_dc1_pd2 {
  242. nvidia,pins = "lcd_dc1_pd2";
  243. nvidia,function = "displaya";
  244. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  245. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  246. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  247. };
  248. sdmmc3_dat6_pd3 {
  249. nvidia,pins = "sdmmc3_dat6_pd3";
  250. nvidia,function = "spdif";
  251. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  252. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  253. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  254. };
  255. sdmmc3_dat7_pd4 {
  256. nvidia,pins = "sdmmc3_dat7_pd4";
  257. nvidia,function = "spdif";
  258. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  259. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  260. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  261. };
  262. vi_d1_pd5 {
  263. nvidia,pins = "vi_d1_pd5";
  264. nvidia,function = "sdmmc2";
  265. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  266. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  267. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  268. };
  269. vi_vsync_pd6 {
  270. nvidia,pins = "vi_vsync_pd6";
  271. nvidia,function = "ddr";
  272. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  273. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  274. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  275. };
  276. vi_hsync_pd7 {
  277. nvidia,pins = "vi_hsync_pd7";
  278. nvidia,function = "ddr";
  279. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  280. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  281. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  282. };
  283. lcd_d0_pe0 {
  284. nvidia,pins = "lcd_d0_pe0";
  285. nvidia,function = "displaya";
  286. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  287. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  288. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  289. };
  290. lcd_d1_pe1 {
  291. nvidia,pins = "lcd_d1_pe1";
  292. nvidia,function = "displaya";
  293. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  294. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  295. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  296. };
  297. lcd_d2_pe2 {
  298. nvidia,pins = "lcd_d2_pe2";
  299. nvidia,function = "displaya";
  300. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  301. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  302. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  303. };
  304. lcd_d3_pe3 {
  305. nvidia,pins = "lcd_d3_pe3";
  306. nvidia,function = "displaya";
  307. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  308. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  309. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  310. };
  311. lcd_d4_pe4 {
  312. nvidia,pins = "lcd_d4_pe4";
  313. nvidia,function = "displaya";
  314. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  315. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  316. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  317. };
  318. lcd_d5_pe5 {
  319. nvidia,pins = "lcd_d5_pe5";
  320. nvidia,function = "displaya";
  321. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  322. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  323. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  324. };
  325. lcd_d6_pe6 {
  326. nvidia,pins = "lcd_d6_pe6";
  327. nvidia,function = "displaya";
  328. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  329. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  330. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  331. };
  332. lcd_d7_pe7 {
  333. nvidia,pins = "lcd_d7_pe7";
  334. nvidia,function = "displaya";
  335. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  336. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  337. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  338. };
  339. lcd_d8_pf0 {
  340. nvidia,pins = "lcd_d8_pf0";
  341. nvidia,function = "displaya";
  342. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  343. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  344. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  345. };
  346. lcd_d9_pf1 {
  347. nvidia,pins = "lcd_d9_pf1";
  348. nvidia,function = "displaya";
  349. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  350. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  351. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  352. };
  353. lcd_d10_pf2 {
  354. nvidia,pins = "lcd_d10_pf2";
  355. nvidia,function = "displaya";
  356. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  357. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  358. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  359. };
  360. lcd_d11_pf3 {
  361. nvidia,pins = "lcd_d11_pf3";
  362. nvidia,function = "displaya";
  363. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  364. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  365. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  366. };
  367. lcd_d12_pf4 {
  368. nvidia,pins = "lcd_d12_pf4";
  369. nvidia,function = "displaya";
  370. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  371. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  372. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  373. };
  374. lcd_d13_pf5 {
  375. nvidia,pins = "lcd_d13_pf5";
  376. nvidia,function = "displaya";
  377. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  378. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  379. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  380. };
  381. lcd_d14_pf6 {
  382. nvidia,pins = "lcd_d14_pf6";
  383. nvidia,function = "displaya";
  384. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  385. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  386. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  387. };
  388. lcd_d15_pf7 {
  389. nvidia,pins = "lcd_d15_pf7";
  390. nvidia,function = "displaya";
  391. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  392. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  393. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  394. };
  395. gmi_ad0_pg0 {
  396. nvidia,pins = "gmi_ad0_pg0";
  397. nvidia,function = "nand";
  398. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  399. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  400. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  401. };
  402. gmi_ad1_pg1 {
  403. nvidia,pins = "gmi_ad1_pg1";
  404. nvidia,function = "nand";
  405. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  406. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  407. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  408. };
  409. gmi_ad2_pg2 {
  410. nvidia,pins = "gmi_ad2_pg2";
  411. nvidia,function = "nand";
  412. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  413. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  414. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  415. };
  416. gmi_ad3_pg3 {
  417. nvidia,pins = "gmi_ad3_pg3";
  418. nvidia,function = "nand";
  419. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  420. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  421. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  422. };
  423. gmi_ad4_pg4 {
  424. nvidia,pins = "gmi_ad4_pg4";
  425. nvidia,function = "nand";
  426. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  427. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  428. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  429. };
  430. gmi_ad5_pg5 {
  431. nvidia,pins = "gmi_ad5_pg5";
  432. nvidia,function = "nand";
  433. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  434. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  435. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  436. };
  437. gmi_ad6_pg6 {
  438. nvidia,pins = "gmi_ad6_pg6";
  439. nvidia,function = "nand";
  440. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  441. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  442. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  443. };
  444. gmi_ad7_pg7 {
  445. nvidia,pins = "gmi_ad7_pg7";
  446. nvidia,function = "nand";
  447. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  448. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  449. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  450. };
  451. gmi_ad8_ph0 {
  452. nvidia,pins = "gmi_ad8_ph0";
  453. nvidia,function = "pwm0";
  454. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  455. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  456. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  457. };
  458. gmi_ad9_ph1 {
  459. nvidia,pins = "gmi_ad9_ph1";
  460. nvidia,function = "pwm1";
  461. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  462. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  463. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  464. };
  465. gmi_ad10_ph2 {
  466. nvidia,pins = "gmi_ad10_ph2";
  467. nvidia,function = "nand";
  468. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  469. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  470. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  471. };
  472. gmi_ad11_ph3 {
  473. nvidia,pins = "gmi_ad11_ph3";
  474. nvidia,function = "nand";
  475. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  476. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  477. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  478. };
  479. gmi_ad12_ph4 {
  480. nvidia,pins = "gmi_ad12_ph4";
  481. nvidia,function = "nand";
  482. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  483. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  484. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  485. };
  486. gmi_ad13_ph5 {
  487. nvidia,pins = "gmi_ad13_ph5";
  488. nvidia,function = "nand";
  489. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  490. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  491. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  492. };
  493. gmi_ad14_ph6 {
  494. nvidia,pins = "gmi_ad14_ph6";
  495. nvidia,function = "nand";
  496. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  497. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  498. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  499. };
  500. gmi_wr_n_pi0 {
  501. nvidia,pins = "gmi_wr_n_pi0";
  502. nvidia,function = "nand";
  503. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  504. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  505. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  506. };
  507. gmi_oe_n_pi1 {
  508. nvidia,pins = "gmi_oe_n_pi1";
  509. nvidia,function = "nand";
  510. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  511. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  512. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  513. };
  514. gmi_dqs_pi2 {
  515. nvidia,pins = "gmi_dqs_pi2";
  516. nvidia,function = "nand";
  517. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  518. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  519. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  520. };
  521. gmi_iordy_pi5 {
  522. nvidia,pins = "gmi_iordy_pi5";
  523. nvidia,function = "rsvd1";
  524. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  525. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  526. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  527. };
  528. gmi_cs7_n_pi6 {
  529. nvidia,pins = "gmi_cs7_n_pi6";
  530. nvidia,function = "nand";
  531. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  532. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  533. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  534. };
  535. gmi_wait_pi7 {
  536. nvidia,pins = "gmi_wait_pi7";
  537. nvidia,function = "nand";
  538. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  539. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  540. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  541. };
  542. lcd_de_pj1 {
  543. nvidia,pins = "lcd_de_pj1";
  544. nvidia,function = "displaya";
  545. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  546. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  547. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  548. };
  549. lcd_hsync_pj3 {
  550. nvidia,pins = "lcd_hsync_pj3";
  551. nvidia,function = "displaya";
  552. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  553. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  554. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  555. };
  556. lcd_vsync_pj4 {
  557. nvidia,pins = "lcd_vsync_pj4";
  558. nvidia,function = "displaya";
  559. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  560. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  561. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  562. };
  563. uart2_cts_n_pj5 {
  564. nvidia,pins = "uart2_cts_n_pj5";
  565. nvidia,function = "uartb";
  566. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  567. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  568. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  569. };
  570. uart2_rts_n_pj6 {
  571. nvidia,pins = "uart2_rts_n_pj6";
  572. nvidia,function = "uartb";
  573. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  574. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  575. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  576. };
  577. gmi_a16_pj7 {
  578. nvidia,pins = "gmi_a16_pj7";
  579. nvidia,function = "spi4";
  580. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  581. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  582. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  583. };
  584. gmi_adv_n_pk0 {
  585. nvidia,pins = "gmi_adv_n_pk0";
  586. nvidia,function = "nand";
  587. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  588. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  589. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  590. };
  591. gmi_clk_pk1 {
  592. nvidia,pins = "gmi_clk_pk1";
  593. nvidia,function = "nand";
  594. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  595. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  596. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  597. };
  598. gmi_cs2_n_pk3 {
  599. nvidia,pins = "gmi_cs2_n_pk3";
  600. nvidia,function = "rsvd1";
  601. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  602. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  603. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  604. };
  605. gmi_cs3_n_pk4 {
  606. nvidia,pins = "gmi_cs3_n_pk4";
  607. nvidia,function = "nand";
  608. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  609. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  610. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  611. };
  612. spdif_out_pk5 {
  613. nvidia,pins = "spdif_out_pk5";
  614. nvidia,function = "spdif";
  615. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  616. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  617. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  618. };
  619. spdif_in_pk6 {
  620. nvidia,pins = "spdif_in_pk6";
  621. nvidia,function = "spdif";
  622. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  623. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  624. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  625. };
  626. gmi_a19_pk7 {
  627. nvidia,pins = "gmi_a19_pk7";
  628. nvidia,function = "spi4";
  629. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  630. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  631. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  632. };
  633. vi_d2_pl0 {
  634. nvidia,pins = "vi_d2_pl0";
  635. nvidia,function = "sdmmc2";
  636. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  637. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  638. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  639. };
  640. vi_d3_pl1 {
  641. nvidia,pins = "vi_d3_pl1";
  642. nvidia,function = "sdmmc2";
  643. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  644. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  645. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  646. };
  647. vi_d4_pl2 {
  648. nvidia,pins = "vi_d4_pl2";
  649. nvidia,function = "vi";
  650. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  651. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  652. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  653. };
  654. vi_d5_pl3 {
  655. nvidia,pins = "vi_d5_pl3";
  656. nvidia,function = "sdmmc2";
  657. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  658. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  659. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  660. };
  661. vi_d6_pl4 {
  662. nvidia,pins = "vi_d6_pl4";
  663. nvidia,function = "vi";
  664. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  665. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  666. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  667. };
  668. vi_d7_pl5 {
  669. nvidia,pins = "vi_d7_pl5";
  670. nvidia,function = "sdmmc2";
  671. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  672. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  673. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  674. };
  675. vi_d8_pl6 {
  676. nvidia,pins = "vi_d8_pl6";
  677. nvidia,function = "sdmmc2";
  678. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  679. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  680. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  681. };
  682. vi_d9_pl7 {
  683. nvidia,pins = "vi_d9_pl7";
  684. nvidia,function = "sdmmc2";
  685. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  686. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  687. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  688. };
  689. lcd_d16_pm0 {
  690. nvidia,pins = "lcd_d16_pm0";
  691. nvidia,function = "displaya";
  692. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  693. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  694. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  695. };
  696. lcd_d17_pm1 {
  697. nvidia,pins = "lcd_d17_pm1";
  698. nvidia,function = "displaya";
  699. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  700. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  701. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  702. };
  703. lcd_d18_pm2 {
  704. nvidia,pins = "lcd_d18_pm2";
  705. nvidia,function = "displaya";
  706. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  707. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  708. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  709. };
  710. lcd_d19_pm3 {
  711. nvidia,pins = "lcd_d19_pm3";
  712. nvidia,function = "displaya";
  713. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  714. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  715. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  716. };
  717. lcd_d20_pm4 {
  718. nvidia,pins = "lcd_d20_pm4";
  719. nvidia,function = "displaya";
  720. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  721. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  722. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  723. };
  724. lcd_d21_pm5 {
  725. nvidia,pins = "lcd_d21_pm5";
  726. nvidia,function = "displaya";
  727. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  728. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  729. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  730. };
  731. lcd_d22_pm6 {
  732. nvidia,pins = "lcd_d22_pm6";
  733. nvidia,function = "displaya";
  734. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  735. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  736. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  737. };
  738. lcd_d23_pm7 {
  739. nvidia,pins = "lcd_d23_pm7";
  740. nvidia,function = "displaya";
  741. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  742. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  743. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  744. };
  745. dap1_fs_pn0 {
  746. nvidia,pins = "dap1_fs_pn0";
  747. nvidia,function = "i2s0";
  748. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  749. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  750. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  751. };
  752. dap1_din_pn1 {
  753. nvidia,pins = "dap1_din_pn1";
  754. nvidia,function = "i2s0";
  755. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  756. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  757. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  758. };
  759. dap1_dout_pn2 {
  760. nvidia,pins = "dap1_dout_pn2";
  761. nvidia,function = "i2s0";
  762. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  763. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  764. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  765. };
  766. dap1_sclk_pn3 {
  767. nvidia,pins = "dap1_sclk_pn3";
  768. nvidia,function = "i2s0";
  769. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  770. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  771. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  772. };
  773. lcd_cs0_n_pn4 {
  774. nvidia,pins = "lcd_cs0_n_pn4";
  775. nvidia,function = "displaya";
  776. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  777. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  778. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  779. };
  780. lcd_sdout_pn5 {
  781. nvidia,pins = "lcd_sdout_pn5";
  782. nvidia,function = "displaya";
  783. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  784. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  785. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  786. };
  787. lcd_dc0_pn6 {
  788. nvidia,pins = "lcd_dc0_pn6";
  789. nvidia,function = "displaya";
  790. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  791. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  792. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  793. };
  794. hdmi_int_pn7 {
  795. nvidia,pins = "hdmi_int_pn7";
  796. nvidia,function = "hdmi";
  797. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  798. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  799. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  800. };
  801. ulpi_data7_po0 {
  802. nvidia,pins = "ulpi_data7_po0";
  803. nvidia,function = "uarta";
  804. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  805. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  806. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  807. };
  808. ulpi_data0_po1 {
  809. nvidia,pins = "ulpi_data0_po1";
  810. nvidia,function = "uarta";
  811. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  812. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  813. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  814. };
  815. ulpi_data1_po2 {
  816. nvidia,pins = "ulpi_data1_po2";
  817. nvidia,function = "uarta";
  818. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  819. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  820. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  821. };
  822. ulpi_data2_po3 {
  823. nvidia,pins = "ulpi_data2_po3";
  824. nvidia,function = "uarta";
  825. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  826. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  827. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  828. };
  829. ulpi_data3_po4 {
  830. nvidia,pins = "ulpi_data3_po4";
  831. nvidia,function = "uarta";
  832. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  833. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  834. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  835. };
  836. ulpi_data4_po5 {
  837. nvidia,pins = "ulpi_data4_po5";
  838. nvidia,function = "uarta";
  839. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  840. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  841. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  842. };
  843. ulpi_data5_po6 {
  844. nvidia,pins = "ulpi_data5_po6";
  845. nvidia,function = "uarta";
  846. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  847. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  848. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  849. };
  850. ulpi_data6_po7 {
  851. nvidia,pins = "ulpi_data6_po7";
  852. nvidia,function = "uarta";
  853. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  854. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  855. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  856. };
  857. dap3_fs_pp0 {
  858. nvidia,pins = "dap3_fs_pp0";
  859. nvidia,function = "i2s2";
  860. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  861. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  862. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  863. };
  864. dap3_din_pp1 {
  865. nvidia,pins = "dap3_din_pp1";
  866. nvidia,function = "i2s2";
  867. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  868. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  869. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  870. };
  871. dap3_dout_pp2 {
  872. nvidia,pins = "dap3_dout_pp2";
  873. nvidia,function = "i2s2";
  874. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  875. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  876. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  877. };
  878. dap3_sclk_pp3 {
  879. nvidia,pins = "dap3_sclk_pp3";
  880. nvidia,function = "i2s2";
  881. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  882. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  883. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  884. };
  885. dap4_fs_pp4 {
  886. nvidia,pins = "dap4_fs_pp4";
  887. nvidia,function = "i2s3";
  888. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  889. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  890. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  891. };
  892. dap4_din_pp5 {
  893. nvidia,pins = "dap4_din_pp5";
  894. nvidia,function = "i2s3";
  895. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  896. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  897. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  898. };
  899. dap4_dout_pp6 {
  900. nvidia,pins = "dap4_dout_pp6";
  901. nvidia,function = "i2s3";
  902. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  903. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  904. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  905. };
  906. dap4_sclk_pp7 {
  907. nvidia,pins = "dap4_sclk_pp7";
  908. nvidia,function = "i2s3";
  909. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  910. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  911. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  912. };
  913. kb_col0_pq0 {
  914. nvidia,pins = "kb_col0_pq0";
  915. nvidia,function = "kbc";
  916. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  917. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  918. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  919. };
  920. kb_col1_pq1 {
  921. nvidia,pins = "kb_col1_pq1";
  922. nvidia,function = "kbc";
  923. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  924. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  925. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  926. };
  927. kb_col2_pq2 {
  928. nvidia,pins = "kb_col2_pq2";
  929. nvidia,function = "kbc";
  930. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  931. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  932. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  933. };
  934. kb_col3_pq3 {
  935. nvidia,pins = "kb_col3_pq3";
  936. nvidia,function = "kbc";
  937. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  938. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  939. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  940. };
  941. kb_col4_pq4 {
  942. nvidia,pins = "kb_col4_pq4";
  943. nvidia,function = "kbc";
  944. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  945. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  946. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  947. };
  948. kb_col5_pq5 {
  949. nvidia,pins = "kb_col5_pq5";
  950. nvidia,function = "kbc";
  951. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  952. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  953. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  954. };
  955. kb_col6_pq6 {
  956. nvidia,pins = "kb_col6_pq6";
  957. nvidia,function = "kbc";
  958. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  959. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  960. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  961. };
  962. kb_col7_pq7 {
  963. nvidia,pins = "kb_col7_pq7";
  964. nvidia,function = "kbc";
  965. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  966. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  967. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  968. };
  969. kb_row0_pr0 {
  970. nvidia,pins = "kb_row0_pr0";
  971. nvidia,function = "kbc";
  972. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  973. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  974. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  975. };
  976. kb_row1_pr1 {
  977. nvidia,pins = "kb_row1_pr1";
  978. nvidia,function = "kbc";
  979. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  980. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  981. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  982. };
  983. kb_row2_pr2 {
  984. nvidia,pins = "kb_row2_pr2";
  985. nvidia,function = "kbc";
  986. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  987. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  988. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  989. };
  990. kb_row3_pr3 {
  991. nvidia,pins = "kb_row3_pr3";
  992. nvidia,function = "kbc";
  993. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  994. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  995. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  996. };
  997. kb_row4_pr4 {
  998. nvidia,pins = "kb_row4_pr4";
  999. nvidia,function = "kbc";
  1000. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1001. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1002. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1003. };
  1004. kb_row5_pr5 {
  1005. nvidia,pins = "kb_row5_pr5";
  1006. nvidia,function = "kbc";
  1007. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1008. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1009. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1010. };
  1011. kb_row6_pr6 {
  1012. nvidia,pins = "kb_row6_pr6";
  1013. nvidia,function = "kbc";
  1014. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1015. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1016. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1017. };
  1018. kb_row7_pr7 {
  1019. nvidia,pins = "kb_row7_pr7";
  1020. nvidia,function = "kbc";
  1021. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1022. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1023. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1024. };
  1025. kb_row8_ps0 {
  1026. nvidia,pins = "kb_row8_ps0";
  1027. nvidia,function = "kbc";
  1028. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1029. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1030. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1031. };
  1032. kb_row9_ps1 {
  1033. nvidia,pins = "kb_row9_ps1";
  1034. nvidia,function = "kbc";
  1035. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1036. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1037. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1038. };
  1039. kb_row10_ps2 {
  1040. nvidia,pins = "kb_row10_ps2";
  1041. nvidia,function = "kbc";
  1042. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1043. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1044. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1045. };
  1046. kb_row11_ps3 {
  1047. nvidia,pins = "kb_row11_ps3";
  1048. nvidia,function = "kbc";
  1049. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1050. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1051. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1052. };
  1053. kb_row12_ps4 {
  1054. nvidia,pins = "kb_row12_ps4";
  1055. nvidia,function = "kbc";
  1056. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1057. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1058. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1059. };
  1060. kb_row13_ps5 {
  1061. nvidia,pins = "kb_row13_ps5";
  1062. nvidia,function = "kbc";
  1063. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1064. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1065. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1066. };
  1067. kb_row14_ps6 {
  1068. nvidia,pins = "kb_row14_ps6";
  1069. nvidia,function = "kbc";
  1070. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1071. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1072. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1073. };
  1074. kb_row15_ps7 {
  1075. nvidia,pins = "kb_row15_ps7";
  1076. nvidia,function = "kbc";
  1077. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1078. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1079. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1080. };
  1081. vi_pclk_pt0 {
  1082. nvidia,pins = "vi_pclk_pt0";
  1083. nvidia,function = "rsvd1";
  1084. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1085. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1086. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1087. };
  1088. vi_mclk_pt1 {
  1089. nvidia,pins = "vi_mclk_pt1";
  1090. nvidia,function = "vi";
  1091. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1092. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1093. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1094. };
  1095. vi_d10_pt2 {
  1096. nvidia,pins = "vi_d10_pt2";
  1097. nvidia,function = "ddr";
  1098. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1099. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1100. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1101. };
  1102. vi_d11_pt3 {
  1103. nvidia,pins = "vi_d11_pt3";
  1104. nvidia,function = "ddr";
  1105. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1106. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1107. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1108. };
  1109. vi_d0_pt4 {
  1110. nvidia,pins = "vi_d0_pt4";
  1111. nvidia,function = "ddr";
  1112. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1113. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1114. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1115. };
  1116. gen2_i2c_scl_pt5 {
  1117. nvidia,pins = "gen2_i2c_scl_pt5";
  1118. nvidia,function = "i2c2";
  1119. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1120. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1121. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1122. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1123. };
  1124. gen2_i2c_sda_pt6 {
  1125. nvidia,pins = "gen2_i2c_sda_pt6";
  1126. nvidia,function = "i2c2";
  1127. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1128. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1129. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1130. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1131. };
  1132. sdmmc4_cmd_pt7 {
  1133. nvidia,pins = "sdmmc4_cmd_pt7";
  1134. nvidia,function = "sdmmc4";
  1135. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1136. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1137. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1138. };
  1139. pu0 {
  1140. nvidia,pins = "pu0";
  1141. nvidia,function = "owr";
  1142. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1143. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1144. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1145. };
  1146. pu1 {
  1147. nvidia,pins = "pu1";
  1148. nvidia,function = "rsvd1";
  1149. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1150. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1151. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1152. };
  1153. pu2 {
  1154. nvidia,pins = "pu2";
  1155. nvidia,function = "rsvd1";
  1156. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1157. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1158. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1159. };
  1160. pu3 {
  1161. nvidia,pins = "pu3";
  1162. nvidia,function = "pwm0";
  1163. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1164. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1165. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1166. };
  1167. pu4 {
  1168. nvidia,pins = "pu4";
  1169. nvidia,function = "pwm1";
  1170. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1171. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1172. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1173. };
  1174. pu5 {
  1175. nvidia,pins = "pu5";
  1176. nvidia,function = "pwm2";
  1177. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1178. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1179. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1180. };
  1181. pu6 {
  1182. nvidia,pins = "pu6";
  1183. nvidia,function = "pwm3";
  1184. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1185. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1186. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1187. };
  1188. jtag_rtck_pu7 {
  1189. nvidia,pins = "jtag_rtck_pu7";
  1190. nvidia,function = "rtck";
  1191. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1192. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1193. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1194. };
  1195. pv0 {
  1196. nvidia,pins = "pv0";
  1197. nvidia,function = "rsvd1";
  1198. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1199. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1200. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1201. };
  1202. pv2 {
  1203. nvidia,pins = "pv2";
  1204. nvidia,function = "owr";
  1205. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1206. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1207. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1208. };
  1209. pv3 {
  1210. nvidia,pins = "pv3";
  1211. nvidia,function = "clk_12m_out";
  1212. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1213. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1214. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1215. };
  1216. ddc_scl_pv4 {
  1217. nvidia,pins = "ddc_scl_pv4";
  1218. nvidia,function = "i2c4";
  1219. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1220. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1221. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1222. };
  1223. ddc_sda_pv5 {
  1224. nvidia,pins = "ddc_sda_pv5";
  1225. nvidia,function = "i2c4";
  1226. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1227. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1228. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1229. };
  1230. crt_hsync_pv6 {
  1231. nvidia,pins = "crt_hsync_pv6";
  1232. nvidia,function = "crt";
  1233. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1234. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1235. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1236. };
  1237. crt_vsync_pv7 {
  1238. nvidia,pins = "crt_vsync_pv7";
  1239. nvidia,function = "crt";
  1240. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1241. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1242. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1243. };
  1244. lcd_cs1_n_pw0 {
  1245. nvidia,pins = "lcd_cs1_n_pw0";
  1246. nvidia,function = "displaya";
  1247. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1248. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1249. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1250. };
  1251. lcd_m1_pw1 {
  1252. nvidia,pins = "lcd_m1_pw1";
  1253. nvidia,function = "displaya";
  1254. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1255. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1256. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1257. };
  1258. spi2_cs1_n_pw2 {
  1259. nvidia,pins = "spi2_cs1_n_pw2";
  1260. nvidia,function = "spi2";
  1261. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1262. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1263. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1264. };
  1265. clk1_out_pw4 {
  1266. nvidia,pins = "clk1_out_pw4";
  1267. nvidia,function = "extperiph1";
  1268. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1269. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1270. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1271. };
  1272. clk2_out_pw5 {
  1273. nvidia,pins = "clk2_out_pw5";
  1274. nvidia,function = "extperiph2";
  1275. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1276. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1277. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1278. };
  1279. uart3_txd_pw6 {
  1280. nvidia,pins = "uart3_txd_pw6";
  1281. nvidia,function = "uartc";
  1282. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1283. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1284. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1285. };
  1286. uart3_rxd_pw7 {
  1287. nvidia,pins = "uart3_rxd_pw7";
  1288. nvidia,function = "uartc";
  1289. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1290. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1291. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1292. };
  1293. spi2_sck_px2 {
  1294. nvidia,pins = "spi2_sck_px2";
  1295. nvidia,function = "gmi";
  1296. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1297. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1298. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1299. };
  1300. spi1_mosi_px4 {
  1301. nvidia,pins = "spi1_mosi_px4";
  1302. nvidia,function = "spi1";
  1303. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1304. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1305. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1306. };
  1307. spi1_sck_px5 {
  1308. nvidia,pins = "spi1_sck_px5";
  1309. nvidia,function = "spi1";
  1310. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1311. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1312. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1313. };
  1314. spi1_cs0_n_px6 {
  1315. nvidia,pins = "spi1_cs0_n_px6";
  1316. nvidia,function = "spi1";
  1317. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1318. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1319. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1320. };
  1321. spi1_miso_px7 {
  1322. nvidia,pins = "spi1_miso_px7";
  1323. nvidia,function = "spi1";
  1324. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1325. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1326. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1327. };
  1328. ulpi_clk_py0 {
  1329. nvidia,pins = "ulpi_clk_py0";
  1330. nvidia,function = "uartd";
  1331. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1332. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1333. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1334. };
  1335. ulpi_dir_py1 {
  1336. nvidia,pins = "ulpi_dir_py1";
  1337. nvidia,function = "uartd";
  1338. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1339. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1340. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1341. };
  1342. ulpi_nxt_py2 {
  1343. nvidia,pins = "ulpi_nxt_py2";
  1344. nvidia,function = "uartd";
  1345. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1346. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1347. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1348. };
  1349. ulpi_stp_py3 {
  1350. nvidia,pins = "ulpi_stp_py3";
  1351. nvidia,function = "uartd";
  1352. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1353. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1354. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1355. };
  1356. sdmmc1_dat3_py4 {
  1357. nvidia,pins = "sdmmc1_dat3_py4";
  1358. nvidia,function = "sdmmc1";
  1359. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1360. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1361. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1362. };
  1363. sdmmc1_dat2_py5 {
  1364. nvidia,pins = "sdmmc1_dat2_py5";
  1365. nvidia,function = "sdmmc1";
  1366. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1367. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1368. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1369. };
  1370. sdmmc1_dat1_py6 {
  1371. nvidia,pins = "sdmmc1_dat1_py6";
  1372. nvidia,function = "sdmmc1";
  1373. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1374. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1375. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1376. };
  1377. sdmmc1_dat0_py7 {
  1378. nvidia,pins = "sdmmc1_dat0_py7";
  1379. nvidia,function = "sdmmc1";
  1380. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1381. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1382. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1383. };
  1384. sdmmc1_clk_pz0 {
  1385. nvidia,pins = "sdmmc1_clk_pz0";
  1386. nvidia,function = "sdmmc1";
  1387. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1388. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1389. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1390. };
  1391. sdmmc1_cmd_pz1 {
  1392. nvidia,pins = "sdmmc1_cmd_pz1";
  1393. nvidia,function = "sdmmc1";
  1394. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1395. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1396. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1397. };
  1398. lcd_sdin_pz2 {
  1399. nvidia,pins = "lcd_sdin_pz2";
  1400. nvidia,function = "displaya";
  1401. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1402. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1403. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1404. };
  1405. lcd_wr_n_pz3 {
  1406. nvidia,pins = "lcd_wr_n_pz3";
  1407. nvidia,function = "displaya";
  1408. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1409. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1410. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1411. };
  1412. lcd_sck_pz4 {
  1413. nvidia,pins = "lcd_sck_pz4";
  1414. nvidia,function = "displaya";
  1415. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1416. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1417. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1418. };
  1419. sys_clk_req_pz5 {
  1420. nvidia,pins = "sys_clk_req_pz5";
  1421. nvidia,function = "sysclk";
  1422. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1423. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1424. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1425. };
  1426. pwr_i2c_scl_pz6 {
  1427. nvidia,pins = "pwr_i2c_scl_pz6";
  1428. nvidia,function = "i2cpwr";
  1429. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1430. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1431. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1432. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1433. };
  1434. pwr_i2c_sda_pz7 {
  1435. nvidia,pins = "pwr_i2c_sda_pz7";
  1436. nvidia,function = "i2cpwr";
  1437. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1438. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1439. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1440. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1441. };
  1442. sdmmc4_dat0_paa0 {
  1443. nvidia,pins = "sdmmc4_dat0_paa0";
  1444. nvidia,function = "sdmmc4";
  1445. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1446. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1447. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1448. };
  1449. sdmmc4_dat1_paa1 {
  1450. nvidia,pins = "sdmmc4_dat1_paa1";
  1451. nvidia,function = "sdmmc4";
  1452. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1453. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1454. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1455. };
  1456. sdmmc4_dat2_paa2 {
  1457. nvidia,pins = "sdmmc4_dat2_paa2";
  1458. nvidia,function = "sdmmc4";
  1459. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1460. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1461. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1462. };
  1463. sdmmc4_dat3_paa3 {
  1464. nvidia,pins = "sdmmc4_dat3_paa3";
  1465. nvidia,function = "sdmmc4";
  1466. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1467. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1468. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1469. };
  1470. sdmmc4_dat4_paa4 {
  1471. nvidia,pins = "sdmmc4_dat4_paa4";
  1472. nvidia,function = "sdmmc4";
  1473. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1474. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1475. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1476. };
  1477. sdmmc4_dat5_paa5 {
  1478. nvidia,pins = "sdmmc4_dat5_paa5";
  1479. nvidia,function = "sdmmc4";
  1480. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1481. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1482. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1483. };
  1484. sdmmc4_dat6_paa6 {
  1485. nvidia,pins = "sdmmc4_dat6_paa6";
  1486. nvidia,function = "sdmmc4";
  1487. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1488. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1489. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1490. };
  1491. sdmmc4_dat7_paa7 {
  1492. nvidia,pins = "sdmmc4_dat7_paa7";
  1493. nvidia,function = "sdmmc4";
  1494. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1495. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1496. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1497. };
  1498. pbb0 {
  1499. nvidia,pins = "pbb0";
  1500. nvidia,function = "i2s4";
  1501. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1502. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1503. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1504. };
  1505. cam_i2c_scl_pbb1 {
  1506. nvidia,pins = "cam_i2c_scl_pbb1";
  1507. nvidia,function = "i2c3";
  1508. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1509. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1510. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1511. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1512. };
  1513. cam_i2c_sda_pbb2 {
  1514. nvidia,pins = "cam_i2c_sda_pbb2";
  1515. nvidia,function = "i2c3";
  1516. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1517. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1518. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1519. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1520. };
  1521. pbb3 {
  1522. nvidia,pins = "pbb3";
  1523. nvidia,function = "vgp3";
  1524. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1525. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1526. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1527. };
  1528. pbb4 {
  1529. nvidia,pins = "pbb4";
  1530. nvidia,function = "vgp4";
  1531. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1532. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1533. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1534. };
  1535. pbb5 {
  1536. nvidia,pins = "pbb5";
  1537. nvidia,function = "vgp5";
  1538. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1539. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1540. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1541. };
  1542. pbb6 {
  1543. nvidia,pins = "pbb6";
  1544. nvidia,function = "vgp6";
  1545. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1546. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1547. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1548. };
  1549. pbb7 {
  1550. nvidia,pins = "pbb7";
  1551. nvidia,function = "i2s4";
  1552. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1553. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1554. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1555. };
  1556. cam_mclk_pcc0 {
  1557. nvidia,pins = "cam_mclk_pcc0";
  1558. nvidia,function = "vi_alt3";
  1559. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1560. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1561. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1562. };
  1563. pcc1 {
  1564. nvidia,pins = "pcc1";
  1565. nvidia,function = "i2s4";
  1566. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1567. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1568. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1569. };
  1570. pcc2 {
  1571. nvidia,pins = "pcc2";
  1572. nvidia,function = "i2s4";
  1573. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1574. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1575. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1576. };
  1577. sdmmc4_rst_n_pcc3 {
  1578. nvidia,pins = "sdmmc4_rst_n_pcc3";
  1579. nvidia,function = "sdmmc4";
  1580. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1581. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1582. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1583. };
  1584. sdmmc4_clk_pcc4 {
  1585. nvidia,pins = "sdmmc4_clk_pcc4";
  1586. nvidia,function = "sdmmc4";
  1587. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1588. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1589. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1590. };
  1591. clk2_req_pcc5 {
  1592. nvidia,pins = "clk2_req_pcc5";
  1593. nvidia,function = "dap";
  1594. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1595. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1596. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1597. };
  1598. pex_l2_rst_n_pcc6 {
  1599. nvidia,pins = "pex_l2_rst_n_pcc6";
  1600. nvidia,function = "pcie";
  1601. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1602. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1603. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1604. };
  1605. pex_l2_clkreq_n_pcc7 {
  1606. nvidia,pins = "pex_l2_clkreq_n_pcc7";
  1607. nvidia,function = "pcie";
  1608. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1609. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1610. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1611. };
  1612. pex_l0_prsnt_n_pdd0 {
  1613. nvidia,pins = "pex_l0_prsnt_n_pdd0";
  1614. nvidia,function = "pcie";
  1615. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1616. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1617. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1618. };
  1619. pex_l0_rst_n_pdd1 {
  1620. nvidia,pins = "pex_l0_rst_n_pdd1";
  1621. nvidia,function = "pcie";
  1622. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1623. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1624. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1625. };
  1626. pex_l0_clkreq_n_pdd2 {
  1627. nvidia,pins = "pex_l0_clkreq_n_pdd2";
  1628. nvidia,function = "pcie";
  1629. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1630. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1631. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1632. };
  1633. pex_wake_n_pdd3 {
  1634. nvidia,pins = "pex_wake_n_pdd3";
  1635. nvidia,function = "pcie";
  1636. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1637. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1638. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1639. };
  1640. pex_l1_prsnt_n_pdd4 {
  1641. nvidia,pins = "pex_l1_prsnt_n_pdd4";
  1642. nvidia,function = "pcie";
  1643. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1644. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1645. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1646. };
  1647. pex_l1_rst_n_pdd5 {
  1648. nvidia,pins = "pex_l1_rst_n_pdd5";
  1649. nvidia,function = "pcie";
  1650. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1651. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1652. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1653. };
  1654. pex_l1_clkreq_n_pdd6 {
  1655. nvidia,pins = "pex_l1_clkreq_n_pdd6";
  1656. nvidia,function = "pcie";
  1657. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1658. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1659. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1660. };
  1661. pex_l2_prsnt_n_pdd7 {
  1662. nvidia,pins = "pex_l2_prsnt_n_pdd7";
  1663. nvidia,function = "pcie";
  1664. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1665. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1666. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1667. };
  1668. clk3_out_pee0 {
  1669. nvidia,pins = "clk3_out_pee0";
  1670. nvidia,function = "extperiph3";
  1671. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1672. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1673. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1674. };
  1675. clk3_req_pee1 {
  1676. nvidia,pins = "clk3_req_pee1";
  1677. nvidia,function = "dev3";
  1678. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1679. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1680. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1681. };
  1682. clk1_req_pee2 {
  1683. nvidia,pins = "clk1_req_pee2";
  1684. nvidia,function = "dap";
  1685. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1686. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1687. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1688. };
  1689. hdmi_cec_pee3 {
  1690. nvidia,pins = "hdmi_cec_pee3";
  1691. nvidia,function = "cec";
  1692. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1693. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1694. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1695. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1696. };
  1697. owr {
  1698. nvidia,pins = "owr";
  1699. nvidia,function = "owr";
  1700. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1701. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1702. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1703. };
  1704. sdio3 {
  1705. nvidia,pins = "drive_sdio3";
  1706. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  1707. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  1708. nvidia,pull-down-strength = <46>;
  1709. nvidia,pull-up-strength = <42>;
  1710. nvidia,slew-rate-rising = <1>;
  1711. nvidia,slew-rate-falling = <1>;
  1712. };
  1713. gpv {
  1714. nvidia,pins = "drive_gpv";
  1715. nvidia,pull-up-strength = <16>;
  1716. };
  1717. };
  1718. };
  1719. serial@70006000 {
  1720. status = "okay";
  1721. };
  1722. i2c@7000c000 {
  1723. status = "okay";
  1724. clock-frequency = <100000>;
  1725. };
  1726. i2c@7000c400 {
  1727. status = "okay";
  1728. clock-frequency = <100000>;
  1729. };
  1730. i2c@7000c500 {
  1731. status = "okay";
  1732. clock-frequency = <100000>;
  1733. };
  1734. hdmiddc: i2c@7000c700 {
  1735. status = "okay";
  1736. clock-frequency = <100000>;
  1737. };
  1738. i2c@7000d000 {
  1739. status = "okay";
  1740. clock-frequency = <100000>;
  1741. rt5640: rt5640@1c {
  1742. compatible = "realtek,rt5640";
  1743. reg = <0x1c>;
  1744. interrupt-parent = <&gpio>;
  1745. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_FALLING>;
  1746. realtek,ldo1-en-gpios =
  1747. <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
  1748. };
  1749. pmic: tps65911@2d {
  1750. compatible = "ti,tps65911";
  1751. reg = <0x2d>;
  1752. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  1753. #interrupt-cells = <2>;
  1754. interrupt-controller;
  1755. wakeup-source;
  1756. ti,system-power-controller;
  1757. #gpio-cells = <2>;
  1758. gpio-controller;
  1759. vcc1-supply = <&vdd_5v_in_reg>;
  1760. vcc2-supply = <&vdd_5v_in_reg>;
  1761. vcc3-supply = <&vio_reg>;
  1762. vcc4-supply = <&vdd_5v_in_reg>;
  1763. vcc5-supply = <&vdd_5v_in_reg>;
  1764. vcc6-supply = <&vdd2_reg>;
  1765. vcc7-supply = <&vdd_5v_in_reg>;
  1766. vccio-supply = <&vdd_5v_in_reg>;
  1767. regulators {
  1768. vdd1_reg: vdd1 {
  1769. regulator-name = "vddio_ddr_1v2";
  1770. regulator-min-microvolt = <1200000>;
  1771. regulator-max-microvolt = <1200000>;
  1772. regulator-always-on;
  1773. };
  1774. vdd2_reg: vdd2 {
  1775. regulator-name = "vdd_1v5_gen";
  1776. regulator-min-microvolt = <1500000>;
  1777. regulator-max-microvolt = <1500000>;
  1778. regulator-always-on;
  1779. };
  1780. vddctrl_reg: vddctrl {
  1781. regulator-name = "vdd_cpu,vdd_sys";
  1782. regulator-min-microvolt = <800000>;
  1783. regulator-max-microvolt = <1250000>;
  1784. regulator-coupled-with = <&core_vdd_reg>;
  1785. regulator-coupled-max-spread = <300000>;
  1786. regulator-max-step-microvolt = <100000>;
  1787. regulator-always-on;
  1788. nvidia,tegra-cpu-regulator;
  1789. };
  1790. vio_reg: vio {
  1791. regulator-name = "vdd_1v8_gen";
  1792. regulator-min-microvolt = <1800000>;
  1793. regulator-max-microvolt = <1800000>;
  1794. regulator-always-on;
  1795. };
  1796. ldo1_reg: ldo1 {
  1797. regulator-name = "vdd_pexa,vdd_pexb";
  1798. regulator-min-microvolt = <1050000>;
  1799. regulator-max-microvolt = <1050000>;
  1800. };
  1801. ldo2_reg: ldo2 {
  1802. regulator-name = "vdd_sata,avdd_plle";
  1803. regulator-min-microvolt = <1050000>;
  1804. regulator-max-microvolt = <1050000>;
  1805. };
  1806. /* LDO3 is not connected to anything */
  1807. ldo4_reg: ldo4 {
  1808. regulator-name = "vdd_rtc";
  1809. regulator-min-microvolt = <1200000>;
  1810. regulator-max-microvolt = <1200000>;
  1811. regulator-always-on;
  1812. };
  1813. ldo5_reg: ldo5 {
  1814. regulator-name = "vddio_sdmmc,avdd_vdac";
  1815. regulator-min-microvolt = <1800000>;
  1816. regulator-max-microvolt = <3300000>;
  1817. regulator-always-on;
  1818. };
  1819. ldo6_reg: ldo6 {
  1820. regulator-name = "avdd_dsi_csi,pwrdet_mipi";
  1821. regulator-min-microvolt = <1200000>;
  1822. regulator-max-microvolt = <1200000>;
  1823. };
  1824. ldo7_reg: ldo7 {
  1825. regulator-name = "vdd_pllm,x,u,a_p_c_s";
  1826. regulator-min-microvolt = <1200000>;
  1827. regulator-max-microvolt = <1200000>;
  1828. regulator-always-on;
  1829. };
  1830. ldo8_reg: ldo8 {
  1831. regulator-name = "vdd_ddr_hs";
  1832. regulator-min-microvolt = <1000000>;
  1833. regulator-max-microvolt = <1000000>;
  1834. regulator-always-on;
  1835. };
  1836. };
  1837. };
  1838. core_vdd_reg: tps62361@60 {
  1839. compatible = "ti,tps62361";
  1840. reg = <0x60>;
  1841. regulator-name = "tps62361-vout";
  1842. regulator-min-microvolt = <500000>;
  1843. regulator-max-microvolt = <1500000>;
  1844. regulator-coupled-with = <&vddctrl_reg>;
  1845. regulator-coupled-max-spread = <300000>;
  1846. regulator-max-step-microvolt = <100000>;
  1847. regulator-boot-on;
  1848. regulator-always-on;
  1849. ti,vsel0-state-high;
  1850. ti,vsel1-state-high;
  1851. nvidia,tegra-core-regulator;
  1852. };
  1853. };
  1854. spi@7000da00 {
  1855. status = "okay";
  1856. spi-max-frequency = <25000000>;
  1857. flash@1 {
  1858. compatible = "winbond,w25q32", "jedec,spi-nor";
  1859. reg = <1>;
  1860. spi-max-frequency = <20000000>;
  1861. };
  1862. };
  1863. pmc@7000e400 {
  1864. status = "okay";
  1865. nvidia,invert-interrupt;
  1866. nvidia,suspend-mode = <1>;
  1867. nvidia,cpu-pwr-good-time = <2000>;
  1868. nvidia,cpu-pwr-off-time = <200>;
  1869. nvidia,core-pwr-good-time = <3845 3845>;
  1870. nvidia,core-pwr-off-time = <0>;
  1871. nvidia,core-power-req-active-high;
  1872. nvidia,sys-clock-req-active-high;
  1873. core-supply = <&core_vdd_reg>;
  1874. };
  1875. ahub@70080000 {
  1876. i2s@70080400 {
  1877. status = "okay";
  1878. };
  1879. };
  1880. mmc@78000000 {
  1881. status = "okay";
  1882. vqmmc-supply = <&ldo5_reg>;
  1883. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  1884. wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
  1885. power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
  1886. bus-width = <4>;
  1887. };
  1888. mmc@78000600 {
  1889. status = "okay";
  1890. bus-width = <8>;
  1891. non-removable;
  1892. };
  1893. usb@7d000000 {
  1894. compatible = "nvidia,tegra30-udc";
  1895. status = "okay";
  1896. dr_mode = "peripheral";
  1897. };
  1898. usb-phy@7d000000 {
  1899. status = "okay";
  1900. };
  1901. usb@7d004000 {
  1902. status = "okay";
  1903. };
  1904. phy2: usb-phy@7d004000 {
  1905. vbus-supply = <&sys_3v3_reg>;
  1906. status = "okay";
  1907. };
  1908. usb@7d008000 {
  1909. status = "okay";
  1910. };
  1911. usb-phy@7d008000 {
  1912. vbus-supply = <&usb3_vbus_reg>;
  1913. status = "okay";
  1914. };
  1915. clk32k_in: clock-32k {
  1916. compatible = "fixed-clock";
  1917. clock-frequency = <32768>;
  1918. #clock-cells = <0>;
  1919. };
  1920. gpio-leds {
  1921. compatible = "gpio-leds";
  1922. gpled1 {
  1923. label = "LED1"; /* CR5A1 (blue) */
  1924. gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
  1925. };
  1926. gpled2 {
  1927. label = "LED2"; /* CR4A2 (green) */
  1928. gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
  1929. };
  1930. };
  1931. vdd_5v_in_reg: regulator-5v0 {
  1932. compatible = "regulator-fixed";
  1933. regulator-name = "vdd_5v_in";
  1934. regulator-min-microvolt = <5000000>;
  1935. regulator-max-microvolt = <5000000>;
  1936. regulator-always-on;
  1937. };
  1938. chargepump_5v_reg: regulator-chargepump {
  1939. compatible = "regulator-fixed";
  1940. regulator-name = "chargepump_5v";
  1941. regulator-min-microvolt = <5000000>;
  1942. regulator-max-microvolt = <5000000>;
  1943. regulator-boot-on;
  1944. regulator-always-on;
  1945. enable-active-high;
  1946. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  1947. };
  1948. ddr_reg: regulator-ddr {
  1949. compatible = "regulator-fixed";
  1950. regulator-name = "vdd_ddr";
  1951. regulator-min-microvolt = <1500000>;
  1952. regulator-max-microvolt = <1500000>;
  1953. regulator-always-on;
  1954. regulator-boot-on;
  1955. enable-active-high;
  1956. gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
  1957. vin-supply = <&vdd_5v_in_reg>;
  1958. };
  1959. vdd_5v_sata_reg: regulator-sata {
  1960. compatible = "regulator-fixed";
  1961. regulator-name = "vdd_5v_sata";
  1962. regulator-min-microvolt = <5000000>;
  1963. regulator-max-microvolt = <5000000>;
  1964. regulator-always-on;
  1965. regulator-boot-on;
  1966. enable-active-high;
  1967. gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
  1968. vin-supply = <&vdd_5v_in_reg>;
  1969. };
  1970. usb1_vbus_reg: regulator-usb1 {
  1971. compatible = "regulator-fixed";
  1972. regulator-name = "usb1_vbus";
  1973. regulator-min-microvolt = <5000000>;
  1974. regulator-max-microvolt = <5000000>;
  1975. enable-active-high;
  1976. gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
  1977. gpio-open-drain;
  1978. vin-supply = <&vdd_5v_in_reg>;
  1979. };
  1980. usb3_vbus_reg: regulator-usb3 {
  1981. compatible = "regulator-fixed";
  1982. regulator-name = "usb3_vbus";
  1983. regulator-min-microvolt = <5000000>;
  1984. regulator-max-microvolt = <5000000>;
  1985. enable-active-high;
  1986. gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
  1987. gpio-open-drain;
  1988. vin-supply = <&vdd_5v_in_reg>;
  1989. };
  1990. sys_3v3_reg: regulator-3v3 {
  1991. compatible = "regulator-fixed";
  1992. regulator-name = "sys_3v3,vdd_3v3_alw";
  1993. regulator-min-microvolt = <3300000>;
  1994. regulator-max-microvolt = <3300000>;
  1995. regulator-always-on;
  1996. regulator-boot-on;
  1997. enable-active-high;
  1998. gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
  1999. vin-supply = <&vdd_5v_in_reg>;
  2000. };
  2001. sys_3v3_pexs_reg: regulator-pexs {
  2002. compatible = "regulator-fixed";
  2003. regulator-name = "sys_3v3_pexs";
  2004. regulator-min-microvolt = <3300000>;
  2005. regulator-max-microvolt = <3300000>;
  2006. regulator-always-on;
  2007. regulator-boot-on;
  2008. enable-active-high;
  2009. gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
  2010. vin-supply = <&sys_3v3_reg>;
  2011. };
  2012. vdd_5v0_hdmi: regulator-hdmi {
  2013. compatible = "regulator-fixed";
  2014. regulator-name = "+VDD_5V_HDMI";
  2015. regulator-min-microvolt = <5000000>;
  2016. regulator-max-microvolt = <5000000>;
  2017. regulator-always-on;
  2018. regulator-boot-on;
  2019. vin-supply = <&sys_3v3_reg>;
  2020. };
  2021. sound {
  2022. compatible = "nvidia,tegra-audio-rt5640-beaver",
  2023. "nvidia,tegra-audio-rt5640";
  2024. nvidia,model = "NVIDIA Tegra Beaver";
  2025. nvidia,audio-routing =
  2026. "Headphones", "HPOR",
  2027. "Headphones", "HPOL",
  2028. "Mic Jack", "MICBIAS1",
  2029. "IN2P", "Mic Jack";
  2030. nvidia,i2s-controller = <&tegra_i2s1>;
  2031. nvidia,audio-codec = <&rt5640>;
  2032. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
  2033. clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
  2034. <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  2035. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  2036. clock-names = "pll_a", "pll_a_out0", "mclk";
  2037. assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
  2038. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  2039. assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  2040. <&tegra_car TEGRA30_CLK_EXTERN1>;
  2041. };
  2042. cpus {
  2043. cpu0: cpu@0 {
  2044. cpu-supply = <&vddctrl_reg>;
  2045. operating-points-v2 = <&cpu0_opp_table>;
  2046. };
  2047. cpu@1 {
  2048. cpu-supply = <&vddctrl_reg>;
  2049. operating-points-v2 = <&cpu0_opp_table>;
  2050. };
  2051. cpu@2 {
  2052. cpu-supply = <&vddctrl_reg>;
  2053. operating-points-v2 = <&cpu0_opp_table>;
  2054. };
  2055. cpu@3 {
  2056. cpu-supply = <&vddctrl_reg>;
  2057. operating-points-v2 = <&cpu0_opp_table>;
  2058. };
  2059. };
  2060. };