tegra30-asus-transformer-common.dtsi 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/input/gpio-keys.h>
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/thermal/thermal.h>
  5. #include "tegra30.dtsi"
  6. #include "tegra30-cpu-opp.dtsi"
  7. #include "tegra30-cpu-opp-microvolt.dtsi"
  8. / {
  9. chassis-type = "convertible";
  10. aliases {
  11. mmc0 = "/mmc@78000600"; /* eMMC */
  12. mmc1 = "/mmc@78000000"; /* uSD slot */
  13. mmc2 = "/mmc@78000400"; /* WiFi */
  14. rtc0 = &pmic;
  15. rtc1 = "/rtc@7000e000";
  16. display0 = &lcd;
  17. display1 = &hdmi;
  18. serial1 = &uartc; /* Bluetooth */
  19. serial2 = &uartb; /* GPS */
  20. };
  21. /*
  22. * The decompressor and also some bootloaders rely on a
  23. * pre-existing /chosen node to be available to insert the
  24. * command line and merge other ATAGS info.
  25. */
  26. chosen {};
  27. memory@80000000 {
  28. reg = <0x80000000 0x40000000>;
  29. };
  30. reserved-memory {
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. ranges;
  34. linux,cma@80000000 {
  35. compatible = "shared-dma-pool";
  36. alloc-ranges = <0x80000000 0x30000000>;
  37. size = <0x10000000>; /* 256MiB */
  38. linux,cma-default;
  39. reusable;
  40. };
  41. ramoops@beb00000 {
  42. compatible = "ramoops";
  43. reg = <0xbeb00000 0x10000>; /* 64kB */
  44. console-size = <0x8000>; /* 32kB */
  45. record-size = <0x400>; /* 1kB */
  46. ecc-size = <16>;
  47. };
  48. trustzone@bfe00000 {
  49. reg = <0xbfe00000 0x200000>; /* 2MB */
  50. no-map;
  51. };
  52. };
  53. host1x@50000000 {
  54. hdmi: hdmi@54280000 {
  55. status = "okay";
  56. hdmi-supply = <&hdmi_5v0_sys>;
  57. pll-supply = <&vdd_1v8_vio>;
  58. vdd-supply = <&vdd_3v3_sys>;
  59. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  60. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  61. };
  62. };
  63. gpio@6000d000 {
  64. init-lpm-in-hog {
  65. gpio-hog;
  66. gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>,
  67. <TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
  68. input;
  69. };
  70. init-lpm-out-hog {
  71. gpio-hog;
  72. gpios = <TEGRA_GPIO(K, 7) GPIO_ACTIVE_HIGH>,
  73. <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
  74. output-low;
  75. };
  76. usb-charge-limit-hog {
  77. gpio-hog;
  78. gpios = <TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
  79. output-high;
  80. };
  81. };
  82. vde@6001a000 {
  83. assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
  84. assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
  85. assigned-clock-rates = <408000000>;
  86. };
  87. pinmux@70000868 {
  88. pinctrl-names = "default";
  89. pinctrl-0 = <&state_default>;
  90. state_default: pinmux {
  91. /* SDMMC1 pinmux */
  92. sdmmc1_clk {
  93. nvidia,pins = "sdmmc1_clk_pz0";
  94. nvidia,function = "sdmmc1";
  95. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  96. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  97. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  98. };
  99. sdmmc1_cmd {
  100. nvidia,pins = "sdmmc1_dat3_py4",
  101. "sdmmc1_dat2_py5",
  102. "sdmmc1_dat1_py6",
  103. "sdmmc1_dat0_py7",
  104. "sdmmc1_cmd_pz1";
  105. nvidia,function = "sdmmc1";
  106. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  107. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  108. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  109. };
  110. sdmmc1_cd {
  111. nvidia,pins = "gmi_iordy_pi5";
  112. nvidia,function = "rsvd1";
  113. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  114. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  115. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  116. };
  117. sdmmc1_wp {
  118. nvidia,pins = "vi_d11_pt3";
  119. nvidia,function = "rsvd2";
  120. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  121. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  122. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  123. };
  124. /* SDMMC2 pinmux */
  125. vi_d1_pd5 {
  126. nvidia,pins = "vi_d1_pd5",
  127. "vi_d2_pl0",
  128. "vi_d3_pl1",
  129. "vi_d5_pl3",
  130. "vi_d7_pl5";
  131. nvidia,function = "sdmmc2";
  132. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  133. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  134. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  135. };
  136. vi_d8_pl6 {
  137. nvidia,pins = "vi_d8_pl6",
  138. "vi_d9_pl7";
  139. nvidia,function = "sdmmc2";
  140. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  141. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  142. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  143. nvidia,lock = <0>;
  144. nvidia,ioreset = <0>;
  145. };
  146. /* SDMMC3 pinmux */
  147. sdmmc3_clk {
  148. nvidia,pins = "sdmmc3_clk_pa6";
  149. nvidia,function = "sdmmc3";
  150. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  151. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  152. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  153. };
  154. sdmmc3_cmd {
  155. nvidia,pins = "sdmmc3_cmd_pa7",
  156. "sdmmc3_dat0_pb7",
  157. "sdmmc3_dat1_pb6",
  158. "sdmmc3_dat2_pb5",
  159. "sdmmc3_dat3_pb4",
  160. "sdmmc3_dat4_pd1",
  161. "sdmmc3_dat5_pd0",
  162. "sdmmc3_dat6_pd3",
  163. "sdmmc3_dat7_pd4";
  164. nvidia,function = "sdmmc3";
  165. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  166. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  167. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  168. };
  169. /* SDMMC4 pinmux */
  170. sdmmc4_clk {
  171. nvidia,pins = "sdmmc4_clk_pcc4";
  172. nvidia,function = "sdmmc4";
  173. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  174. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  175. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  176. };
  177. sdmmc4_cmd {
  178. nvidia,pins = "sdmmc4_cmd_pt7",
  179. "sdmmc4_dat0_paa0",
  180. "sdmmc4_dat1_paa1",
  181. "sdmmc4_dat2_paa2",
  182. "sdmmc4_dat3_paa3",
  183. "sdmmc4_dat4_paa4",
  184. "sdmmc4_dat5_paa5",
  185. "sdmmc4_dat6_paa6",
  186. "sdmmc4_dat7_paa7";
  187. nvidia,function = "sdmmc4";
  188. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  189. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  190. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  191. };
  192. sdmmc4_rst_n {
  193. nvidia,pins = "sdmmc4_rst_n_pcc3";
  194. nvidia,function = "rsvd2";
  195. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  196. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  197. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  198. };
  199. cam_mclk {
  200. nvidia,pins = "cam_mclk_pcc0";
  201. nvidia,function = "vi_alt3";
  202. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  203. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  204. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  205. };
  206. drive_sdmmc4 {
  207. nvidia,pins = "drive_gma",
  208. "drive_gmb",
  209. "drive_gmc",
  210. "drive_gmd";
  211. nvidia,pull-down-strength = <9>;
  212. nvidia,pull-up-strength = <9>;
  213. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  214. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  215. };
  216. /* I2C pinmux */
  217. gen1_i2c {
  218. nvidia,pins = "gen1_i2c_scl_pc4",
  219. "gen1_i2c_sda_pc5";
  220. nvidia,function = "i2c1";
  221. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  222. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  223. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  224. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  225. nvidia,lock = <0>;
  226. };
  227. gen2_i2c {
  228. nvidia,pins = "gen2_i2c_scl_pt5",
  229. "gen2_i2c_sda_pt6";
  230. nvidia,function = "i2c2";
  231. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  232. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  233. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  234. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  235. nvidia,lock = <0>;
  236. };
  237. cam_i2c {
  238. nvidia,pins = "cam_i2c_scl_pbb1",
  239. "cam_i2c_sda_pbb2";
  240. nvidia,function = "i2c3";
  241. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  242. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  243. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  244. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  245. nvidia,lock = <0>;
  246. };
  247. ddc_i2c {
  248. nvidia,pins = "ddc_scl_pv4",
  249. "ddc_sda_pv5";
  250. nvidia,function = "i2c4";
  251. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  252. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  253. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  254. nvidia,lock = <0>;
  255. };
  256. pwr_i2c {
  257. nvidia,pins = "pwr_i2c_scl_pz6",
  258. "pwr_i2c_sda_pz7";
  259. nvidia,function = "i2cpwr";
  260. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  261. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  262. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  263. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  264. nvidia,lock = <0>;
  265. };
  266. hotplug_i2c {
  267. nvidia,pins = "pu4";
  268. nvidia,function = "rsvd4";
  269. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  270. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  271. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  272. };
  273. /* HDMI pinmux */
  274. hdmi_cec {
  275. nvidia,pins = "hdmi_cec_pee3";
  276. nvidia,function = "cec";
  277. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  278. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  279. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  280. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  281. nvidia,lock = <0>;
  282. };
  283. hdmi_hpd {
  284. nvidia,pins = "hdmi_int_pn7";
  285. nvidia,function = "hdmi";
  286. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  287. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  288. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  289. };
  290. /* UART-A */
  291. ulpi_data0_po1 {
  292. nvidia,pins = "ulpi_data0_po1";
  293. nvidia,function = "uarta";
  294. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  295. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  296. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  297. };
  298. ulpi_data1_po2 {
  299. nvidia,pins = "ulpi_data1_po2";
  300. nvidia,function = "uarta";
  301. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  302. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  303. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  304. };
  305. ulpi_data5_po6 {
  306. nvidia,pins = "ulpi_data5_po6";
  307. nvidia,function = "uarta";
  308. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  309. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  310. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  311. };
  312. ulpi_data7_po0 {
  313. nvidia,pins = "ulpi_data7_po0",
  314. "ulpi_data2_po3",
  315. "ulpi_data3_po4",
  316. "ulpi_data4_po5",
  317. "ulpi_data6_po7";
  318. nvidia,function = "uarta";
  319. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  320. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  321. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  322. };
  323. /* UART-B */
  324. uartb_txd_rts {
  325. nvidia,pins = "uart2_txd_pc2",
  326. "uart2_rts_n_pj6";
  327. nvidia,function = "uartb";
  328. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  329. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  330. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  331. };
  332. uartb_rxd_cts {
  333. nvidia,pins = "uart2_rxd_pc3",
  334. "uart2_cts_n_pj5";
  335. nvidia,function = "uartb";
  336. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  337. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  338. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  339. };
  340. /* UART-C */
  341. uartc_rxd_cts {
  342. nvidia,pins = "uart3_cts_n_pa1",
  343. "uart3_rxd_pw7";
  344. nvidia,function = "uartc";
  345. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  346. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  347. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  348. };
  349. uartc_txd_rts {
  350. nvidia,pins = "uart3_rts_n_pc0",
  351. "uart3_txd_pw6";
  352. nvidia,function = "uartc";
  353. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  354. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  355. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  356. };
  357. /* UART-D */
  358. ulpi_nxt_py2 {
  359. nvidia,pins = "ulpi_nxt_py2";
  360. nvidia,function = "uartd";
  361. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  362. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  363. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  364. };
  365. ulpi_clk_py0 {
  366. nvidia,pins = "ulpi_clk_py0",
  367. "ulpi_dir_py1",
  368. "ulpi_stp_py3";
  369. nvidia,function = "uartd";
  370. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  371. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  372. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  373. };
  374. /* I2S pinmux */
  375. dap_i2s0 {
  376. nvidia,pins = "dap1_fs_pn0",
  377. "dap1_din_pn1",
  378. "dap1_dout_pn2",
  379. "dap1_sclk_pn3";
  380. nvidia,function = "i2s0";
  381. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  382. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  383. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  384. };
  385. dap_i2s1 {
  386. nvidia,pins = "dap2_fs_pa2",
  387. "dap2_sclk_pa3",
  388. "dap2_din_pa4",
  389. "dap2_dout_pa5";
  390. nvidia,function = "i2s1";
  391. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  392. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  393. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  394. };
  395. dap3_fs {
  396. nvidia,pins = "dap3_fs_pp0",
  397. "dap3_din_pp1";
  398. nvidia,function = "i2s2";
  399. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  400. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  401. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  402. };
  403. dap3_dout {
  404. nvidia,pins = "dap3_dout_pp2",
  405. "dap3_sclk_pp3";
  406. nvidia,function = "i2s2";
  407. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  408. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  409. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  410. };
  411. dap_i2s3 {
  412. nvidia,pins = "dap4_fs_pp4",
  413. "dap4_din_pp5",
  414. "dap4_dout_pp6",
  415. "dap4_sclk_pp7";
  416. nvidia,function = "i2s3";
  417. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  418. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  419. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  420. };
  421. /* Sensors pinmux */
  422. nct_irq {
  423. nvidia,pins = "pcc2";
  424. nvidia,function = "i2s4";
  425. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  426. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  427. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  428. };
  429. /* Asus EC pinmux */
  430. ec_irqs {
  431. nvidia,pins = "kb_row10_ps2",
  432. "kb_row15_ps7";
  433. nvidia,function = "kbc";
  434. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  435. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  436. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  437. };
  438. ec_reqs {
  439. nvidia,pins = "kb_col1_pq1";
  440. nvidia,function = "kbc";
  441. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  442. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  443. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  444. };
  445. /* Memory type bootstrap */
  446. mem_boostraps {
  447. nvidia,pins = "gmi_ad4_pg4",
  448. "gmi_ad5_pg5";
  449. nvidia,function = "nand";
  450. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  451. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  452. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  453. };
  454. /* PCI-e pinmux */
  455. pex_l2_rst_n {
  456. nvidia,pins = "pex_l2_rst_n_pcc6",
  457. "pex_l0_rst_n_pdd1",
  458. "pex_l1_rst_n_pdd5";
  459. nvidia,function = "pcie";
  460. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  461. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  462. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  463. };
  464. pex_l2_clkreq_n {
  465. nvidia,pins = "pex_l2_clkreq_n_pcc7",
  466. "pex_l0_prsnt_n_pdd0",
  467. "pex_l0_clkreq_n_pdd2",
  468. "pex_wake_n_pdd3",
  469. "pex_l1_prsnt_n_pdd4",
  470. "pex_l1_clkreq_n_pdd6",
  471. "pex_l2_prsnt_n_pdd7";
  472. nvidia,function = "pcie";
  473. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  474. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  475. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  476. };
  477. /* SPI pinmux */
  478. spi1_mosi_px4 {
  479. nvidia,pins = "spi1_mosi_px4",
  480. "spi1_sck_px5",
  481. "spi1_cs0_n_px6",
  482. "spi1_miso_px7";
  483. nvidia,function = "spi1";
  484. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  485. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  486. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  487. };
  488. spi2_cs1_n_pw2 {
  489. nvidia,pins = "spi2_cs1_n_pw2";
  490. nvidia,function = "spi2";
  491. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  492. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  493. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  494. };
  495. spi2_sck_px2 {
  496. nvidia,pins = "spi2_sck_px2";
  497. nvidia,function = "spi2";
  498. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  499. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  500. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  501. };
  502. gmi_a17_pb0 {
  503. nvidia,pins = "gmi_a17_pb0",
  504. "gmi_a16_pj7";
  505. nvidia,function = "spi4";
  506. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  507. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  508. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  509. };
  510. gmi_a18_pb1 {
  511. nvidia,pins = "gmi_a18_pb1";
  512. nvidia,function = "spi4";
  513. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  514. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  515. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  516. };
  517. gmi_a19_pk7 {
  518. nvidia,pins = "gmi_a19_pk7";
  519. nvidia,function = "spi4";
  520. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  521. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  522. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  523. };
  524. /* Display A pinmux */
  525. lcd_pwr0_pb2 {
  526. nvidia,pins = "lcd_pwr0_pb2",
  527. "lcd_pclk_pb3",
  528. "lcd_pwr1_pc1",
  529. "lcd_d0_pe0",
  530. "lcd_d1_pe1",
  531. "lcd_d2_pe2",
  532. "lcd_d3_pe3",
  533. "lcd_d4_pe4",
  534. "lcd_d5_pe5",
  535. "lcd_d6_pe6",
  536. "lcd_d7_pe7",
  537. "lcd_d8_pf0",
  538. "lcd_d9_pf1",
  539. "lcd_d10_pf2",
  540. "lcd_d11_pf3",
  541. "lcd_d12_pf4",
  542. "lcd_d13_pf5",
  543. "lcd_d14_pf6",
  544. "lcd_d15_pf7",
  545. "lcd_de_pj1",
  546. "lcd_hsync_pj3",
  547. "lcd_vsync_pj4",
  548. "lcd_d16_pm0",
  549. "lcd_d17_pm1",
  550. "lcd_d18_pm2",
  551. "lcd_d19_pm3",
  552. "lcd_d20_pm4",
  553. "lcd_d21_pm5",
  554. "lcd_d22_pm6",
  555. "lcd_d23_pm7",
  556. "lcd_dc0_pn6",
  557. "lcd_sdin_pz2";
  558. nvidia,function = "displaya";
  559. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  560. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  561. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  562. };
  563. lcd_cs0_n_pn4 {
  564. nvidia,pins = "lcd_cs0_n_pn4",
  565. "lcd_sdout_pn5",
  566. "lcd_wr_n_pz3";
  567. nvidia,function = "displaya";
  568. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  569. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  570. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  571. };
  572. blink {
  573. nvidia,pins = "clk_32k_out_pa0";
  574. nvidia,function = "blink";
  575. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  576. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  577. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  578. };
  579. /* KBC keys */
  580. kb_col0_pq0 {
  581. nvidia,pins = "kb_col0_pq0";
  582. nvidia,function = "kbc";
  583. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  584. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  585. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  586. };
  587. kb_col1_pq1 {
  588. nvidia,pins = "kb_row1_pr1",
  589. "kb_row3_pr3",
  590. "kb_row8_ps0",
  591. "kb_row14_ps6";
  592. nvidia,function = "kbc";
  593. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  594. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  595. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  596. };
  597. kb_col4_pq4 {
  598. nvidia,pins = "kb_col4_pq4",
  599. "kb_col5_pq5",
  600. "kb_col7_pq7",
  601. "kb_row2_pr2",
  602. "kb_row4_pr4",
  603. "kb_row5_pr5",
  604. "kb_row12_ps4",
  605. "kb_row13_ps5";
  606. nvidia,function = "kbc";
  607. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  608. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  609. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  610. };
  611. gmi_wp_n_pc7 {
  612. nvidia,pins = "gmi_wp_n_pc7",
  613. "gmi_wait_pi7",
  614. "gmi_cs3_n_pk4";
  615. nvidia,function = "rsvd1";
  616. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  617. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  618. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  619. };
  620. gmi_cs0_n_pj0 {
  621. nvidia,pins = "gmi_cs0_n_pj0",
  622. "gmi_cs1_n_pj2",
  623. "gmi_cs2_n_pk3";
  624. nvidia,function = "rsvd1";
  625. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  626. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  627. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  628. };
  629. vi_pclk_pt0 {
  630. nvidia,pins = "vi_pclk_pt0";
  631. nvidia,function = "rsvd1";
  632. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  633. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  634. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  635. nvidia,lock = <0>;
  636. nvidia,ioreset = <0>;
  637. };
  638. /* GPIO keys pinmux */
  639. power_key {
  640. nvidia,pins = "pv0";
  641. nvidia,function = "rsvd1";
  642. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  643. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  644. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  645. };
  646. vol_keys {
  647. nvidia,pins = "kb_col2_pq2",
  648. "kb_col3_pq3";
  649. nvidia,function = "rsvd4";
  650. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  651. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  652. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  653. };
  654. /* Bluetooth */
  655. bt_shutdown {
  656. nvidia,pins = "pu0";
  657. nvidia,function = "rsvd4";
  658. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  659. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  660. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  661. };
  662. bt_dev_wake {
  663. nvidia,pins = "pu1";
  664. nvidia,function = "rsvd1";
  665. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  666. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  667. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  668. };
  669. bt_host_wake {
  670. nvidia,pins = "pu6";
  671. nvidia,function = "rsvd4";
  672. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  673. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  674. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  675. };
  676. pu2 {
  677. nvidia,pins = "pu2";
  678. nvidia,function = "rsvd1";
  679. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  680. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  681. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  682. };
  683. pu3 {
  684. nvidia,pins = "pu3";
  685. nvidia,function = "rsvd4";
  686. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  687. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  688. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  689. };
  690. pcc1 {
  691. nvidia,pins = "pcc1";
  692. nvidia,function = "rsvd2";
  693. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  694. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  695. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  696. };
  697. pv2 {
  698. nvidia,pins = "pv2";
  699. nvidia,function = "rsvd2";
  700. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  701. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  702. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  703. };
  704. pv3 {
  705. nvidia,pins = "pv3";
  706. nvidia,function = "rsvd2";
  707. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  708. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  709. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  710. };
  711. vi_vsync_pd6 {
  712. nvidia,pins = "vi_vsync_pd6",
  713. "vi_hsync_pd7";
  714. nvidia,function = "rsvd2";
  715. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  716. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  717. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  718. nvidia,lock = <0>;
  719. nvidia,ioreset = <0>;
  720. };
  721. vi_d10_pt2 {
  722. nvidia,pins = "vi_d10_pt2",
  723. "vi_d0_pt4", "pbb0";
  724. nvidia,function = "rsvd2";
  725. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  726. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  727. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  728. };
  729. kb_row0_pr0 {
  730. nvidia,pins = "kb_row0_pr0";
  731. nvidia,function = "rsvd4";
  732. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  733. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  734. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  735. };
  736. gmi_ad0_pg0 {
  737. nvidia,pins = "gmi_ad0_pg0",
  738. "gmi_ad1_pg1",
  739. "gmi_ad2_pg2",
  740. "gmi_ad3_pg3",
  741. "gmi_ad6_pg6",
  742. "gmi_ad7_pg7",
  743. "gmi_wr_n_pi0",
  744. "gmi_oe_n_pi1",
  745. "gmi_dqs_pi2",
  746. "gmi_adv_n_pk0",
  747. "gmi_clk_pk1";
  748. nvidia,function = "nand";
  749. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  750. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  751. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  752. };
  753. gmi_ad13_ph5 {
  754. nvidia,pins = "gmi_ad13_ph5";
  755. nvidia,function = "nand";
  756. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  757. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  758. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  759. };
  760. gmi_ad10_ph2 {
  761. nvidia,pins = "gmi_ad10_ph2",
  762. "gmi_ad11_ph3",
  763. "gmi_ad14_ph6";
  764. nvidia,function = "nand";
  765. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  766. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  767. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  768. };
  769. gmi_ad12_ph4 {
  770. nvidia,pins = "gmi_ad12_ph4",
  771. "gmi_rst_n_pi4",
  772. "gmi_cs7_n_pi6";
  773. nvidia,function = "nand";
  774. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  775. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  776. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  777. };
  778. /* Vibrator control */
  779. vibrator {
  780. nvidia,pins = "gmi_ad15_ph7";
  781. nvidia,function = "nand";
  782. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  783. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  784. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  785. };
  786. /* PWM pimnmux */
  787. pwm_0 {
  788. nvidia,pins = "gmi_ad8_ph0";
  789. nvidia,function = "pwm0";
  790. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  791. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  792. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  793. };
  794. pwm_2 {
  795. nvidia,pins = "pu5";
  796. nvidia,function = "pwm2";
  797. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  798. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  799. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  800. };
  801. gmi_cs6_n_pi3 {
  802. nvidia,pins = "gmi_cs6_n_pi3";
  803. nvidia,function = "gmi";
  804. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  805. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  806. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  807. };
  808. /* Spdif pinmux */
  809. spdif_out {
  810. nvidia,pins = "spdif_out_pk5";
  811. nvidia,function = "spdif";
  812. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  813. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  814. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  815. };
  816. spdif_in {
  817. nvidia,pins = "spdif_in_pk6";
  818. nvidia,function = "spdif";
  819. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  820. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  821. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  822. };
  823. vi_d4_pl2 {
  824. nvidia,pins = "vi_d4_pl2";
  825. nvidia,function = "vi";
  826. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  827. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  828. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  829. };
  830. vi_d6_pl4 {
  831. nvidia,pins = "vi_d6_pl4";
  832. nvidia,function = "vi";
  833. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  834. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  835. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  836. nvidia,lock = <0>;
  837. nvidia,ioreset = <0>;
  838. };
  839. vi_mclk_pt1 {
  840. nvidia,pins = "vi_mclk_pt1";
  841. nvidia,function = "vi";
  842. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  843. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  844. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  845. };
  846. jtag_rtck {
  847. nvidia,pins = "jtag_rtck_pu7";
  848. nvidia,function = "rtck";
  849. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  850. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  851. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  852. };
  853. crt_hsync_pv6 {
  854. nvidia,pins = "crt_hsync_pv6",
  855. "crt_vsync_pv7";
  856. nvidia,function = "crt";
  857. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  858. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  859. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  860. };
  861. clk1_out {
  862. nvidia,pins = "clk1_out_pw4";
  863. nvidia,function = "extperiph1";
  864. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  865. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  866. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  867. };
  868. clk2_out {
  869. nvidia,pins = "clk2_out_pw5";
  870. nvidia,function = "extperiph2";
  871. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  872. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  873. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  874. };
  875. clk3_out {
  876. nvidia,pins = "clk3_out_pee0";
  877. nvidia,function = "extperiph3";
  878. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  879. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  880. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  881. };
  882. sys_clk_req {
  883. nvidia,pins = "sys_clk_req_pz5";
  884. nvidia,function = "sysclk";
  885. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  886. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  887. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  888. };
  889. pbb4 {
  890. nvidia,pins = "pbb4";
  891. nvidia,function = "vgp4";
  892. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  893. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  894. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  895. };
  896. pbb5 {
  897. nvidia,pins = "pbb5";
  898. nvidia,function = "vgp5";
  899. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  900. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  901. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  902. };
  903. pbb6 {
  904. nvidia,pins = "pbb6";
  905. nvidia,function = "vgp6";
  906. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  907. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  908. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  909. };
  910. clk2_req_pcc5 {
  911. nvidia,pins = "clk2_req_pcc5",
  912. "clk1_req_pee2";
  913. nvidia,function = "dap";
  914. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  915. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  916. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  917. };
  918. clk3_req_pee1 {
  919. nvidia,pins = "clk3_req_pee1";
  920. nvidia,function = "dev3";
  921. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  922. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  923. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  924. };
  925. owr {
  926. nvidia,pins = "owr";
  927. nvidia,function = "owr";
  928. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  929. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  930. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  931. };
  932. /* GPIO power/drive control */
  933. drive_dap1 {
  934. nvidia,pins = "drive_dap1",
  935. "drive_dap2",
  936. "drive_dbg",
  937. "drive_at5",
  938. "drive_gme",
  939. "drive_ddc",
  940. "drive_ao1",
  941. "drive_uart3";
  942. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  943. nvidia,schmitt = <TEGRA_PIN_ENABLE>;
  944. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  945. nvidia,pull-down-strength = <31>;
  946. nvidia,pull-up-strength = <31>;
  947. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  948. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  949. };
  950. drive_sdio1 {
  951. nvidia,pins = "drive_sdio1",
  952. "drive_sdio3";
  953. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  954. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  955. nvidia,pull-down-strength = <46>;
  956. nvidia,pull-up-strength = <42>;
  957. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
  958. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
  959. };
  960. };
  961. };
  962. serial@70006040 {
  963. compatible = "nvidia,tegra30-hsuart";
  964. /delete-property/ reg-shift;
  965. status = "okay";
  966. /* Broadcom GPS BCM47511 */
  967. };
  968. serial@70006200 {
  969. compatible = "nvidia,tegra30-hsuart";
  970. /delete-property/ reg-shift;
  971. status = "okay";
  972. nvidia,adjust-baud-rates = <0 9600 100>,
  973. <9600 115200 200>,
  974. <1000000 4000000 136>;
  975. bluetooth {
  976. max-speed = <4000000>;
  977. clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  978. clock-names = "txco";
  979. interrupt-parent = <&gpio>;
  980. interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
  981. interrupt-names = "host-wakeup";
  982. device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
  983. shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
  984. vbat-supply = <&vdd_3v3_com>;
  985. vddio-supply = <&vdd_1v8_vio>;
  986. };
  987. };
  988. pwm@7000a000 {
  989. status = "okay";
  990. };
  991. lcd_ddc: i2c@7000c000 {
  992. status = "okay";
  993. clock-frequency = <100000>;
  994. };
  995. i2c@7000c400 {
  996. status = "okay";
  997. clock-frequency = <400000>;
  998. };
  999. i2c@7000c500 {
  1000. status = "okay";
  1001. /* Aichi AMI306 digital compass */
  1002. magnetometer@e {
  1003. compatible = "asahi-kasei,ak8974";
  1004. reg = <0x0e>;
  1005. avdd-supply = <&vdd_3v3_sys>;
  1006. dvdd-supply = <&vdd_1v8_vio>;
  1007. };
  1008. /* Dynaimage ambient light sensor */
  1009. light-sensor@1c {
  1010. compatible = "dynaimage,al3010";
  1011. reg = <0x1c>;
  1012. interrupt-parent = <&gpio>;
  1013. interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
  1014. vdd-supply = <&vdd_3v3_sys>;
  1015. };
  1016. gyroscope@68 {
  1017. compatible = "invensense,mpu3050";
  1018. reg = <0x68>;
  1019. interrupt-parent = <&gpio>;
  1020. interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
  1021. vdd-supply = <&vdd_3v3_sys>;
  1022. vlogic-supply = <&vdd_1v8_vio>;
  1023. i2c-gate {
  1024. #address-cells = <1>;
  1025. #size-cells = <0>;
  1026. accelerometer@f {
  1027. compatible = "kionix,kxtf9";
  1028. reg = <0x0f>;
  1029. interrupt-parent = <&gpio>;
  1030. interrupts = <TEGRA_GPIO(O, 5) IRQ_TYPE_EDGE_RISING>;
  1031. vdd-supply = <&vdd_1v8_vio>;
  1032. vddio-supply = <&vdd_1v8_vio>;
  1033. };
  1034. };
  1035. };
  1036. };
  1037. hdmi_ddc: i2c@7000c700 {
  1038. status = "okay";
  1039. clock-frequency = <93750>;
  1040. };
  1041. i2c@7000d000 {
  1042. status = "okay";
  1043. clock-frequency = <400000>;
  1044. nct72: temperature-sensor@4c {
  1045. compatible = "onnn,nct1008";
  1046. reg = <0x4c>;
  1047. interrupt-parent = <&gpio>;
  1048. interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
  1049. vcc-supply = <&vdd_3v3_sys>;
  1050. #thermal-sensor-cells = <1>;
  1051. };
  1052. /* Texas Instruments TPS659110 PMIC */
  1053. pmic: pmic@2d {
  1054. compatible = "ti,tps65911";
  1055. reg = <0x2d>;
  1056. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  1057. #interrupt-cells = <2>;
  1058. interrupt-controller;
  1059. wakeup-source;
  1060. ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
  1061. ti,system-power-controller;
  1062. ti,sleep-keep-ck32k;
  1063. ti,sleep-enable;
  1064. #gpio-cells = <2>;
  1065. gpio-controller;
  1066. vcc1-supply = <&vdd_5v0_bat>;
  1067. vcc2-supply = <&vdd_5v0_bat>;
  1068. vcc3-supply = <&vdd_1v8_vio>;
  1069. vcc4-supply = <&vdd_5v0_sys>;
  1070. vcc5-supply = <&vdd_5v0_bat>;
  1071. vcc6-supply = <&vdd_3v3_sys>;
  1072. vcc7-supply = <&vdd_5v0_bat>;
  1073. vccio-supply = <&vdd_5v0_bat>;
  1074. pmic-sleep-hog {
  1075. gpio-hog;
  1076. gpios = <2 GPIO_ACTIVE_HIGH>;
  1077. output-high;
  1078. };
  1079. regulators {
  1080. /* VDD1 is not used by Transformers */
  1081. vddio_ddr: vdd2 {
  1082. regulator-name = "vddio_ddr";
  1083. regulator-min-microvolt = <1200000>;
  1084. regulator-max-microvolt = <1200000>;
  1085. regulator-always-on;
  1086. regulator-boot-on;
  1087. };
  1088. vdd_cpu: vddctrl {
  1089. regulator-name = "vdd_cpu,vdd_sys";
  1090. regulator-min-microvolt = <600000>;
  1091. regulator-max-microvolt = <1400000>;
  1092. regulator-coupled-with = <&vdd_core>;
  1093. regulator-coupled-max-spread = <300000>;
  1094. regulator-max-step-microvolt = <100000>;
  1095. regulator-always-on;
  1096. regulator-boot-on;
  1097. ti,regulator-ext-sleep-control = <1>;
  1098. nvidia,tegra-cpu-regulator;
  1099. };
  1100. vdd_1v8_vio: vio {
  1101. regulator-name = "vdd_1v8_gen";
  1102. /* FIXME: eMMC won't work, if set to 1.8 V */
  1103. regulator-min-microvolt = <1500000>;
  1104. regulator-max-microvolt = <3300000>;
  1105. regulator-always-on;
  1106. regulator-boot-on;
  1107. };
  1108. /* eMMC VDD */
  1109. vcore_emmc: ldo1 {
  1110. regulator-name = "vdd_emmc_core";
  1111. regulator-min-microvolt = <3300000>;
  1112. regulator-max-microvolt = <3300000>;
  1113. regulator-always-on;
  1114. };
  1115. /* uSD slot VDD */
  1116. vdd_usd: ldo2 {
  1117. regulator-name = "vdd_usd";
  1118. regulator-min-microvolt = <3100000>;
  1119. regulator-max-microvolt = <3100000>;
  1120. /* FIXME: Without this, voltage switching fails */
  1121. regulator-always-on;
  1122. };
  1123. /* uSD slot VDDIO */
  1124. vddio_usd: ldo3 {
  1125. regulator-name = "vddio_usd";
  1126. regulator-min-microvolt = <1800000>;
  1127. regulator-max-microvolt = <3100000>;
  1128. };
  1129. ldo4 {
  1130. regulator-name = "vdd_rtc";
  1131. regulator-min-microvolt = <1200000>;
  1132. regulator-max-microvolt = <1200000>;
  1133. regulator-always-on;
  1134. };
  1135. /* LDO5 is not used by Transformers */
  1136. ldo6 {
  1137. regulator-name = "avdd_dsi_csi,pwrdet_mipi";
  1138. regulator-min-microvolt = <1200000>;
  1139. regulator-max-microvolt = <1200000>;
  1140. };
  1141. ldo7 {
  1142. regulator-name = "vdd_pllm,x,u,a_p_c_s";
  1143. regulator-min-microvolt = <1200000>;
  1144. regulator-max-microvolt = <1200000>;
  1145. regulator-always-on;
  1146. regulator-boot-on;
  1147. ti,regulator-ext-sleep-control = <8>;
  1148. };
  1149. ldo8 {
  1150. regulator-name = "vdd_ddr_hs";
  1151. regulator-min-microvolt = <1000000>;
  1152. regulator-max-microvolt = <1000000>;
  1153. regulator-always-on;
  1154. ti,regulator-ext-sleep-control = <8>;
  1155. };
  1156. };
  1157. };
  1158. vdd_core: core-regulator@60 {
  1159. compatible = "ti,tps62361";
  1160. reg = <0x60>;
  1161. regulator-name = "tps62361-vout";
  1162. regulator-min-microvolt = <500000>;
  1163. regulator-max-microvolt = <1770000>;
  1164. regulator-coupled-with = <&vdd_cpu>;
  1165. regulator-coupled-max-spread = <300000>;
  1166. regulator-max-step-microvolt = <100000>;
  1167. regulator-boot-on;
  1168. regulator-always-on;
  1169. ti,enable-vout-discharge;
  1170. ti,vsel0-state-high;
  1171. ti,vsel1-state-high;
  1172. nvidia,tegra-core-regulator;
  1173. };
  1174. };
  1175. pmc@7000e400 {
  1176. status = "okay";
  1177. nvidia,invert-interrupt;
  1178. /* FIXME: LP1 doesn't work at the moment */
  1179. nvidia,suspend-mode = <2>;
  1180. nvidia,cpu-pwr-good-time = <2000>;
  1181. nvidia,cpu-pwr-off-time = <200>;
  1182. nvidia,core-pwr-good-time = <3845 3845>;
  1183. nvidia,core-pwr-off-time = <0>;
  1184. nvidia,core-power-req-active-high;
  1185. nvidia,sys-clock-req-active-high;
  1186. core-supply = <&vdd_core>;
  1187. /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */
  1188. i2c-thermtrip {
  1189. nvidia,i2c-controller-id = <4>;
  1190. nvidia,bus-addr = <0x2d>;
  1191. nvidia,reg-addr = <0x3f>;
  1192. nvidia,reg-data = <0x81>;
  1193. };
  1194. };
  1195. hda@70030000 {
  1196. status = "okay";
  1197. };
  1198. ahub@70080000 {
  1199. i2s@70080400 { /* i2s1 */
  1200. status = "okay";
  1201. };
  1202. /* BT SCO */
  1203. i2s@70080600 { /* i2s3 */
  1204. status = "okay";
  1205. };
  1206. };
  1207. mmc@78000000 {
  1208. status = "okay";
  1209. /* FIXME: Full 208Mhz clock rate doesn't work reliably */
  1210. max-frequency = <104000000>;
  1211. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  1212. bus-width = <4>;
  1213. vmmc-supply = <&vdd_usd>; /* ldo2 */
  1214. vqmmc-supply = <&vddio_usd>; /* ldo3 */
  1215. };
  1216. mmc@78000400 {
  1217. status = "okay";
  1218. #address-cells = <1>;
  1219. #size-cells = <0>;
  1220. assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
  1221. assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
  1222. assigned-clock-rates = <50000000>;
  1223. max-frequency = <50000000>;
  1224. keep-power-in-suspend;
  1225. bus-width = <4>;
  1226. non-removable;
  1227. mmc-pwrseq = <&brcm_wifi_pwrseq>;
  1228. vmmc-supply = <&vdd_3v3_com>;
  1229. vqmmc-supply = <&vdd_1v8_vio>;
  1230. /* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */
  1231. wifi@1 {
  1232. compatible = "brcm,bcm4329-fmac";
  1233. reg = <1>;
  1234. interrupt-parent = <&gpio>;
  1235. interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
  1236. interrupt-names = "host-wake";
  1237. };
  1238. };
  1239. mmc@78000600 {
  1240. status = "okay";
  1241. bus-width = <8>;
  1242. vmmc-supply = <&vcore_emmc>;
  1243. vqmmc-supply = <&vdd_1v8_vio>;
  1244. mmc-ddr-3_3v;
  1245. non-removable;
  1246. };
  1247. /* USB via ASUS connector */
  1248. usb@7d000000 {
  1249. compatible = "nvidia,tegra30-udc";
  1250. status = "okay";
  1251. dr_mode = "peripheral";
  1252. };
  1253. usb-phy@7d000000 {
  1254. status = "okay";
  1255. dr_mode = "peripheral";
  1256. nvidia,hssync-start-delay = <0>;
  1257. nvidia,xcvr-lsfslew = <2>;
  1258. nvidia,xcvr-lsrslew = <2>;
  1259. vbus-supply = <&vdd_5v0_sys>;
  1260. };
  1261. /* Dock's USB port */
  1262. usb@7d008000 {
  1263. status = "okay";
  1264. };
  1265. usb-phy@7d008000 {
  1266. status = "okay";
  1267. vbus-supply = <&vdd_5v0_bat>;
  1268. };
  1269. mains: ac-adapter-detect {
  1270. compatible = "gpio-charger";
  1271. charger-type = "mains";
  1272. gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
  1273. };
  1274. backlight: backlight {
  1275. compatible = "pwm-backlight";
  1276. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  1277. power-supply = <&vdd_5v0_bl>;
  1278. pwms = <&pwm 0 4000000>;
  1279. brightness-levels = <1 255>;
  1280. num-interpolated-steps = <254>;
  1281. default-brightness-level = <40>;
  1282. };
  1283. /* PMIC has a built-in 32KHz oscillator which is used by PMC */
  1284. clk32k_in: clock-32k {
  1285. compatible = "fixed-clock";
  1286. #clock-cells = <0>;
  1287. clock-frequency = <32768>;
  1288. clock-output-names = "pmic-oscillator";
  1289. };
  1290. cpus {
  1291. cpu0: cpu@0 {
  1292. cpu-supply = <&vdd_cpu>;
  1293. operating-points-v2 = <&cpu0_opp_table>;
  1294. #cooling-cells = <2>;
  1295. };
  1296. cpu1: cpu@1 {
  1297. cpu-supply = <&vdd_cpu>;
  1298. operating-points-v2 = <&cpu0_opp_table>;
  1299. #cooling-cells = <2>;
  1300. };
  1301. cpu2: cpu@2 {
  1302. cpu-supply = <&vdd_cpu>;
  1303. operating-points-v2 = <&cpu0_opp_table>;
  1304. #cooling-cells = <2>;
  1305. };
  1306. cpu3: cpu@3 {
  1307. cpu-supply = <&vdd_cpu>;
  1308. operating-points-v2 = <&cpu0_opp_table>;
  1309. #cooling-cells = <2>;
  1310. };
  1311. };
  1312. extcon-keys {
  1313. compatible = "gpio-keys";
  1314. interrupt-parent = <&gpio>;
  1315. switch-dock-hall-sensor {
  1316. label = "Lid sensor";
  1317. gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
  1318. linux,input-type = <EV_SW>;
  1319. linux,code = <SW_LID>;
  1320. debounce-interval = <500>;
  1321. wakeup-event-action = <EV_ACT_ASSERTED>;
  1322. wakeup-source;
  1323. };
  1324. switch-lineout-detect {
  1325. label = "Audio dock line-out detect";
  1326. gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>;
  1327. linux,input-type = <EV_SW>;
  1328. linux,code = <SW_LINEOUT_INSERT>;
  1329. debounce-interval = <10>;
  1330. wakeup-event-action = <EV_ACT_ASSERTED>;
  1331. wakeup-source;
  1332. };
  1333. };
  1334. firmware {
  1335. trusted-foundations {
  1336. compatible = "tlm,trusted-foundations";
  1337. tlm,version-major = <2>;
  1338. tlm,version-minor = <8>;
  1339. };
  1340. };
  1341. gpio-keys {
  1342. compatible = "gpio-keys";
  1343. interrupt-parent = <&gpio>;
  1344. key-power {
  1345. label = "Power";
  1346. gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
  1347. linux,code = <KEY_POWER>;
  1348. debounce-interval = <10>;
  1349. wakeup-event-action = <EV_ACT_ASSERTED>;
  1350. wakeup-source;
  1351. };
  1352. key-volume-up {
  1353. label = "Volume Up";
  1354. gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
  1355. linux,code = <KEY_VOLUMEUP>;
  1356. debounce-interval = <10>;
  1357. wakeup-event-action = <EV_ACT_ASSERTED>;
  1358. wakeup-source;
  1359. };
  1360. key-volume-down {
  1361. label = "Volume Down";
  1362. gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
  1363. linux,code = <KEY_VOLUMEDOWN>;
  1364. debounce-interval = <10>;
  1365. wakeup-event-action = <EV_ACT_ASSERTED>;
  1366. wakeup-source;
  1367. };
  1368. };
  1369. vdd_5v0_bat: regulator-bat {
  1370. compatible = "regulator-fixed";
  1371. regulator-name = "vdd_ac_bat";
  1372. regulator-min-microvolt = <5000000>;
  1373. regulator-max-microvolt = <5000000>;
  1374. regulator-always-on;
  1375. regulator-boot-on;
  1376. };
  1377. vdd_5v0_cp: regulator-sby {
  1378. compatible = "regulator-fixed";
  1379. regulator-name = "vdd_5v0_sby";
  1380. regulator-min-microvolt = <5000000>;
  1381. regulator-max-microvolt = <5000000>;
  1382. regulator-always-on;
  1383. regulator-boot-on;
  1384. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  1385. enable-active-high;
  1386. vin-supply = <&vdd_5v0_bat>;
  1387. };
  1388. vdd_5v0_sys: regulator-5v {
  1389. compatible = "regulator-fixed";
  1390. regulator-name = "vdd_5v0_sys";
  1391. regulator-min-microvolt = <5000000>;
  1392. regulator-max-microvolt = <5000000>;
  1393. regulator-always-on;
  1394. regulator-boot-on;
  1395. gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
  1396. enable-active-high;
  1397. vin-supply = <&vdd_5v0_bat>;
  1398. };
  1399. vdd_1v5_ddr: regulator-ddr {
  1400. compatible = "regulator-fixed";
  1401. regulator-name = "vdd_ddr";
  1402. regulator-min-microvolt = <1500000>;
  1403. regulator-max-microvolt = <1500000>;
  1404. regulator-always-on;
  1405. regulator-boot-on;
  1406. gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
  1407. enable-active-high;
  1408. vin-supply = <&vdd_5v0_bat>;
  1409. };
  1410. vdd_3v3_sys: regulator-3v {
  1411. compatible = "regulator-fixed";
  1412. regulator-name = "vdd_3v3_sys";
  1413. regulator-min-microvolt = <3300000>;
  1414. regulator-max-microvolt = <3300000>;
  1415. regulator-always-on;
  1416. regulator-boot-on;
  1417. gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
  1418. enable-active-high;
  1419. vin-supply = <&vdd_5v0_bat>;
  1420. };
  1421. vdd_pnl: regulator-panel {
  1422. compatible = "regulator-fixed";
  1423. regulator-name = "vdd_panel";
  1424. regulator-min-microvolt = <3300000>;
  1425. regulator-max-microvolt = <3300000>;
  1426. regulator-enable-ramp-delay = <20000>;
  1427. gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
  1428. enable-active-high;
  1429. vin-supply = <&vdd_3v3_sys>;
  1430. };
  1431. vdd_3v3_com: regulator-com {
  1432. compatible = "regulator-fixed";
  1433. regulator-name = "vdd_3v3_com";
  1434. regulator-min-microvolt = <3300000>;
  1435. regulator-max-microvolt = <3300000>;
  1436. regulator-always-on;
  1437. gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
  1438. enable-active-high;
  1439. vin-supply = <&vdd_3v3_sys>;
  1440. };
  1441. vdd_5v0_bl: regulator-bl {
  1442. compatible = "regulator-fixed";
  1443. regulator-name = "vdd_5v0_bl";
  1444. regulator-min-microvolt = <5000000>;
  1445. regulator-max-microvolt = <5000000>;
  1446. regulator-boot-on;
  1447. gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
  1448. enable-active-high;
  1449. vin-supply = <&vdd_5v0_bat>;
  1450. };
  1451. hdmi_5v0_sys: regulator-hdmi {
  1452. compatible = "regulator-fixed";
  1453. regulator-name = "hdmi_5v0_sys";
  1454. regulator-min-microvolt = <5000000>;
  1455. regulator-max-microvolt = <5000000>;
  1456. gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  1457. enable-active-high;
  1458. vin-supply = <&vdd_5v0_sys>;
  1459. };
  1460. sound {
  1461. nvidia,i2s-controller = <&tegra_i2s1>;
  1462. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
  1463. nvidia,hp-mute-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>;
  1464. clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
  1465. <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  1466. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1467. clock-names = "pll_a", "pll_a_out0", "mclk";
  1468. assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
  1469. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1470. assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  1471. <&tegra_car TEGRA30_CLK_EXTERN1>;
  1472. };
  1473. thermal-zones {
  1474. /*
  1475. * NCT72 has two sensors:
  1476. *
  1477. * 0: internal that monitors ambient/skin temperature
  1478. * 1: external that is connected to the CPU's diode
  1479. *
  1480. * Ideally we should use userspace thermal governor,
  1481. * but it's a much more complex solution. The "skin"
  1482. * zone exists as a simpler solution which prevents
  1483. * Transformers from getting too hot from a user's
  1484. * tactile perspective. The CPU zone is intended to
  1485. * protect silicon from damage.
  1486. */
  1487. skin-thermal {
  1488. polling-delay-passive = <1000>; /* milliseconds */
  1489. polling-delay = <5000>; /* milliseconds */
  1490. thermal-sensors = <&nct72 0>;
  1491. trips {
  1492. trip0: skin-alert {
  1493. /* throttle at 57C until temperature drops to 56.8C */
  1494. temperature = <57000>;
  1495. hysteresis = <200>;
  1496. type = "passive";
  1497. };
  1498. trip1: skin-crit {
  1499. /* shut down at 65C */
  1500. temperature = <65000>;
  1501. hysteresis = <2000>;
  1502. type = "critical";
  1503. };
  1504. };
  1505. cooling-maps {
  1506. map0 {
  1507. trip = <&trip0>;
  1508. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1509. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1510. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1511. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1512. <&actmon THERMAL_NO_LIMIT
  1513. THERMAL_NO_LIMIT>;
  1514. };
  1515. };
  1516. };
  1517. cpu-thermal {
  1518. polling-delay-passive = <1000>; /* milliseconds */
  1519. polling-delay = <5000>; /* milliseconds */
  1520. thermal-sensors = <&nct72 1>;
  1521. trips {
  1522. trip2: cpu-alert {
  1523. /* throttle at 75C until temperature drops to 74.8C */
  1524. temperature = <75000>;
  1525. hysteresis = <200>;
  1526. type = "passive";
  1527. };
  1528. trip3: cpu-crit {
  1529. /* shut down at 90C */
  1530. temperature = <90000>;
  1531. hysteresis = <2000>;
  1532. type = "critical";
  1533. };
  1534. };
  1535. cooling-maps {
  1536. map1 {
  1537. trip = <&trip2>;
  1538. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1539. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1540. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1541. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1542. <&actmon THERMAL_NO_LIMIT
  1543. THERMAL_NO_LIMIT>;
  1544. };
  1545. };
  1546. };
  1547. };
  1548. brcm_wifi_pwrseq: wifi-pwrseq {
  1549. compatible = "mmc-pwrseq-simple";
  1550. clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  1551. clock-names = "ext_clock";
  1552. reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
  1553. post-power-on-delay-ms = <300>;
  1554. power-off-delay-us = <300>;
  1555. };
  1556. };