tegra30-asus-nexus7-grouper.dtsi 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include "tegra30-asus-nexus7-grouper-common.dtsi"
  3. #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
  4. / {
  5. compatible = "asus,grouper", "nvidia,tegra30";
  6. display-panel {
  7. panel-timing {
  8. clock-frequency = <68000000>;
  9. hactive = <800>;
  10. vactive = <1280>;
  11. hfront-porch = <24>;
  12. hback-porch = <32>;
  13. hsync-len = <24>;
  14. vsync-len = <1>;
  15. vfront-porch = <5>;
  16. vback-porch = <32>;
  17. };
  18. };
  19. pinmux@70000868 {
  20. state_default: pinmux {
  21. lcd_dc1_pd2 {
  22. nvidia,pins = "lcd_dc1_pd2";
  23. nvidia,function = "displaya";
  24. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  25. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  26. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  27. };
  28. lcd_pwr2_pc6 {
  29. nvidia,pins = "lcd_pwr2_pc6";
  30. nvidia,function = "displaya";
  31. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  32. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  33. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  34. };
  35. spi2_cs2_n_pw3 {
  36. nvidia,pins = "spi2_cs2_n_pw3";
  37. nvidia,function = "spi2";
  38. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  39. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  40. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  41. };
  42. spi1_sck_px5 {
  43. nvidia,pins = "spi1_sck_px5";
  44. nvidia,function = "spi1";
  45. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  46. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  47. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  48. };
  49. pu5 {
  50. nvidia,pins = "pu5";
  51. nvidia,function = "pwm2";
  52. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  53. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  54. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  55. };
  56. spi1_miso_px7 {
  57. nvidia,pins = "spi1_miso_px7";
  58. nvidia,function = "spi1";
  59. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  60. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  61. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  62. };
  63. spi2_mosi_px0 {
  64. nvidia,pins = "spi2_mosi_px0";
  65. nvidia,function = "spi2";
  66. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  67. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  68. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  69. };
  70. kb_row7_pr7 {
  71. nvidia,pins = "kb_row7_pr7";
  72. nvidia,function = "kbc";
  73. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  74. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  75. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  76. };
  77. pu3 {
  78. nvidia,pins = "pu3";
  79. nvidia,function = "rsvd4";
  80. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  81. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  82. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  83. };
  84. pu4 {
  85. nvidia,pins = "pu4";
  86. nvidia,function = "pwm1";
  87. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  88. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  89. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  90. };
  91. kb_row15_ps7 {
  92. nvidia,pins = "kb_row15_ps7";
  93. nvidia,function = "kbc";
  94. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  95. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  96. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  97. };
  98. kb_row3_pr3 {
  99. nvidia,pins = "kb_row3_pr3";
  100. nvidia,function = "kbc";
  101. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  102. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  103. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  104. };
  105. kb_row13_ps5 {
  106. nvidia,pins = "kb_row13_ps5";
  107. nvidia,function = "kbc";
  108. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  109. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  110. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  111. };
  112. gmi_wp_n_pc7 {
  113. nvidia,pins = "gmi_wp_n_pc7",
  114. "gmi_wait_pi7",
  115. "gmi_cs4_n_pk2",
  116. "gmi_cs3_n_pk4";
  117. nvidia,function = "rsvd1";
  118. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  119. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  120. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  121. };
  122. gmi_cs6_n_pi3 {
  123. nvidia,pins = "gmi_cs6_n_pi3";
  124. nvidia,function = "gmi";
  125. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  126. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  127. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  128. };
  129. };
  130. };
  131. i2c@7000c500 {
  132. nfc@28 {
  133. compatible = "nxp,pn544-i2c";
  134. reg = <0x28>;
  135. interrupt-parent = <&gpio>;
  136. interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_EDGE_RISING>;
  137. enable-gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
  138. firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
  139. };
  140. };
  141. };