tegra30-asus-nexus7-grouper-common.dtsi 34 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320
  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/input/gpio-keys.h>
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/power/summit,smb347-charger.h>
  5. #include <dt-bindings/thermal/thermal.h>
  6. #include "tegra30.dtsi"
  7. #include "tegra30-cpu-opp.dtsi"
  8. #include "tegra30-cpu-opp-microvolt.dtsi"
  9. #include "tegra30-asus-lvds-display.dtsi"
  10. / {
  11. aliases {
  12. mmc0 = &sdmmc4; /* eMMC */
  13. mmc1 = &sdmmc3; /* WiFi */
  14. rtc0 = &pmic;
  15. rtc1 = "/rtc@7000e000";
  16. serial1 = &uartc; /* Bluetooth */
  17. serial2 = &uartb; /* GPS */
  18. };
  19. /*
  20. * The decompressor and also some bootloaders rely on a
  21. * pre-existing /chosen node to be available to insert the
  22. * command line and merge other ATAGS info.
  23. */
  24. chosen {};
  25. memory@80000000 {
  26. reg = <0x80000000 0x40000000>;
  27. };
  28. reserved-memory {
  29. #address-cells = <1>;
  30. #size-cells = <1>;
  31. ranges;
  32. linux,cma@80000000 {
  33. compatible = "shared-dma-pool";
  34. alloc-ranges = <0x80000000 0x30000000>;
  35. size = <0x10000000>; /* 256MiB */
  36. linux,cma-default;
  37. reusable;
  38. };
  39. ramoops@bfdf0000 {
  40. compatible = "ramoops";
  41. reg = <0xbfdf0000 0x10000>; /* 64kB */
  42. console-size = <0x8000>; /* 32kB */
  43. record-size = <0x400>; /* 1kB */
  44. ecc-size = <16>;
  45. };
  46. trustzone@bfe00000 {
  47. reg = <0xbfe00000 0x200000>;
  48. no-map;
  49. };
  50. };
  51. gpio@6000d000 {
  52. init-mode-hog {
  53. gpio-hog;
  54. gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>,
  55. <TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>,
  56. <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
  57. output-low;
  58. };
  59. init-low-power-mode-hog {
  60. gpio-hog;
  61. gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  62. input;
  63. };
  64. };
  65. pinmux@70000868 {
  66. pinctrl-names = "default";
  67. pinctrl-0 = <&state_default>;
  68. state_default: pinmux {
  69. clk_32k_out_pa0 {
  70. nvidia,pins = "clk_32k_out_pa0";
  71. nvidia,function = "blink";
  72. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  73. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  74. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  75. };
  76. uart3_cts_n_pa1 {
  77. nvidia,pins = "uart3_cts_n_pa1",
  78. "uart3_rxd_pw7";
  79. nvidia,function = "uartc";
  80. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  81. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  82. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  83. };
  84. dap2_fs_pa2 {
  85. nvidia,pins = "dap2_fs_pa2",
  86. "dap2_sclk_pa3",
  87. "dap2_din_pa4",
  88. "dap2_dout_pa5";
  89. nvidia,function = "i2s1";
  90. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  91. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  92. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  93. };
  94. sdmmc3_clk_pa6 {
  95. nvidia,pins = "sdmmc3_clk_pa6";
  96. nvidia,function = "sdmmc3";
  97. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  98. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  99. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  100. };
  101. sdmmc3_cmd_pa7 {
  102. nvidia,pins = "sdmmc3_cmd_pa7",
  103. "sdmmc3_dat3_pb4",
  104. "sdmmc3_dat2_pb5",
  105. "sdmmc3_dat1_pb6",
  106. "sdmmc3_dat0_pb7",
  107. "sdmmc3_dat4_pd1",
  108. "sdmmc3_dat6_pd3",
  109. "sdmmc3_dat7_pd4";
  110. nvidia,function = "sdmmc3";
  111. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  112. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  113. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  114. };
  115. gmi_a17_pb0 {
  116. nvidia,pins = "gmi_a17_pb0",
  117. "gmi_a18_pb1";
  118. nvidia,function = "uartd";
  119. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  120. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  121. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  122. };
  123. lcd_pwr0_pb2 {
  124. nvidia,pins = "lcd_pwr0_pb2",
  125. "lcd_pwr1_pc1",
  126. "lcd_m1_pw1";
  127. nvidia,function = "displaya";
  128. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  129. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  130. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  131. };
  132. lcd_pclk_pb3 {
  133. nvidia,pins = "lcd_pclk_pb3",
  134. "lcd_d0_pe0",
  135. "lcd_d1_pe1",
  136. "lcd_d2_pe2",
  137. "lcd_d3_pe3",
  138. "lcd_d4_pe4",
  139. "lcd_d5_pe5",
  140. "lcd_d6_pe6",
  141. "lcd_d7_pe7",
  142. "lcd_d8_pf0",
  143. "lcd_d9_pf1",
  144. "lcd_d10_pf2",
  145. "lcd_d11_pf3",
  146. "lcd_d12_pf4",
  147. "lcd_d13_pf5",
  148. "lcd_d14_pf6",
  149. "lcd_d15_pf7",
  150. "lcd_de_pj1",
  151. "lcd_hsync_pj3",
  152. "lcd_vsync_pj4",
  153. "lcd_d16_pm0",
  154. "lcd_d17_pm1",
  155. "lcd_d18_pm2",
  156. "lcd_d19_pm3",
  157. "lcd_d20_pm4",
  158. "lcd_d21_pm5",
  159. "lcd_d22_pm6",
  160. "lcd_d23_pm7",
  161. "lcd_cs0_n_pn4",
  162. "lcd_sdout_pn5",
  163. "lcd_dc0_pn6",
  164. "lcd_cs1_n_pw0",
  165. "lcd_sdin_pz2",
  166. "lcd_sck_pz4";
  167. nvidia,function = "displaya";
  168. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  169. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  170. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  171. };
  172. uart3_rts_n_pc0 {
  173. nvidia,pins = "uart3_rts_n_pc0",
  174. "uart3_txd_pw6";
  175. nvidia,function = "uartc";
  176. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  177. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  178. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  179. };
  180. uart2_txd_pc2 {
  181. nvidia,pins = "uart2_txd_pc2",
  182. "uart2_rts_n_pj6";
  183. nvidia,function = "uartb";
  184. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  185. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  186. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  187. };
  188. uart2_rxd_pc3 {
  189. nvidia,pins = "uart2_rxd_pc3",
  190. "uart2_cts_n_pj5";
  191. nvidia,function = "uartb";
  192. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  193. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  194. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  195. };
  196. gen1_i2c_scl_pc4 {
  197. nvidia,pins = "gen1_i2c_scl_pc4",
  198. "gen1_i2c_sda_pc5";
  199. nvidia,function = "i2c1";
  200. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  201. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  202. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  203. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  204. };
  205. gmi_wp_n_pc7 {
  206. nvidia,pins = "gmi_wp_n_pc7",
  207. "gmi_wait_pi7",
  208. "gmi_cs4_n_pk2",
  209. "gmi_cs3_n_pk4";
  210. nvidia,function = "rsvd1";
  211. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  212. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  213. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  214. };
  215. gmi_ad12_ph4 {
  216. nvidia,pins = "gmi_ad12_ph4",
  217. "gmi_cs0_n_pj0",
  218. "gmi_cs1_n_pj2",
  219. "gmi_cs2_n_pk3";
  220. nvidia,function = "rsvd1";
  221. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  222. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  223. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  224. };
  225. sdmmc3_dat5_pd0 {
  226. nvidia,pins = "sdmmc3_dat5_pd0";
  227. nvidia,function = "sdmmc3";
  228. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  229. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  230. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  231. };
  232. gmi_ad0_pg0 {
  233. nvidia,pins = "gmi_ad0_pg0",
  234. "gmi_ad1_pg1",
  235. "gmi_ad14_ph6",
  236. "pu1";
  237. nvidia,function = "rsvd1";
  238. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  239. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  240. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  241. };
  242. gmi_ad2_pg2 {
  243. nvidia,pins = "gmi_ad2_pg2",
  244. "gmi_ad3_pg3",
  245. "gmi_ad6_pg6",
  246. "gmi_ad7_pg7";
  247. nvidia,function = "rsvd1";
  248. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  249. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  250. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  251. };
  252. gmi_ad4_pg4 {
  253. nvidia,pins = "gmi_ad4_pg4",
  254. "gmi_ad5_pg5";
  255. nvidia,function = "nand";
  256. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  257. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  258. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  259. };
  260. gmi_ad8_ph0 {
  261. nvidia,pins = "gmi_ad8_ph0";
  262. nvidia,function = "pwm0";
  263. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  264. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  265. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  266. };
  267. gmi_ad9_ph1 {
  268. nvidia,pins = "gmi_ad9_ph1";
  269. nvidia,function = "rsvd4";
  270. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  271. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  272. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  273. };
  274. gmi_ad10_ph2 {
  275. nvidia,pins = "gmi_ad10_ph2";
  276. nvidia,function = "pwm2";
  277. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  278. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  279. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  280. };
  281. gmi_ad11_ph3 {
  282. nvidia,pins = "gmi_ad11_ph3";
  283. nvidia,function = "pwm3";
  284. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  285. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  286. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  287. };
  288. gmi_ad13_ph5 {
  289. nvidia,pins = "gmi_ad13_ph5",
  290. "gmi_wr_n_pi0",
  291. "gmi_oe_n_pi1",
  292. "gmi_adv_n_pk0";
  293. nvidia,function = "rsvd1";
  294. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  295. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  296. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  297. };
  298. gmi_ad15_ph7 {
  299. nvidia,pins = "gmi_ad15_ph7";
  300. nvidia,function = "rsvd1";
  301. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  302. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  303. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  304. };
  305. gmi_dqs_pi2 {
  306. nvidia,pins = "gmi_dqs_pi2",
  307. "pu2",
  308. "pv1";
  309. nvidia,function = "rsvd1";
  310. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  311. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  312. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  313. };
  314. gmi_rst_n_pi4 {
  315. nvidia,pins = "gmi_rst_n_pi4";
  316. nvidia,function = "nand";
  317. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  318. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  319. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  320. };
  321. gmi_iordy_pi5 {
  322. nvidia,pins = "gmi_iordy_pi5";
  323. nvidia,function = "rsvd1";
  324. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  325. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  326. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  327. };
  328. gmi_cs7_n_pi6 {
  329. nvidia,pins = "gmi_cs7_n_pi6",
  330. "gmi_clk_pk1";
  331. nvidia,function = "nand";
  332. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  333. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  334. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  335. };
  336. gmi_a16_pj7 {
  337. nvidia,pins = "gmi_a16_pj7",
  338. "gmi_a19_pk7";
  339. nvidia,function = "uartd";
  340. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  341. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  342. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  343. };
  344. spdif_out_pk5 {
  345. nvidia,pins = "spdif_out_pk5";
  346. nvidia,function = "spdif";
  347. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  348. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  349. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  350. };
  351. spdif_in_pk6 {
  352. nvidia,pins = "spdif_in_pk6";
  353. nvidia,function = "spdif";
  354. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  355. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  356. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  357. };
  358. dap1_fs_pn0 {
  359. nvidia,pins = "dap1_fs_pn0",
  360. "dap1_din_pn1",
  361. "dap1_dout_pn2",
  362. "dap1_sclk_pn3";
  363. nvidia,function = "i2s0";
  364. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  365. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  366. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  367. };
  368. hdmi_int_pn7 {
  369. nvidia,pins = "hdmi_int_pn7";
  370. nvidia,function = "hdmi";
  371. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  372. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  373. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  374. };
  375. ulpi_data7_po0 {
  376. nvidia,pins = "ulpi_data7_po0";
  377. nvidia,function = "uarta";
  378. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  379. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  380. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  381. };
  382. ulpi_data3_po4 {
  383. nvidia,pins = "ulpi_data3_po4";
  384. nvidia,function = "ulpi";
  385. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  386. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  387. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  388. };
  389. dap3_fs_pp0 {
  390. nvidia,pins = "dap3_fs_pp0";
  391. nvidia,function = "i2s2";
  392. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  393. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  394. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  395. };
  396. dap4_fs_pp4 {
  397. nvidia,pins = "dap4_fs_pp4",
  398. "dap4_din_pp5",
  399. "dap4_dout_pp6",
  400. "dap4_sclk_pp7";
  401. nvidia,function = "i2s3";
  402. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  403. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  404. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  405. };
  406. kb_col0_pq0 {
  407. nvidia,pins = "kb_col0_pq0",
  408. "kb_col1_pq1",
  409. "kb_row1_pr1";
  410. nvidia,function = "kbc";
  411. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  412. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  413. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  414. };
  415. kb_col2_pq2 {
  416. nvidia,pins = "kb_col2_pq2",
  417. "kb_col3_pq3";
  418. nvidia,function = "rsvd4";
  419. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  420. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  421. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  422. };
  423. kb_col4_pq4 {
  424. nvidia,pins = "kb_col4_pq4",
  425. "kb_col5_pq5",
  426. "kb_col7_pq7",
  427. "kb_row2_pr2",
  428. "kb_row4_pr4",
  429. "kb_row5_pr5",
  430. "kb_row14_ps6";
  431. nvidia,function = "kbc";
  432. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  433. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  434. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  435. };
  436. kb_row0_pr0 {
  437. nvidia,pins = "kb_row0_pr0";
  438. nvidia,function = "rsvd4";
  439. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  440. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  441. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  442. };
  443. kb_row6_pr6 {
  444. nvidia,pins = "kb_row6_pr6",
  445. "kb_row8_ps0",
  446. "kb_row9_ps1",
  447. "kb_row10_ps2";
  448. nvidia,function = "kbc";
  449. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  450. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  451. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  452. };
  453. kb_row11_ps3 {
  454. nvidia,pins = "kb_row11_ps3",
  455. "kb_row12_ps4";
  456. nvidia,function = "kbc";
  457. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  458. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  459. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  460. };
  461. gen2_i2c_scl_pt5 {
  462. nvidia,pins = "gen2_i2c_scl_pt5",
  463. "gen2_i2c_sda_pt6";
  464. nvidia,function = "i2c2";
  465. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  466. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  467. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  468. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  469. };
  470. sdmmc4_cmd_pt7 {
  471. nvidia,pins = "sdmmc4_cmd_pt7",
  472. "sdmmc4_dat0_paa0",
  473. "sdmmc4_dat1_paa1",
  474. "sdmmc4_dat2_paa2",
  475. "sdmmc4_dat3_paa3",
  476. "sdmmc4_dat4_paa4",
  477. "sdmmc4_dat5_paa5",
  478. "sdmmc4_dat6_paa6",
  479. "sdmmc4_dat7_paa7";
  480. nvidia,function = "sdmmc4";
  481. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  482. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  483. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  484. };
  485. pu0 {
  486. nvidia,pins = "pu0",
  487. "pu6";
  488. nvidia,function = "rsvd4";
  489. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  490. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  491. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  492. };
  493. jtag_rtck_pu7 {
  494. nvidia,pins = "jtag_rtck_pu7";
  495. nvidia,function = "rtck";
  496. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  497. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  498. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  499. };
  500. pv0 {
  501. nvidia,pins = "pv0";
  502. nvidia,function = "rsvd1";
  503. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  504. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  505. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  506. };
  507. ddc_scl_pv4 {
  508. nvidia,pins = "ddc_scl_pv4",
  509. "ddc_sda_pv5";
  510. nvidia,function = "i2c4";
  511. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  512. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  513. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  514. };
  515. crt_hsync_pv6 {
  516. nvidia,pins = "crt_hsync_pv6",
  517. "crt_vsync_pv7";
  518. nvidia,function = "crt";
  519. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  520. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  521. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  522. };
  523. spi2_cs1_n_pw2 {
  524. nvidia,pins = "spi2_cs1_n_pw2",
  525. "spi2_miso_px1",
  526. "spi2_sck_px2";
  527. nvidia,function = "spi2";
  528. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  529. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  530. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  531. };
  532. clk1_out_pw4 {
  533. nvidia,pins = "clk1_out_pw4";
  534. nvidia,function = "extperiph1";
  535. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  536. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  537. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  538. };
  539. clk2_out_pw5 {
  540. nvidia,pins = "clk2_out_pw5";
  541. nvidia,function = "extperiph2";
  542. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  543. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  544. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  545. };
  546. spi2_cs0_n_px3 {
  547. nvidia,pins = "spi2_cs0_n_px3";
  548. nvidia,function = "spi6";
  549. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  550. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  551. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  552. };
  553. spi1_mosi_px4 {
  554. nvidia,pins = "spi1_mosi_px4",
  555. "spi1_cs0_n_px6";
  556. nvidia,function = "spi1";
  557. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  558. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  559. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  560. };
  561. ulpi_clk_py0 {
  562. nvidia,pins = "ulpi_clk_py0",
  563. "ulpi_dir_py1";
  564. nvidia,function = "ulpi";
  565. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  566. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  567. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  568. };
  569. sdmmc1_dat3_py4 {
  570. nvidia,pins = "sdmmc1_dat3_py4",
  571. "sdmmc1_dat2_py5",
  572. "sdmmc1_dat1_py6",
  573. "sdmmc1_dat0_py7",
  574. "sdmmc1_cmd_pz1";
  575. nvidia,function = "sdmmc1";
  576. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  577. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  578. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  579. };
  580. sdmmc1_clk_pz0 {
  581. nvidia,pins = "sdmmc1_clk_pz0";
  582. nvidia,function = "sdmmc1";
  583. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  584. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  585. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  586. };
  587. lcd_wr_n_pz3 {
  588. nvidia,pins = "lcd_wr_n_pz3";
  589. nvidia,function = "displaya";
  590. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  591. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  592. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  593. };
  594. sys_clk_req_pz5 {
  595. nvidia,pins = "sys_clk_req_pz5";
  596. nvidia,function = "sysclk";
  597. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  598. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  599. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  600. };
  601. pwr_i2c_scl_pz6 {
  602. nvidia,pins = "pwr_i2c_scl_pz6",
  603. "pwr_i2c_sda_pz7";
  604. nvidia,function = "i2cpwr";
  605. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  606. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  607. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  608. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  609. };
  610. pbb0 {
  611. nvidia,pins = "pbb0",
  612. "pcc1";
  613. nvidia,function = "rsvd2";
  614. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  615. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  616. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  617. };
  618. cam_i2c_scl_pbb1 {
  619. nvidia,pins = "cam_i2c_scl_pbb1",
  620. "cam_i2c_sda_pbb2";
  621. nvidia,function = "i2c3";
  622. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  623. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  624. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  625. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  626. };
  627. pbb3 {
  628. nvidia,pins = "pbb3";
  629. nvidia,function = "vgp3";
  630. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  631. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  632. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  633. };
  634. pbb4 {
  635. nvidia,pins = "pbb4";
  636. nvidia,function = "vgp4";
  637. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  638. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  639. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  640. };
  641. pbb5 {
  642. nvidia,pins = "pbb5";
  643. nvidia,function = "vgp5";
  644. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  645. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  646. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  647. };
  648. pbb6 {
  649. nvidia,pins = "pbb6";
  650. nvidia,function = "vgp6";
  651. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  652. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  653. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  654. };
  655. pbb7 {
  656. nvidia,pins = "pbb7",
  657. "pcc2";
  658. nvidia,function = "i2s4";
  659. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  660. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  661. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  662. };
  663. cam_mclk_pcc0 {
  664. nvidia,pins = "cam_mclk_pcc0";
  665. nvidia,function = "vi_alt3";
  666. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  667. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  668. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  669. };
  670. sdmmc4_rst_n_pcc3 {
  671. nvidia,pins = "sdmmc4_rst_n_pcc3";
  672. nvidia,function = "rsvd2";
  673. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  674. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  675. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  676. };
  677. sdmmc4_clk_pcc4 {
  678. nvidia,pins = "sdmmc4_clk_pcc4";
  679. nvidia,function = "sdmmc4";
  680. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  681. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  682. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  683. };
  684. clk2_req_pcc5 {
  685. nvidia,pins = "clk2_req_pcc5";
  686. nvidia,function = "dap";
  687. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  688. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  689. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  690. };
  691. pex_l2_rst_n_pcc6 {
  692. nvidia,pins = "pex_l2_rst_n_pcc6",
  693. "pex_l2_clkreq_n_pcc7";
  694. nvidia,function = "pcie";
  695. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  696. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  697. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  698. };
  699. pex_wake_n_pdd3 {
  700. nvidia,pins = "pex_wake_n_pdd3",
  701. "pex_l2_prsnt_n_pdd7";
  702. nvidia,function = "pcie";
  703. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  704. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  705. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  706. };
  707. clk3_out_pee0 {
  708. nvidia,pins = "clk3_out_pee0";
  709. nvidia,function = "extperiph3";
  710. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  711. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  712. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  713. };
  714. clk1_req_pee2 {
  715. nvidia,pins = "clk1_req_pee2";
  716. nvidia,function = "dap";
  717. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  718. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  719. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  720. };
  721. hdmi_cec_pee3 {
  722. nvidia,pins = "hdmi_cec_pee3";
  723. nvidia,function = "cec";
  724. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  725. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  726. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  727. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  728. };
  729. owr {
  730. nvidia,pins = "owr";
  731. nvidia,function = "owr";
  732. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  733. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  734. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  735. };
  736. drive_dap1 {
  737. nvidia,pins = "drive_dap1",
  738. "drive_dap2",
  739. "drive_dbg",
  740. "drive_at5",
  741. "drive_gme",
  742. "drive_ddc",
  743. "drive_ao1",
  744. "drive_uart3";
  745. nvidia,high-speed-mode = <0>;
  746. nvidia,schmitt = <TEGRA_PIN_ENABLE>;
  747. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  748. nvidia,pull-down-strength = <31>;
  749. nvidia,pull-up-strength = <31>;
  750. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  751. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  752. };
  753. drive_sdio1 {
  754. nvidia,pins = "drive_sdio1",
  755. "drive_sdio3";
  756. nvidia,high-speed-mode = <0>;
  757. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  758. nvidia,pull-down-strength = <46>;
  759. nvidia,pull-up-strength = <42>;
  760. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
  761. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
  762. };
  763. drive_gma {
  764. nvidia,pins = "drive_gma",
  765. "drive_gmb",
  766. "drive_gmc",
  767. "drive_gmd";
  768. nvidia,pull-down-strength = <9>;
  769. nvidia,pull-up-strength = <9>;
  770. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  771. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  772. };
  773. };
  774. };
  775. uartb: serial@70006040 {
  776. compatible = "nvidia,tegra30-hsuart";
  777. /delete-property/ reg-shift;
  778. /* GPS BCM4751 */
  779. };
  780. uartc: serial@70006200 {
  781. compatible = "nvidia,tegra30-hsuart";
  782. /delete-property/ reg-shift;
  783. status = "okay";
  784. nvidia,adjust-baud-rates = <0 9600 100>,
  785. <9600 115200 200>,
  786. <1000000 4000000 136>;
  787. /* Azurewave AW-NH665 BCM4330B1 */
  788. bluetooth {
  789. compatible = "brcm,bcm4330-bt";
  790. interrupt-parent = <&gpio>;
  791. interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
  792. interrupt-names = "host-wakeup";
  793. max-speed = <4000000>;
  794. clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  795. clock-names = "txco";
  796. vbat-supply = <&vdd_3v3_sys>;
  797. vddio-supply = <&vdd_1v8>;
  798. device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
  799. shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
  800. };
  801. };
  802. pwm: pwm@7000a000 {
  803. status = "okay";
  804. };
  805. i2c@7000c400 {
  806. clock-frequency = <400000>;
  807. status = "okay";
  808. touchscreen@10 {
  809. compatible = "elan,ektf3624";
  810. reg = <0x10>;
  811. interrupt-parent = <&gpio>;
  812. interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_LOW>;
  813. reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
  814. vcc33-supply = <&vcc_3v3_ts>;
  815. vccio-supply = <&vcc_3v3_ts>;
  816. touchscreen-size-x = <2112>;
  817. touchscreen-size-y = <1280>;
  818. touchscreen-swapped-x-y;
  819. touchscreen-inverted-x;
  820. };
  821. };
  822. i2c@7000c500 {
  823. clock-frequency = <100000>;
  824. status = "okay";
  825. compass@e {
  826. compatible = "asahi-kasei,ak8974";
  827. reg = <0x0e>;
  828. interrupt-parent = <&gpio>;
  829. interrupts = <TEGRA_GPIO(W, 0) IRQ_TYPE_EDGE_RISING>;
  830. avdd-supply = <&vdd_3v3_sys>;
  831. dvdd-supply = <&vdd_1v8>;
  832. mount-matrix = "0", "-1", "0",
  833. "-1", "0", "0",
  834. "0", "0", "-1";
  835. };
  836. light-sensor@1c {
  837. compatible = "dynaimage,al3010";
  838. reg = <0x1c>;
  839. interrupt-parent = <&gpio>;
  840. interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
  841. vdd-supply = <&vdd_3v3_sys>;
  842. };
  843. accelerometer@68 {
  844. compatible = "invensense,mpu6050";
  845. reg = <0x68>;
  846. interrupt-parent = <&gpio>;
  847. interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
  848. vdd-supply = <&vdd_3v3_sys>;
  849. vddio-supply = <&vdd_1v8>;
  850. mount-matrix = "0", "-1", "0",
  851. "-1", "0", "0",
  852. "0", "0", "-1";
  853. };
  854. };
  855. i2c@7000d000 {
  856. clock-frequency = <100000>;
  857. status = "okay";
  858. rt5640: audio-codec@1c {
  859. compatible = "realtek,rt5640";
  860. reg = <0x1c>;
  861. realtek,dmic1-data-pin = <1>;
  862. };
  863. nct72: temperature-sensor@4c {
  864. compatible = "onnn,nct1008";
  865. reg = <0x4c>;
  866. vcc-supply = <&vdd_3v3_sys>;
  867. interrupt-parent = <&gpio>;
  868. interrupts = <TEGRA_GPIO(S, 3) IRQ_TYPE_EDGE_FALLING>;
  869. #thermal-sensor-cells = <1>;
  870. };
  871. fuel-gauge@55 {
  872. compatible = "ti,bq27541";
  873. reg = <0x55>;
  874. power-supplies = <&power_supply>;
  875. };
  876. power_supply: charger@6a {
  877. compatible = "summit,smb347";
  878. reg = <0x6a>;
  879. interrupt-parent = <&gpio>;
  880. interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>;
  881. summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>;
  882. summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>;
  883. summit,enable-usb-charging;
  884. monitored-battery = <&battery_cell>;
  885. usb_vbus: usb-vbus {
  886. regulator-name = "usb_vbus";
  887. regulator-min-microvolt = <5000000>;
  888. regulator-max-microvolt = <5000000>;
  889. regulator-min-microamp = <750000>;
  890. regulator-max-microamp = <750000>;
  891. /*
  892. * SMB347 INOK input pin is connected to PMIC's
  893. * ACOK output, which is fixed to ACTIVE_LOW as
  894. * long as battery voltage is in a good range.
  895. *
  896. * Active INOK disables SMB347 output, so polarity
  897. * needs to be toggled when we want to get the
  898. * output.
  899. */
  900. summit,needs-inok-toggle;
  901. };
  902. };
  903. };
  904. pmc@7000e400 {
  905. status = "okay";
  906. nvidia,invert-interrupt;
  907. nvidia,suspend-mode = <1>;
  908. nvidia,cpu-pwr-good-time = <2000>;
  909. nvidia,cpu-pwr-off-time = <200>;
  910. nvidia,core-pwr-good-time = <3845 3845>;
  911. nvidia,core-pwr-off-time = <0>;
  912. nvidia,core-power-req-active-high;
  913. nvidia,sys-clock-req-active-high;
  914. core-supply = <&vdd_core>;
  915. };
  916. ahub@70080000 {
  917. i2s@70080400 {
  918. status = "okay";
  919. };
  920. };
  921. brcm_wifi_pwrseq: wifi-pwrseq {
  922. compatible = "mmc-pwrseq-simple";
  923. clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
  924. clock-names = "ext_clock";
  925. reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
  926. post-power-on-delay-ms = <300>;
  927. power-off-delay-us = <300>;
  928. };
  929. sdmmc3: mmc@78000400 {
  930. status = "okay";
  931. #address-cells = <1>;
  932. #size-cells = <0>;
  933. assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
  934. assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
  935. assigned-clock-rates = <50000000>;
  936. max-frequency = <50000000>;
  937. keep-power-in-suspend;
  938. bus-width = <4>;
  939. non-removable;
  940. mmc-pwrseq = <&brcm_wifi_pwrseq>;
  941. vmmc-supply = <&vdd_3v3_sys>;
  942. vqmmc-supply = <&vdd_1v8>;
  943. /* Azurewave AW-NH665 BCM4330 */
  944. wifi@1 {
  945. reg = <1>;
  946. compatible = "brcm,bcm4329-fmac";
  947. interrupt-parent = <&gpio>;
  948. interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
  949. interrupt-names = "host-wake";
  950. };
  951. };
  952. sdmmc4: mmc@78000600 {
  953. status = "okay";
  954. bus-width = <8>;
  955. vmmc-supply = <&vcore_emmc>;
  956. vqmmc-supply = <&vdd_1v8>;
  957. non-removable;
  958. };
  959. usb@7d000000 {
  960. compatible = "nvidia,tegra30-udc";
  961. status = "okay";
  962. dr_mode = "otg";
  963. vbus-supply = <&usb_vbus>;
  964. };
  965. usb-phy@7d000000 {
  966. status = "okay";
  967. dr_mode = "otg";
  968. nvidia,hssync-start-delay = <0>;
  969. nvidia,xcvr-lsfslew = <2>;
  970. nvidia,xcvr-lsrslew = <2>;
  971. };
  972. backlight: backlight {
  973. compatible = "pwm-backlight";
  974. power-supply = <&vdd_5v0_sys>;
  975. pwms = <&pwm 0 50000>;
  976. brightness-levels = <1 255>;
  977. num-interpolated-steps = <254>;
  978. default-brightness-level = <15>;
  979. };
  980. battery_cell: battery-cell {
  981. compatible = "simple-battery";
  982. constant-charge-current-max-microamp = <1800000>;
  983. operating-range-celsius = <0 45>;
  984. };
  985. /* PMIC has a built-in 32KHz oscillator which is used by PMC */
  986. clk32k_in: clock-32k {
  987. compatible = "fixed-clock";
  988. #clock-cells = <0>;
  989. clock-frequency = <32768>;
  990. clock-output-names = "pmic-oscillator";
  991. };
  992. cpus {
  993. cpu0: cpu@0 {
  994. cpu-supply = <&vdd_cpu>;
  995. operating-points-v2 = <&cpu0_opp_table>;
  996. #cooling-cells = <2>;
  997. };
  998. cpu1: cpu@1 {
  999. cpu-supply = <&vdd_cpu>;
  1000. operating-points-v2 = <&cpu0_opp_table>;
  1001. #cooling-cells = <2>;
  1002. };
  1003. cpu2: cpu@2 {
  1004. cpu-supply = <&vdd_cpu>;
  1005. operating-points-v2 = <&cpu0_opp_table>;
  1006. #cooling-cells = <2>;
  1007. };
  1008. cpu3: cpu@3 {
  1009. cpu-supply = <&vdd_cpu>;
  1010. operating-points-v2 = <&cpu0_opp_table>;
  1011. #cooling-cells = <2>;
  1012. };
  1013. };
  1014. display-panel {
  1015. /*
  1016. * Nexus 7 supports two compatible panel models:
  1017. *
  1018. * 1. hydis,hv070wx2-1e0
  1019. * 2. chunghwa,claa070wp03xg
  1020. *
  1021. * We want to use timing which is optimized for Nexus 7,
  1022. * hence we need to customize the timing.
  1023. */
  1024. compatible = "panel-lvds";
  1025. width-mm = <94>;
  1026. height-mm = <150>;
  1027. rotation = <180>;
  1028. data-mapping = "jeida-24";
  1029. /* DDC unconnected on Nexus 7 */
  1030. /delete-property/ ddc-i2c-bus;
  1031. };
  1032. firmware {
  1033. trusted-foundations {
  1034. compatible = "tlm,trusted-foundations";
  1035. tlm,version-major = <0x0>;
  1036. tlm,version-minor = <0x0>;
  1037. };
  1038. };
  1039. gpio-keys {
  1040. compatible = "gpio-keys";
  1041. switch-hall-sensor {
  1042. label = "Lid";
  1043. gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
  1044. linux,input-type = <EV_SW>;
  1045. linux,code = <SW_LID>;
  1046. debounce-interval = <500>;
  1047. wakeup-event-action = <EV_ACT_DEASSERTED>;
  1048. wakeup-source;
  1049. };
  1050. key-power {
  1051. label = "Power";
  1052. gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
  1053. linux,code = <KEY_POWER>;
  1054. debounce-interval = <10>;
  1055. wakeup-event-action = <EV_ACT_ASSERTED>;
  1056. wakeup-source;
  1057. };
  1058. key-volume-up {
  1059. label = "Volume Up";
  1060. gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
  1061. linux,code = <KEY_VOLUMEUP>;
  1062. debounce-interval = <10>;
  1063. wakeup-event-action = <EV_ACT_ASSERTED>;
  1064. wakeup-source;
  1065. };
  1066. key-volume-down {
  1067. label = "Volume Down";
  1068. gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
  1069. linux,code = <KEY_VOLUMEDOWN>;
  1070. debounce-interval = <10>;
  1071. wakeup-event-action = <EV_ACT_ASSERTED>;
  1072. wakeup-source;
  1073. };
  1074. };
  1075. vdd_5v0_sys: regulator-5v0 {
  1076. compatible = "regulator-fixed";
  1077. regulator-name = "vdd_5v0";
  1078. regulator-min-microvolt = <5000000>;
  1079. regulator-max-microvolt = <5000000>;
  1080. regulator-always-on;
  1081. regulator-boot-on;
  1082. };
  1083. vdd_3v3_sys: regulator-3v3 {
  1084. compatible = "regulator-fixed";
  1085. regulator-name = "vdd_3v3";
  1086. regulator-min-microvolt = <3300000>;
  1087. regulator-max-microvolt = <3300000>;
  1088. regulator-always-on;
  1089. regulator-boot-on;
  1090. vin-supply = <&vdd_5v0_sys>;
  1091. };
  1092. vdd_pnl: regulator-panel {
  1093. compatible = "regulator-fixed";
  1094. regulator-name = "vdd_panel";
  1095. regulator-min-microvolt = <3300000>;
  1096. regulator-max-microvolt = <3300000>;
  1097. regulator-enable-ramp-delay = <300000>;
  1098. gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
  1099. enable-active-high;
  1100. vin-supply = <&vdd_3v3_sys>;
  1101. };
  1102. vcc_3v3_ts: regulator-ts {
  1103. compatible = "regulator-fixed";
  1104. regulator-name = "ldo_s-1167_3v3";
  1105. regulator-min-microvolt = <3300000>;
  1106. regulator-max-microvolt = <3300000>;
  1107. regulator-always-on;
  1108. regulator-boot-on;
  1109. vin-supply = <&vdd_5v0_sys>;
  1110. };
  1111. sound {
  1112. compatible = "nvidia,tegra-audio-rt5640-grouper",
  1113. "nvidia,tegra-audio-rt5640";
  1114. nvidia,model = "ASUS Google Nexus 7 ALC5642";
  1115. nvidia,audio-routing =
  1116. "Headphones", "HPOR",
  1117. "Headphones", "HPOL",
  1118. "Speakers", "SPORP",
  1119. "Speakers", "SPORN",
  1120. "Speakers", "SPOLP",
  1121. "Speakers", "SPOLN",
  1122. "DMIC1", "Mic Jack";
  1123. nvidia,i2s-controller = <&tegra_i2s1>;
  1124. nvidia,audio-codec = <&rt5640>;
  1125. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
  1126. clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
  1127. <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  1128. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1129. clock-names = "pll_a", "pll_a_out0", "mclk";
  1130. assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
  1131. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1132. assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  1133. <&tegra_car TEGRA30_CLK_EXTERN1>;
  1134. };
  1135. thermal-zones {
  1136. /*
  1137. * NCT72 has two sensors:
  1138. *
  1139. * 0: internal that monitors ambient/skin temperature
  1140. * 1: external that is connected to the CPU's diode
  1141. *
  1142. * Ideally we should use userspace thermal governor,
  1143. * but it's a much more complex solution. The "skin"
  1144. * zone is a simpler solution which prevents Nexus 7
  1145. * from getting too hot from a user's tactile perspective.
  1146. * The CPU zone is intended to protect silicon from damage.
  1147. */
  1148. skin-thermal {
  1149. polling-delay-passive = <1000>; /* milliseconds */
  1150. polling-delay = <5000>; /* milliseconds */
  1151. thermal-sensors = <&nct72 0>;
  1152. trips {
  1153. trip0: skin-alert {
  1154. /* throttle at 57C until temperature drops to 56.8C */
  1155. temperature = <57000>;
  1156. hysteresis = <200>;
  1157. type = "passive";
  1158. };
  1159. trip1: skin-crit {
  1160. /* shut down at 65C */
  1161. temperature = <65000>;
  1162. hysteresis = <2000>;
  1163. type = "critical";
  1164. };
  1165. };
  1166. cooling-maps {
  1167. map0 {
  1168. trip = <&trip0>;
  1169. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1170. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1171. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1172. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1173. <&actmon THERMAL_NO_LIMIT
  1174. THERMAL_NO_LIMIT>;
  1175. };
  1176. };
  1177. };
  1178. cpu-thermal {
  1179. polling-delay-passive = <1000>; /* milliseconds */
  1180. polling-delay = <5000>; /* milliseconds */
  1181. thermal-sensors = <&nct72 1>;
  1182. trips {
  1183. trip2: cpu-alert {
  1184. /* throttle at 85C until temperature drops to 84.8C */
  1185. temperature = <85000>;
  1186. hysteresis = <200>;
  1187. type = "passive";
  1188. };
  1189. trip3: cpu-crit {
  1190. /* shut down at 90C */
  1191. temperature = <90000>;
  1192. hysteresis = <2000>;
  1193. type = "critical";
  1194. };
  1195. };
  1196. cooling-maps {
  1197. map1 {
  1198. trip = <&trip2>;
  1199. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1200. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1201. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1202. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  1203. <&actmon THERMAL_NO_LIMIT
  1204. THERMAL_NO_LIMIT>;
  1205. };
  1206. };
  1207. };
  1208. };
  1209. };