tegra20-trimslice.dts 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include "tegra20.dtsi"
  5. #include "tegra20-cpu-opp.dtsi"
  6. / {
  7. model = "Compulab TrimSlice board";
  8. compatible = "compulab,trimslice", "nvidia,tegra20";
  9. aliases {
  10. rtc0 = "/i2c@7000c500/rtc@56";
  11. rtc1 = "/rtc@7000e000";
  12. serial0 = &uarta;
  13. };
  14. chosen {
  15. stdout-path = "serial0:115200n8";
  16. };
  17. memory@0 {
  18. reg = <0x00000000 0x40000000>;
  19. };
  20. host1x@50000000 {
  21. hdmi@54280000 {
  22. status = "okay";
  23. vdd-supply = <&hdmi_vdd_reg>;
  24. pll-supply = <&hdmi_pll_reg>;
  25. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  26. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  27. GPIO_ACTIVE_HIGH>;
  28. };
  29. };
  30. pinmux@70000014 {
  31. pinctrl-names = "default";
  32. pinctrl-0 = <&state_default>;
  33. state_default: pinmux {
  34. ata {
  35. nvidia,pins = "ata";
  36. nvidia,function = "ide";
  37. };
  38. atb {
  39. nvidia,pins = "atb", "gma";
  40. nvidia,function = "sdio4";
  41. };
  42. atc {
  43. nvidia,pins = "atc", "gmb";
  44. nvidia,function = "nand";
  45. };
  46. atd {
  47. nvidia,pins = "atd", "ate", "gme", "pta";
  48. nvidia,function = "gmi";
  49. };
  50. cdev1 {
  51. nvidia,pins = "cdev1";
  52. nvidia,function = "plla_out";
  53. };
  54. cdev2 {
  55. nvidia,pins = "cdev2";
  56. nvidia,function = "pllp_out4";
  57. };
  58. crtp {
  59. nvidia,pins = "crtp";
  60. nvidia,function = "crt";
  61. };
  62. csus {
  63. nvidia,pins = "csus";
  64. nvidia,function = "vi_sensor_clk";
  65. };
  66. dap1 {
  67. nvidia,pins = "dap1";
  68. nvidia,function = "dap1";
  69. };
  70. dap2 {
  71. nvidia,pins = "dap2";
  72. nvidia,function = "dap2";
  73. };
  74. dap3 {
  75. nvidia,pins = "dap3";
  76. nvidia,function = "dap3";
  77. };
  78. dap4 {
  79. nvidia,pins = "dap4";
  80. nvidia,function = "dap4";
  81. };
  82. ddc {
  83. nvidia,pins = "ddc";
  84. nvidia,function = "i2c2";
  85. };
  86. dta {
  87. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  88. nvidia,function = "vi";
  89. };
  90. dtf {
  91. nvidia,pins = "dtf";
  92. nvidia,function = "i2c3";
  93. };
  94. gmc {
  95. nvidia,pins = "gmc", "gmd";
  96. nvidia,function = "sflash";
  97. };
  98. gpu {
  99. nvidia,pins = "gpu";
  100. nvidia,function = "uarta";
  101. };
  102. gpu7 {
  103. nvidia,pins = "gpu7";
  104. nvidia,function = "rtck";
  105. };
  106. gpv {
  107. nvidia,pins = "gpv", "slxa", "slxk";
  108. nvidia,function = "pcie";
  109. };
  110. hdint {
  111. nvidia,pins = "hdint";
  112. nvidia,function = "hdmi";
  113. };
  114. i2cp {
  115. nvidia,pins = "i2cp";
  116. nvidia,function = "i2cp";
  117. };
  118. irrx {
  119. nvidia,pins = "irrx", "irtx";
  120. nvidia,function = "uartb";
  121. };
  122. kbca {
  123. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  124. "kbce", "kbcf";
  125. nvidia,function = "kbc";
  126. };
  127. lcsn {
  128. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  129. "ld3", "ld4", "ld5", "ld6", "ld7",
  130. "ld8", "ld9", "ld10", "ld11", "ld12",
  131. "ld13", "ld14", "ld15", "ld16", "ld17",
  132. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  133. "lhs", "lm0", "lm1", "lpp", "lpw0",
  134. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  135. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  136. "lvs";
  137. nvidia,function = "displaya";
  138. };
  139. owc {
  140. nvidia,pins = "owc", "uac";
  141. nvidia,function = "rsvd2";
  142. };
  143. pmc {
  144. nvidia,pins = "pmc";
  145. nvidia,function = "pwr_on";
  146. };
  147. rm {
  148. nvidia,pins = "rm";
  149. nvidia,function = "i2c1";
  150. };
  151. sdb {
  152. nvidia,pins = "sdb", "sdc", "sdd";
  153. nvidia,function = "pwm";
  154. };
  155. sdio1 {
  156. nvidia,pins = "sdio1";
  157. nvidia,function = "sdio1";
  158. };
  159. slxc {
  160. nvidia,pins = "slxc", "slxd";
  161. nvidia,function = "sdio3";
  162. };
  163. spdi {
  164. nvidia,pins = "spdi", "spdo";
  165. nvidia,function = "spdif";
  166. };
  167. spia {
  168. nvidia,pins = "spia", "spib", "spic";
  169. nvidia,function = "spi2";
  170. };
  171. spid {
  172. nvidia,pins = "spid", "spie", "spif";
  173. nvidia,function = "spi1";
  174. };
  175. spig {
  176. nvidia,pins = "spig", "spih";
  177. nvidia,function = "spi2_alt";
  178. };
  179. uaa {
  180. nvidia,pins = "uaa", "uab", "uda";
  181. nvidia,function = "ulpi";
  182. };
  183. uad {
  184. nvidia,pins = "uad";
  185. nvidia,function = "irda";
  186. };
  187. uca {
  188. nvidia,pins = "uca", "ucb";
  189. nvidia,function = "uartc";
  190. };
  191. conf_ata {
  192. nvidia,pins = "ata", "atc", "atd", "ate",
  193. "crtp", "dap2", "dap3", "dap4", "dta",
  194. "dtb", "dtc", "dtd", "dte", "gmb",
  195. "gme", "i2cp", "pta", "slxc", "slxd",
  196. "spdi", "spdo", "uda";
  197. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  198. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  199. };
  200. conf_atb {
  201. nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
  202. "gma", "gmc", "gmd", "gpu", "gpu7",
  203. "gpv", "sdio1", "slxa", "slxk", "uac";
  204. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  205. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  206. };
  207. conf_ck32 {
  208. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  209. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  210. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  211. };
  212. conf_csus {
  213. nvidia,pins = "csus", "spia", "spib",
  214. "spid", "spif";
  215. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  216. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  217. };
  218. conf_ddc {
  219. nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
  220. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  221. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  222. };
  223. conf_hdint {
  224. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  225. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  226. "lvp0", "pmc";
  227. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  228. };
  229. conf_irrx {
  230. nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
  231. "kbcc", "kbcd", "kbce", "kbcf", "owc",
  232. "spic", "spie", "spig", "spih", "uaa",
  233. "uab", "uad", "uca", "ucb";
  234. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  235. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  236. };
  237. conf_lc {
  238. nvidia,pins = "lc", "ls";
  239. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  240. };
  241. conf_ld0 {
  242. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  243. "ld5", "ld6", "ld7", "ld8", "ld9",
  244. "ld10", "ld11", "ld12", "ld13", "ld14",
  245. "ld15", "ld16", "ld17", "ldi", "lhp0",
  246. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  247. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  248. "lvs", "sdb";
  249. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  250. };
  251. conf_ld17_0 {
  252. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  253. "ld23_22";
  254. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  255. };
  256. conf_spif {
  257. nvidia,pins = "spif";
  258. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  259. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  260. };
  261. };
  262. };
  263. i2s@70002800 {
  264. status = "okay";
  265. };
  266. serial@70006000 {
  267. status = "okay";
  268. };
  269. dvi_ddc: i2c@7000c000 {
  270. status = "okay";
  271. clock-frequency = <100000>;
  272. };
  273. spi@7000c380 {
  274. status = "okay";
  275. spi-max-frequency = <48000000>;
  276. flash@0 {
  277. compatible = "winbond,w25q80bl", "jedec,spi-nor";
  278. reg = <0>;
  279. spi-max-frequency = <48000000>;
  280. };
  281. };
  282. hdmi_ddc: i2c@7000c400 {
  283. status = "okay";
  284. clock-frequency = <100000>;
  285. };
  286. i2c@7000c500 {
  287. status = "okay";
  288. clock-frequency = <400000>;
  289. codec: codec@1a {
  290. compatible = "ti,tlv320aic23";
  291. reg = <0x1a>;
  292. };
  293. rtc@56 {
  294. compatible = "emmicro,em3027";
  295. reg = <0x56>;
  296. };
  297. };
  298. pmc@7000e400 {
  299. nvidia,suspend-mode = <1>;
  300. nvidia,cpu-pwr-good-time = <5000>;
  301. nvidia,cpu-pwr-off-time = <5000>;
  302. nvidia,core-pwr-good-time = <3845 3845>;
  303. nvidia,core-pwr-off-time = <3875>;
  304. nvidia,sys-clock-req-active-high;
  305. core-supply = <&vdd_core>;
  306. };
  307. pcie@80003000 {
  308. status = "okay";
  309. avdd-pex-supply = <&pci_vdd_reg>;
  310. vdd-pex-supply = <&pci_vdd_reg>;
  311. avdd-pex-pll-supply = <&pci_vdd_reg>;
  312. avdd-plle-supply = <&pci_vdd_reg>;
  313. vddio-pex-clk-supply = <&pci_clk_reg>;
  314. pci@1,0 {
  315. status = "okay";
  316. };
  317. };
  318. usb@c5000000 {
  319. status = "okay";
  320. };
  321. usb-phy@c5000000 {
  322. status = "okay";
  323. vbus-supply = <&vbus_reg>;
  324. };
  325. usb@c5004000 {
  326. status = "okay";
  327. };
  328. usb-phy@c5004000 {
  329. status = "okay";
  330. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  331. GPIO_ACTIVE_LOW>;
  332. };
  333. usb@c5008000 {
  334. status = "okay";
  335. };
  336. usb-phy@c5008000 {
  337. status = "okay";
  338. };
  339. mmc@c8000000 {
  340. status = "okay";
  341. broken-cd;
  342. bus-width = <4>;
  343. };
  344. mmc@c8000600 {
  345. status = "okay";
  346. cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
  347. wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  348. bus-width = <4>;
  349. };
  350. clk32k_in: clock-32k {
  351. compatible = "fixed-clock";
  352. clock-frequency = <32768>;
  353. #clock-cells = <0>;
  354. };
  355. gpio-keys {
  356. compatible = "gpio-keys";
  357. key-power {
  358. label = "Power";
  359. gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
  360. linux,code = <KEY_POWER>;
  361. wakeup-source;
  362. };
  363. };
  364. poweroff {
  365. compatible = "gpio-poweroff";
  366. gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
  367. };
  368. hdmi_vdd_reg: regulator-hdmi {
  369. compatible = "regulator-fixed";
  370. regulator-name = "avdd_hdmi";
  371. regulator-min-microvolt = <3300000>;
  372. regulator-max-microvolt = <3300000>;
  373. regulator-always-on;
  374. };
  375. hdmi_pll_reg: regulator-hdmipll {
  376. compatible = "regulator-fixed";
  377. regulator-name = "avdd_hdmi_pll";
  378. regulator-min-microvolt = <1800000>;
  379. regulator-max-microvolt = <1800000>;
  380. regulator-always-on;
  381. };
  382. vbus_reg: regulator-vbus {
  383. compatible = "regulator-fixed";
  384. regulator-name = "usb1_vbus";
  385. regulator-min-microvolt = <5000000>;
  386. regulator-max-microvolt = <5000000>;
  387. enable-active-high;
  388. gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
  389. regulator-always-on;
  390. regulator-boot-on;
  391. };
  392. pci_clk_reg: regulator-pciclk {
  393. compatible = "regulator-fixed";
  394. regulator-name = "pci_clk";
  395. regulator-min-microvolt = <3300000>;
  396. regulator-max-microvolt = <3300000>;
  397. regulator-always-on;
  398. };
  399. pci_vdd_reg: regulator-pcivdd {
  400. compatible = "regulator-fixed";
  401. regulator-name = "pci_vdd";
  402. regulator-min-microvolt = <1050000>;
  403. regulator-max-microvolt = <1050000>;
  404. regulator-always-on;
  405. };
  406. vdd_core: regulator-core {
  407. compatible = "regulator-fixed";
  408. regulator-name = "vdd_core";
  409. regulator-min-microvolt = <1300000>;
  410. regulator-max-microvolt = <1300000>;
  411. regulator-always-on;
  412. };
  413. sound {
  414. compatible = "nvidia,tegra-audio-trimslice";
  415. nvidia,i2s-controller = <&tegra_i2s1>;
  416. nvidia,audio-codec = <&codec>;
  417. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  418. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  419. <&tegra_car TEGRA20_CLK_CDEV1>;
  420. clock-names = "pll_a", "pll_a_out0", "mclk";
  421. };
  422. cpus {
  423. cpu0: cpu@0 {
  424. operating-points-v2 = <&cpu0_opp_table>;
  425. };
  426. cpu@1 {
  427. operating-points-v2 = <&cpu0_opp_table>;
  428. };
  429. };
  430. };