tegra20-tamonten.dtsi 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include "tegra20.dtsi"
  3. / {
  4. model = "Avionic Design Tamonten SOM";
  5. compatible = "ad,tamonten", "nvidia,tegra20";
  6. aliases {
  7. rtc0 = "/i2c@7000d000/tps6586x@34";
  8. rtc1 = "/rtc@7000e000";
  9. serial0 = &uartd;
  10. };
  11. chosen {
  12. stdout-path = "serial0:115200n8";
  13. };
  14. memory@0 {
  15. reg = <0x00000000 0x20000000>;
  16. };
  17. host1x@50000000 {
  18. hdmi@54280000 {
  19. vdd-supply = <&hdmi_vdd_reg>;
  20. pll-supply = <&hdmi_pll_reg>;
  21. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  22. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  23. GPIO_ACTIVE_HIGH>;
  24. };
  25. };
  26. pinmux@70000014 {
  27. pinctrl-names = "default";
  28. pinctrl-0 = <&state_default>;
  29. state_default: pinmux {
  30. ata {
  31. nvidia,pins = "ata";
  32. nvidia,function = "ide";
  33. };
  34. atb {
  35. nvidia,pins = "atb", "gma", "gme";
  36. nvidia,function = "sdio4";
  37. };
  38. atc {
  39. nvidia,pins = "atc";
  40. nvidia,function = "nand";
  41. };
  42. atd {
  43. nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  44. "spia", "spib", "spic";
  45. nvidia,function = "gmi";
  46. };
  47. cdev1 {
  48. nvidia,pins = "cdev1";
  49. nvidia,function = "plla_out";
  50. };
  51. cdev2 {
  52. nvidia,pins = "cdev2";
  53. nvidia,function = "pllp_out4";
  54. };
  55. crtp {
  56. nvidia,pins = "crtp";
  57. nvidia,function = "crt";
  58. };
  59. csus {
  60. nvidia,pins = "csus";
  61. nvidia,function = "vi_sensor_clk";
  62. };
  63. dap1 {
  64. nvidia,pins = "dap1";
  65. nvidia,function = "dap1";
  66. };
  67. dap2 {
  68. nvidia,pins = "dap2";
  69. nvidia,function = "dap2";
  70. };
  71. dap3 {
  72. nvidia,pins = "dap3";
  73. nvidia,function = "dap3";
  74. };
  75. dap4 {
  76. nvidia,pins = "dap4";
  77. nvidia,function = "dap4";
  78. };
  79. dta {
  80. nvidia,pins = "dta", "dtd";
  81. nvidia,function = "sdio2";
  82. };
  83. dtb {
  84. nvidia,pins = "dtb", "dtc", "dte";
  85. nvidia,function = "rsvd1";
  86. };
  87. dtf {
  88. nvidia,pins = "dtf";
  89. nvidia,function = "i2c3";
  90. };
  91. gmc {
  92. nvidia,pins = "gmc";
  93. nvidia,function = "uartd";
  94. };
  95. gpu7 {
  96. nvidia,pins = "gpu7";
  97. nvidia,function = "rtck";
  98. };
  99. gpv {
  100. nvidia,pins = "gpv", "slxa", "slxk";
  101. nvidia,function = "pcie";
  102. };
  103. hdint {
  104. nvidia,pins = "hdint";
  105. nvidia,function = "hdmi";
  106. };
  107. i2cp {
  108. nvidia,pins = "i2cp";
  109. nvidia,function = "i2cp";
  110. };
  111. irrx {
  112. nvidia,pins = "irrx", "irtx";
  113. nvidia,function = "uarta";
  114. };
  115. kbca {
  116. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  117. "kbce", "kbcf";
  118. nvidia,function = "kbc";
  119. };
  120. lcsn {
  121. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  122. "ld3", "ld4", "ld5", "ld6", "ld7",
  123. "ld8", "ld9", "ld10", "ld11", "ld12",
  124. "ld13", "ld14", "ld15", "ld16", "ld17",
  125. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  126. "lhs", "lm0", "lm1", "lpp", "lpw0",
  127. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  128. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  129. "lvs";
  130. nvidia,function = "displaya";
  131. };
  132. owc {
  133. nvidia,pins = "owc", "spdi", "spdo", "uac";
  134. nvidia,function = "rsvd2";
  135. };
  136. pmc {
  137. nvidia,pins = "pmc";
  138. nvidia,function = "pwr_on";
  139. };
  140. rm {
  141. nvidia,pins = "rm";
  142. nvidia,function = "i2c1";
  143. };
  144. sdb {
  145. nvidia,pins = "sdb", "sdc", "sdd";
  146. nvidia,function = "pwm";
  147. };
  148. sdio1 {
  149. nvidia,pins = "sdio1";
  150. nvidia,function = "sdio1";
  151. };
  152. slxc {
  153. nvidia,pins = "slxc", "slxd";
  154. nvidia,function = "spdif";
  155. };
  156. spid {
  157. nvidia,pins = "spid", "spie", "spif";
  158. nvidia,function = "spi1";
  159. };
  160. spig {
  161. nvidia,pins = "spig", "spih";
  162. nvidia,function = "spi2_alt";
  163. };
  164. uaa {
  165. nvidia,pins = "uaa", "uab", "uda";
  166. nvidia,function = "ulpi";
  167. };
  168. uad {
  169. nvidia,pins = "uad";
  170. nvidia,function = "irda";
  171. };
  172. uca {
  173. nvidia,pins = "uca", "ucb";
  174. nvidia,function = "uartc";
  175. };
  176. conf_ata {
  177. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  178. "cdev1", "cdev2", "dap1", "dtb", "dtf",
  179. "gma", "gmb", "gmc", "gmd", "gme", "gpu7",
  180. "gpv", "i2cp", "irrx", "irtx", "pta",
  181. "rm", "slxa", "slxk", "spia", "spib",
  182. "uac";
  183. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  184. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  185. };
  186. conf_ck32 {
  187. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  188. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  189. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  190. };
  191. conf_csus {
  192. nvidia,pins = "csus", "spid", "spif";
  193. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  194. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  195. };
  196. conf_crtp {
  197. nvidia,pins = "crtp", "dap2", "dap3", "dap4",
  198. "dtc", "dte", "gpu", "sdio1",
  199. "slxc", "slxd", "spdi", "spdo", "spig",
  200. "uda";
  201. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  202. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  203. };
  204. conf_ddc {
  205. nvidia,pins = "ddc", "dta", "dtd", "kbca",
  206. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  207. "sdc", "uad", "uca";
  208. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  209. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  210. };
  211. conf_hdint {
  212. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  213. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  214. "lvp0", "owc", "sdb";
  215. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  216. };
  217. conf_sdd {
  218. nvidia,pins = "sdd", "spic", "spie", "spih",
  219. "uaa", "uab", "ucb";
  220. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  221. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  222. };
  223. conf_lc {
  224. nvidia,pins = "lc", "ls";
  225. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  226. };
  227. conf_ld0 {
  228. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  229. "ld5", "ld6", "ld7", "ld8", "ld9",
  230. "ld10", "ld11", "ld12", "ld13", "ld14",
  231. "ld15", "ld16", "ld17", "ldi", "lhp0",
  232. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  233. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  234. "lvs", "pmc";
  235. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  236. };
  237. conf_ld17_0 {
  238. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  239. "ld23_22";
  240. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  241. };
  242. };
  243. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  244. ddc {
  245. nvidia,pins = "ddc";
  246. nvidia,function = "i2c2";
  247. };
  248. pta {
  249. nvidia,pins = "pta";
  250. nvidia,function = "rsvd4";
  251. };
  252. };
  253. state_i2cmux_pta: pinmux_i2cmux_pta {
  254. ddc {
  255. nvidia,pins = "ddc";
  256. nvidia,function = "rsvd4";
  257. };
  258. pta {
  259. nvidia,pins = "pta";
  260. nvidia,function = "i2c2";
  261. };
  262. };
  263. state_i2cmux_idle: pinmux_i2cmux_idle {
  264. ddc {
  265. nvidia,pins = "ddc";
  266. nvidia,function = "rsvd4";
  267. };
  268. pta {
  269. nvidia,pins = "pta";
  270. nvidia,function = "rsvd4";
  271. };
  272. };
  273. };
  274. i2s@70002800 {
  275. status = "okay";
  276. };
  277. serial@70006300 {
  278. status = "okay";
  279. };
  280. i2c@7000c000 {
  281. clock-frequency = <400000>;
  282. status = "okay";
  283. };
  284. i2c@7000c400 {
  285. clock-frequency = <100000>;
  286. status = "okay";
  287. };
  288. i2cmux {
  289. compatible = "i2c-mux-pinctrl";
  290. #address-cells = <1>;
  291. #size-cells = <0>;
  292. i2c-parent = <&{/i2c@7000c400}>;
  293. pinctrl-names = "ddc", "pta", "idle";
  294. pinctrl-0 = <&state_i2cmux_ddc>;
  295. pinctrl-1 = <&state_i2cmux_pta>;
  296. pinctrl-2 = <&state_i2cmux_idle>;
  297. hdmi_ddc: i2c@0 {
  298. reg = <0>;
  299. #address-cells = <1>;
  300. #size-cells = <0>;
  301. };
  302. i2c@1 {
  303. reg = <1>;
  304. #address-cells = <1>;
  305. #size-cells = <0>;
  306. };
  307. };
  308. i2c@7000d000 {
  309. clock-frequency = <400000>;
  310. status = "okay";
  311. pmic: tps6586x@34 {
  312. compatible = "ti,tps6586x";
  313. reg = <0x34>;
  314. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  315. ti,system-power-controller;
  316. #gpio-cells = <2>;
  317. gpio-controller;
  318. /* vdd_5v0_reg must be provided by the base board */
  319. sys-supply = <&vdd_5v0_reg>;
  320. vin-sm0-supply = <&sys_reg>;
  321. vin-sm1-supply = <&sys_reg>;
  322. vin-sm2-supply = <&sys_reg>;
  323. vinldo01-supply = <&sm2_reg>;
  324. vinldo23-supply = <&sm2_reg>;
  325. vinldo4-supply = <&sm2_reg>;
  326. vinldo678-supply = <&sm2_reg>;
  327. vinldo9-supply = <&sm2_reg>;
  328. regulators {
  329. sys_reg: sys {
  330. regulator-name = "vdd_sys";
  331. regulator-always-on;
  332. };
  333. vdd_core: sm0 {
  334. regulator-name = "vdd_sys_sm0,vdd_core";
  335. regulator-min-microvolt = <1200000>;
  336. regulator-max-microvolt = <1200000>;
  337. regulator-always-on;
  338. };
  339. sm1 {
  340. regulator-name = "vdd_sys_sm1,vdd_cpu";
  341. regulator-min-microvolt = <1000000>;
  342. regulator-max-microvolt = <1000000>;
  343. regulator-always-on;
  344. };
  345. sm2_reg: sm2 {
  346. regulator-name = "vdd_sys_sm2,vin_ldo*";
  347. regulator-min-microvolt = <3700000>;
  348. regulator-max-microvolt = <3700000>;
  349. regulator-always-on;
  350. };
  351. pci_clk_reg: ldo0 {
  352. regulator-name = "vdd_ldo0,vddio_pex_clk";
  353. regulator-min-microvolt = <3300000>;
  354. regulator-max-microvolt = <3300000>;
  355. };
  356. ldo1 {
  357. regulator-name = "vdd_ldo1,avdd_pll*";
  358. regulator-min-microvolt = <1100000>;
  359. regulator-max-microvolt = <1100000>;
  360. regulator-always-on;
  361. };
  362. ldo2 {
  363. regulator-name = "vdd_ldo2,vdd_rtc";
  364. regulator-min-microvolt = <1200000>;
  365. regulator-max-microvolt = <1200000>;
  366. };
  367. ldo3 {
  368. regulator-name = "vdd_ldo3,avdd_usb*";
  369. regulator-min-microvolt = <3300000>;
  370. regulator-max-microvolt = <3300000>;
  371. regulator-always-on;
  372. };
  373. ldo4 {
  374. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  375. regulator-min-microvolt = <1800000>;
  376. regulator-max-microvolt = <1800000>;
  377. regulator-always-on;
  378. };
  379. ldo5 {
  380. regulator-name = "vdd_ldo5,vcore_mmc";
  381. regulator-min-microvolt = <2850000>;
  382. regulator-max-microvolt = <2850000>;
  383. };
  384. ldo6 {
  385. regulator-name = "vdd_ldo6,avdd_vdac";
  386. /*
  387. * According to the Tegra 2 Automotive
  388. * DataSheet, a typical value for this
  389. * would be 2.8V, but the PMIC only
  390. * supports 2.85V.
  391. */
  392. regulator-min-microvolt = <2850000>;
  393. regulator-max-microvolt = <2850000>;
  394. };
  395. hdmi_vdd_reg: ldo7 {
  396. regulator-name = "vdd_ldo7,avdd_hdmi";
  397. regulator-min-microvolt = <3300000>;
  398. regulator-max-microvolt = <3300000>;
  399. };
  400. hdmi_pll_reg: ldo8 {
  401. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  402. regulator-min-microvolt = <1800000>;
  403. regulator-max-microvolt = <1800000>;
  404. };
  405. ldo9 {
  406. regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
  407. /*
  408. * According to the Tegra 2 Automotive
  409. * DataSheet, a typical value for this
  410. * would be 2.8V, but the PMIC only
  411. * supports 2.85V.
  412. */
  413. regulator-min-microvolt = <2850000>;
  414. regulator-max-microvolt = <2850000>;
  415. regulator-always-on;
  416. };
  417. ldo_rtc {
  418. regulator-name = "vdd_rtc_out";
  419. regulator-min-microvolt = <3300000>;
  420. regulator-max-microvolt = <3300000>;
  421. regulator-always-on;
  422. };
  423. };
  424. };
  425. temperature-sensor@4c {
  426. compatible = "onnn,nct1008";
  427. reg = <0x4c>;
  428. };
  429. };
  430. pmc@7000e400 {
  431. nvidia,invert-interrupt;
  432. nvidia,suspend-mode = <1>;
  433. nvidia,cpu-pwr-good-time = <5000>;
  434. nvidia,cpu-pwr-off-time = <5000>;
  435. nvidia,core-pwr-good-time = <3845 3845>;
  436. nvidia,core-pwr-off-time = <3875>;
  437. nvidia,sys-clock-req-active-high;
  438. core-supply = <&vdd_core>;
  439. };
  440. pcie@80003000 {
  441. avdd-pex-supply = <&pci_vdd_reg>;
  442. vdd-pex-supply = <&pci_vdd_reg>;
  443. avdd-pex-pll-supply = <&pci_vdd_reg>;
  444. avdd-plle-supply = <&pci_vdd_reg>;
  445. vddio-pex-clk-supply = <&pci_clk_reg>;
  446. };
  447. usb@c5008000 {
  448. status = "okay";
  449. };
  450. usb-phy@c5008000 {
  451. status = "okay";
  452. };
  453. mmc@c8000600 {
  454. cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
  455. wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
  456. bus-width = <4>;
  457. status = "okay";
  458. };
  459. clk32k_in: clock-32k {
  460. compatible = "fixed-clock";
  461. clock-frequency = <32768>;
  462. #clock-cells = <0>;
  463. };
  464. pci_vdd_reg: regulator-1v05 {
  465. compatible = "regulator-fixed";
  466. regulator-name = "vdd_1v05";
  467. regulator-min-microvolt = <1050000>;
  468. regulator-max-microvolt = <1050000>;
  469. gpio = <&pmic 2 0>;
  470. enable-active-high;
  471. };
  472. };