tegra124-venice2.dts 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include "tegra124.dtsi"
  5. / {
  6. model = "NVIDIA Tegra124 Venice2";
  7. compatible = "nvidia,venice2", "nvidia,tegra124";
  8. aliases {
  9. rtc0 = "/i2c@7000d000/pmic@40";
  10. rtc1 = "/rtc@7000e000";
  11. serial0 = &uarta;
  12. };
  13. chosen {
  14. stdout-path = "serial0:115200n8";
  15. };
  16. memory@80000000 {
  17. reg = <0x0 0x80000000 0x0 0x80000000>;
  18. };
  19. host1x@50000000 {
  20. hdmi@54280000 {
  21. status = "okay";
  22. vdd-supply = <&vdd_3v3_hdmi>;
  23. pll-supply = <&vdd_hdmi_pll>;
  24. hdmi-supply = <&vdd_5v0_hdmi>;
  25. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  26. nvidia,hpd-gpio =
  27. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  28. };
  29. sor@54540000 {
  30. status = "okay";
  31. avdd-io-hdmi-dp-supply = <&vdd_1v05_run>;
  32. vdd-hdmi-dp-pll-supply = <&vdd_3v3_run>;
  33. nvidia,dpaux = <&dpaux>;
  34. nvidia,panel = <&panel>;
  35. };
  36. dpaux@545c0000 {
  37. vdd-supply = <&vdd_3v3_panel>;
  38. status = "okay";
  39. aux-bus {
  40. panel: panel {
  41. compatible = "lg,lp129qe";
  42. backlight = <&backlight>;
  43. };
  44. };
  45. };
  46. };
  47. gpu@57000000 {
  48. /*
  49. * Node left disabled on purpose - the bootloader will enable
  50. * it after having set the VPR up
  51. */
  52. vdd-supply = <&vdd_gpu>;
  53. };
  54. pinmux: pinmux@70000868 {
  55. pinctrl-names = "boot";
  56. pinctrl-0 = <&pinmux_boot>;
  57. pinmux_boot: common {
  58. dap_mclk1_pw4 {
  59. nvidia,pins = "dap_mclk1_pw4";
  60. nvidia,function = "extperiph1";
  61. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  62. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  63. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  64. };
  65. dap1_din_pn1 {
  66. nvidia,pins = "dap1_din_pn1";
  67. nvidia,function = "i2s0";
  68. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  69. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  70. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  71. };
  72. dap1_dout_pn2 {
  73. nvidia,pins = "dap1_dout_pn2",
  74. "dap1_fs_pn0",
  75. "dap1_sclk_pn3";
  76. nvidia,function = "i2s0";
  77. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  78. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  79. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  80. };
  81. dap2_din_pa4 {
  82. nvidia,pins = "dap2_din_pa4";
  83. nvidia,function = "i2s1";
  84. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  85. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  86. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  87. };
  88. dap2_dout_pa5 {
  89. nvidia,pins = "dap2_dout_pa5",
  90. "dap2_fs_pa2",
  91. "dap2_sclk_pa3";
  92. nvidia,function = "i2s1";
  93. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  94. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  95. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  96. };
  97. dvfs_pwm_px0 {
  98. nvidia,pins = "dvfs_pwm_px0",
  99. "dvfs_clk_px2";
  100. nvidia,function = "cldvfs";
  101. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  102. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  103. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  104. };
  105. ulpi_clk_py0 {
  106. nvidia,pins = "ulpi_clk_py0",
  107. "ulpi_nxt_py2",
  108. "ulpi_stp_py3";
  109. nvidia,function = "spi1";
  110. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  111. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  112. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  113. };
  114. ulpi_dir_py1 {
  115. nvidia,pins = "ulpi_dir_py1";
  116. nvidia,function = "spi1";
  117. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  118. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  119. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  120. };
  121. cam_i2c_scl_pbb1 {
  122. nvidia,pins = "cam_i2c_scl_pbb1",
  123. "cam_i2c_sda_pbb2";
  124. nvidia,function = "i2c3";
  125. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  126. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  127. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  128. nvidia,lock = <TEGRA_PIN_DISABLE>;
  129. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  130. };
  131. gen2_i2c_scl_pt5 {
  132. nvidia,pins = "gen2_i2c_scl_pt5",
  133. "gen2_i2c_sda_pt6";
  134. nvidia,function = "i2c2";
  135. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  136. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  137. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  138. nvidia,lock = <TEGRA_PIN_DISABLE>;
  139. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  140. };
  141. pg4 {
  142. nvidia,pins = "pg4",
  143. "pg5",
  144. "pg6",
  145. "pi3";
  146. nvidia,function = "spi4";
  147. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  148. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  149. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  150. };
  151. pg7 {
  152. nvidia,pins = "pg7";
  153. nvidia,function = "spi4";
  154. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  155. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  156. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  157. };
  158. ph1 {
  159. nvidia,pins = "ph1";
  160. nvidia,function = "pwm1";
  161. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  162. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  163. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  164. };
  165. pk0 {
  166. nvidia,pins = "pk0",
  167. "kb_row15_ps7",
  168. "clk_32k_out_pa0";
  169. nvidia,function = "soc";
  170. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  171. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  172. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  173. };
  174. sdmmc1_clk_pz0 {
  175. nvidia,pins = "sdmmc1_clk_pz0";
  176. nvidia,function = "sdmmc1";
  177. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  178. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  179. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  180. };
  181. sdmmc1_cmd_pz1 {
  182. nvidia,pins = "sdmmc1_cmd_pz1",
  183. "sdmmc1_dat0_py7",
  184. "sdmmc1_dat1_py6",
  185. "sdmmc1_dat2_py5",
  186. "sdmmc1_dat3_py4";
  187. nvidia,function = "sdmmc1";
  188. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  189. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  190. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  191. };
  192. sdmmc3_clk_pa6 {
  193. nvidia,pins = "sdmmc3_clk_pa6";
  194. nvidia,function = "sdmmc3";
  195. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  196. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  197. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  198. };
  199. sdmmc3_cmd_pa7 {
  200. nvidia,pins = "sdmmc3_cmd_pa7",
  201. "sdmmc3_dat0_pb7",
  202. "sdmmc3_dat1_pb6",
  203. "sdmmc3_dat2_pb5",
  204. "sdmmc3_dat3_pb4",
  205. "sdmmc3_clk_lb_out_pee4",
  206. "sdmmc3_clk_lb_in_pee5";
  207. nvidia,function = "sdmmc3";
  208. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  209. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  210. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  211. };
  212. sdmmc4_clk_pcc4 {
  213. nvidia,pins = "sdmmc4_clk_pcc4";
  214. nvidia,function = "sdmmc4";
  215. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  216. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  217. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  218. };
  219. sdmmc4_cmd_pt7 {
  220. nvidia,pins = "sdmmc4_cmd_pt7",
  221. "sdmmc4_dat0_paa0",
  222. "sdmmc4_dat1_paa1",
  223. "sdmmc4_dat2_paa2",
  224. "sdmmc4_dat3_paa3",
  225. "sdmmc4_dat4_paa4",
  226. "sdmmc4_dat5_paa5",
  227. "sdmmc4_dat6_paa6",
  228. "sdmmc4_dat7_paa7";
  229. nvidia,function = "sdmmc4";
  230. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  231. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  232. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  233. };
  234. pwr_i2c_scl_pz6 {
  235. nvidia,pins = "pwr_i2c_scl_pz6",
  236. "pwr_i2c_sda_pz7";
  237. nvidia,function = "i2cpwr";
  238. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  239. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  240. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  241. nvidia,lock = <TEGRA_PIN_DISABLE>;
  242. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  243. };
  244. jtag_rtck {
  245. nvidia,pins = "jtag_rtck";
  246. nvidia,function = "rtck";
  247. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  248. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  249. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  250. };
  251. clk_32k_in {
  252. nvidia,pins = "clk_32k_in";
  253. nvidia,function = "clk";
  254. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  255. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  256. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  257. };
  258. core_pwr_req {
  259. nvidia,pins = "core_pwr_req";
  260. nvidia,function = "pwron";
  261. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  262. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  263. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  264. };
  265. cpu_pwr_req {
  266. nvidia,pins = "cpu_pwr_req";
  267. nvidia,function = "cpu";
  268. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  269. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  270. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  271. };
  272. pwr_int_n {
  273. nvidia,pins = "pwr_int_n";
  274. nvidia,function = "pmi";
  275. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  276. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  277. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  278. };
  279. reset_out_n {
  280. nvidia,pins = "reset_out_n";
  281. nvidia,function = "reset_out_n";
  282. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  283. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  284. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  285. };
  286. clk3_out_pee0 {
  287. nvidia,pins = "clk3_out_pee0";
  288. nvidia,function = "extperiph3";
  289. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  290. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  291. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  292. };
  293. dap4_din_pp5 {
  294. nvidia,pins = "dap4_din_pp5";
  295. nvidia,function = "i2s3";
  296. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  297. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  298. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  299. };
  300. dap4_dout_pp6 {
  301. nvidia,pins = "dap4_dout_pp6",
  302. "dap4_fs_pp4",
  303. "dap4_sclk_pp7";
  304. nvidia,function = "i2s3";
  305. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  306. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  307. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  308. };
  309. gen1_i2c_sda_pc5 {
  310. nvidia,pins = "gen1_i2c_sda_pc5",
  311. "gen1_i2c_scl_pc4";
  312. nvidia,function = "i2c1";
  313. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  314. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  315. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  316. nvidia,lock = <TEGRA_PIN_DISABLE>;
  317. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  318. };
  319. uart2_cts_n_pj5 {
  320. nvidia,pins = "uart2_cts_n_pj5";
  321. nvidia,function = "uartb";
  322. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  323. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  324. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  325. };
  326. uart2_rts_n_pj6 {
  327. nvidia,pins = "uart2_rts_n_pj6";
  328. nvidia,function = "uartb";
  329. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  330. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  331. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  332. };
  333. uart2_rxd_pc3 {
  334. nvidia,pins = "uart2_rxd_pc3";
  335. nvidia,function = "irda";
  336. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  337. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  338. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  339. };
  340. uart2_txd_pc2 {
  341. nvidia,pins = "uart2_txd_pc2";
  342. nvidia,function = "irda";
  343. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  344. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  345. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  346. };
  347. uart3_cts_n_pa1 {
  348. nvidia,pins = "uart3_cts_n_pa1",
  349. "uart3_rxd_pw7";
  350. nvidia,function = "uartc";
  351. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  352. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  353. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  354. };
  355. uart3_rts_n_pc0 {
  356. nvidia,pins = "uart3_rts_n_pc0",
  357. "uart3_txd_pw6";
  358. nvidia,function = "uartc";
  359. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  360. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  361. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  362. };
  363. hdmi_cec_pee3 {
  364. nvidia,pins = "hdmi_cec_pee3";
  365. nvidia,function = "cec";
  366. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  367. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  368. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  369. nvidia,lock = <TEGRA_PIN_DISABLE>;
  370. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  371. };
  372. hdmi_int_pn7 {
  373. nvidia,pins = "hdmi_int_pn7";
  374. nvidia,function = "rsvd1";
  375. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  376. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  377. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  378. };
  379. ddc_scl_pv4 {
  380. nvidia,pins = "ddc_scl_pv4",
  381. "ddc_sda_pv5";
  382. nvidia,function = "i2c4";
  383. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  384. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  385. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  386. nvidia,lock = <TEGRA_PIN_DISABLE>;
  387. nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
  388. };
  389. pj7 {
  390. nvidia,pins = "pj7",
  391. "pk7";
  392. nvidia,function = "uartd";
  393. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  394. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  395. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  396. };
  397. pb0 {
  398. nvidia,pins = "pb0",
  399. "pb1";
  400. nvidia,function = "uartd";
  401. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  402. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  403. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  404. };
  405. ph0 {
  406. nvidia,pins = "ph0";
  407. nvidia,function = "pwm0";
  408. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  409. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  410. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  411. };
  412. kb_row10_ps2 {
  413. nvidia,pins = "kb_row10_ps2";
  414. nvidia,function = "uarta";
  415. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  416. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  417. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  418. };
  419. kb_row9_ps1 {
  420. nvidia,pins = "kb_row9_ps1";
  421. nvidia,function = "uarta";
  422. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  423. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  424. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  425. };
  426. kb_row6_pr6 {
  427. nvidia,pins = "kb_row6_pr6";
  428. nvidia,function = "displaya_alt";
  429. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  430. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  431. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  432. };
  433. usb_vbus_en0_pn4 {
  434. nvidia,pins = "usb_vbus_en0_pn4",
  435. "usb_vbus_en1_pn5";
  436. nvidia,function = "usb";
  437. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  438. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  439. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  440. nvidia,lock = <TEGRA_PIN_DISABLE>;
  441. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  442. };
  443. drive_sdio1 {
  444. nvidia,pins = "drive_sdio1";
  445. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  446. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  447. nvidia,pull-down-strength = <32>;
  448. nvidia,pull-up-strength = <42>;
  449. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  450. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  451. };
  452. drive_sdio3 {
  453. nvidia,pins = "drive_sdio3";
  454. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  455. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  456. nvidia,pull-down-strength = <20>;
  457. nvidia,pull-up-strength = <36>;
  458. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  459. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  460. };
  461. drive_gma {
  462. nvidia,pins = "drive_gma";
  463. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  464. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  465. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  466. nvidia,pull-down-strength = <1>;
  467. nvidia,pull-up-strength = <2>;
  468. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  469. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  470. nvidia,drive-type = <1>;
  471. };
  472. als_irq_l {
  473. nvidia,pins = "gpio_x3_aud_px3";
  474. nvidia,function = "gmi";
  475. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  476. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  477. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  478. };
  479. codec_irq_l {
  480. nvidia,pins = "ph4";
  481. nvidia,function = "gmi";
  482. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  483. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  484. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  485. };
  486. lcd_bl_en {
  487. nvidia,pins = "ph2";
  488. nvidia,function = "gmi";
  489. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  490. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  491. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  492. };
  493. touch_irq_l {
  494. nvidia,pins = "gpio_w3_aud_pw3";
  495. nvidia,function = "spi6";
  496. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  497. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  498. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  499. };
  500. tpm_davint_l {
  501. nvidia,pins = "ph6";
  502. nvidia,function = "gmi";
  503. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  504. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  505. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  506. };
  507. ts_irq_l {
  508. nvidia,pins = "pk2";
  509. nvidia,function = "gmi";
  510. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  511. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  512. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  513. };
  514. ts_reset_l {
  515. nvidia,pins = "pk4";
  516. nvidia,function = "gmi";
  517. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  518. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  519. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  520. };
  521. ts_shdn_l {
  522. nvidia,pins = "pk1";
  523. nvidia,function = "gmi";
  524. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  525. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  526. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  527. };
  528. ph7 {
  529. nvidia,pins = "ph7";
  530. nvidia,function = "gmi";
  531. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  532. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  533. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  534. };
  535. kb_col0_ap {
  536. nvidia,pins = "kb_col0_pq0";
  537. nvidia,function = "rsvd4";
  538. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  539. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  540. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  541. };
  542. lid_open {
  543. nvidia,pins = "kb_row4_pr4";
  544. nvidia,function = "rsvd3";
  545. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  546. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  547. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  548. };
  549. en_vdd_sd {
  550. nvidia,pins = "kb_row0_pr0";
  551. nvidia,function = "rsvd4";
  552. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  553. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  554. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  555. };
  556. ac_ok {
  557. nvidia,pins = "pj0";
  558. nvidia,function = "gmi";
  559. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  560. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  561. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  562. };
  563. sensor_irq_l {
  564. nvidia,pins = "pi6";
  565. nvidia,function = "gmi";
  566. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  567. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  568. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  569. };
  570. wifi_en {
  571. nvidia,pins = "gpio_x7_aud_px7";
  572. nvidia,function = "rsvd4";
  573. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  574. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  575. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  576. };
  577. wifi_rst_l {
  578. nvidia,pins = "clk2_req_pcc5";
  579. nvidia,function = "dap";
  580. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  581. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  582. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  583. };
  584. hp_det_l {
  585. nvidia,pins = "ulpi_data1_po2";
  586. nvidia,function = "spi3";
  587. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  588. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  589. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  590. };
  591. };
  592. };
  593. serial@70006000 {
  594. status = "okay";
  595. };
  596. pwm@7000a000 {
  597. status = "okay";
  598. };
  599. i2c@7000c000 {
  600. status = "okay";
  601. clock-frequency = <100000>;
  602. acodec: audio-codec@10 {
  603. compatible = "maxim,max98090";
  604. reg = <0x10>;
  605. interrupt-parent = <&gpio>;
  606. interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
  607. };
  608. };
  609. i2c@7000c400 {
  610. status = "okay";
  611. clock-frequency = <100000>;
  612. trackpad@4b {
  613. compatible = "atmel,maxtouch";
  614. reg = <0x4b>;
  615. interrupt-parent = <&gpio>;
  616. interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
  617. linux,gpio-keymap = <0 0 0 BTN_LEFT>;
  618. };
  619. };
  620. i2c@7000c500 {
  621. status = "okay";
  622. clock-frequency = <100000>;
  623. };
  624. hdmi_ddc: i2c@7000c700 {
  625. status = "okay";
  626. clock-frequency = <100000>;
  627. };
  628. i2c@7000d000 {
  629. status = "okay";
  630. clock-frequency = <400000>;
  631. pmic: pmic@40 {
  632. compatible = "ams,as3722";
  633. reg = <0x40>;
  634. interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
  635. ams,system-power-controller;
  636. #interrupt-cells = <2>;
  637. interrupt-controller;
  638. gpio-controller;
  639. #gpio-cells = <2>;
  640. pinctrl-names = "default";
  641. pinctrl-0 = <&as3722_default>;
  642. as3722_default: pinmux {
  643. gpio0 {
  644. pins = "gpio0";
  645. function = "gpio";
  646. bias-pull-down;
  647. };
  648. gpio1_2_4_7 {
  649. pins = "gpio1", "gpio2", "gpio4", "gpio7";
  650. function = "gpio";
  651. bias-pull-up;
  652. };
  653. gpio3_6 {
  654. pins = "gpio3", "gpio6";
  655. bias-high-impedance;
  656. };
  657. gpio5 {
  658. pins = "gpio5";
  659. function = "clk32k-out";
  660. };
  661. };
  662. regulators {
  663. vsup-sd2-supply = <&vdd_5v0_sys>;
  664. vsup-sd3-supply = <&vdd_5v0_sys>;
  665. vsup-sd4-supply = <&vdd_5v0_sys>;
  666. vsup-sd5-supply = <&vdd_5v0_sys>;
  667. vin-ldo0-supply = <&vdd_1v35_lp0>;
  668. vin-ldo1-6-supply = <&vdd_3v3_run>;
  669. vin-ldo2-5-7-supply = <&vddio_1v8>;
  670. vin-ldo3-4-supply = <&vdd_3v3_sys>;
  671. vin-ldo9-10-supply = <&vdd_5v0_sys>;
  672. vin-ldo11-supply = <&vdd_3v3_run>;
  673. sd0 {
  674. regulator-name = "+VDD_CPU_AP";
  675. regulator-min-microvolt = <700000>;
  676. regulator-max-microvolt = <1400000>;
  677. regulator-min-microamp = <3500000>;
  678. regulator-max-microamp = <3500000>;
  679. regulator-always-on;
  680. regulator-boot-on;
  681. ams,ext-control = <2>;
  682. };
  683. sd1 {
  684. regulator-name = "+VDD_CORE";
  685. regulator-min-microvolt = <700000>;
  686. regulator-max-microvolt = <1350000>;
  687. regulator-min-microamp = <2500000>;
  688. regulator-max-microamp = <2500000>;
  689. regulator-always-on;
  690. regulator-boot-on;
  691. ams,ext-control = <1>;
  692. };
  693. vdd_1v35_lp0: sd2 {
  694. regulator-name = "+1.35V_LP0(sd2)";
  695. regulator-min-microvolt = <1350000>;
  696. regulator-max-microvolt = <1350000>;
  697. regulator-always-on;
  698. regulator-boot-on;
  699. };
  700. sd3 {
  701. regulator-name = "+1.35V_LP0(sd3)";
  702. regulator-min-microvolt = <1350000>;
  703. regulator-max-microvolt = <1350000>;
  704. regulator-always-on;
  705. regulator-boot-on;
  706. };
  707. vdd_1v05_run: sd4 {
  708. regulator-name = "+1.05V_RUN";
  709. regulator-min-microvolt = <1050000>;
  710. regulator-max-microvolt = <1050000>;
  711. };
  712. vddio_1v8: sd5 {
  713. regulator-name = "+1.8V_VDDIO";
  714. regulator-min-microvolt = <1800000>;
  715. regulator-max-microvolt = <1800000>;
  716. regulator-boot-on;
  717. regulator-always-on;
  718. };
  719. vdd_gpu: sd6 {
  720. regulator-name = "+VDD_GPU_AP";
  721. regulator-min-microvolt = <650000>;
  722. regulator-max-microvolt = <1200000>;
  723. regulator-min-microamp = <3500000>;
  724. regulator-max-microamp = <3500000>;
  725. regulator-boot-on;
  726. regulator-always-on;
  727. };
  728. avdd_1v05_run: ldo0 {
  729. regulator-name = "+1.05V_RUN_AVDD";
  730. regulator-min-microvolt = <1050000>;
  731. regulator-max-microvolt = <1050000>;
  732. regulator-boot-on;
  733. regulator-always-on;
  734. ams,ext-control = <1>;
  735. };
  736. ldo1 {
  737. regulator-name = "+1.8V_RUN_CAM";
  738. regulator-min-microvolt = <1800000>;
  739. regulator-max-microvolt = <1800000>;
  740. };
  741. ldo2 {
  742. regulator-name = "+1.2V_GEN_AVDD";
  743. regulator-min-microvolt = <1200000>;
  744. regulator-max-microvolt = <1200000>;
  745. regulator-boot-on;
  746. regulator-always-on;
  747. };
  748. ldo3 {
  749. regulator-name = "+1.00V_LP0_VDD_RTC";
  750. regulator-min-microvolt = <1000000>;
  751. regulator-max-microvolt = <1000000>;
  752. regulator-boot-on;
  753. regulator-always-on;
  754. ams,enable-tracking;
  755. };
  756. vdd_run_cam: ldo4 {
  757. regulator-name = "+3.3V_RUN_CAM";
  758. regulator-min-microvolt = <2800000>;
  759. regulator-max-microvolt = <2800000>;
  760. };
  761. ldo5 {
  762. regulator-name = "+1.2V_RUN_CAM_FRONT";
  763. regulator-min-microvolt = <1200000>;
  764. regulator-max-microvolt = <1200000>;
  765. };
  766. vddio_sdmmc3: ldo6 {
  767. regulator-name = "+VDDIO_SDMMC3";
  768. regulator-min-microvolt = <1800000>;
  769. regulator-max-microvolt = <3300000>;
  770. };
  771. ldo7 {
  772. regulator-name = "+1.05V_RUN_CAM_REAR";
  773. regulator-min-microvolt = <1050000>;
  774. regulator-max-microvolt = <1050000>;
  775. };
  776. ldo9 {
  777. regulator-name = "+2.8V_RUN_TOUCH";
  778. regulator-min-microvolt = <2800000>;
  779. regulator-max-microvolt = <2800000>;
  780. };
  781. ldo10 {
  782. regulator-name = "+2.8V_RUN_CAM_AF";
  783. regulator-min-microvolt = <2800000>;
  784. regulator-max-microvolt = <2800000>;
  785. };
  786. ldo11 {
  787. regulator-name = "+1.8V_RUN_VPP_FUSE";
  788. regulator-min-microvolt = <1800000>;
  789. regulator-max-microvolt = <1800000>;
  790. };
  791. };
  792. };
  793. };
  794. spi@7000d400 {
  795. status = "okay";
  796. cros_ec: cros-ec@0 {
  797. compatible = "google,cros-ec-spi";
  798. spi-max-frequency = <4000000>;
  799. interrupt-parent = <&gpio>;
  800. interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
  801. reg = <0>;
  802. google,cros-ec-spi-msg-delay = <2000>;
  803. i2c-tunnel {
  804. compatible = "google,cros-ec-i2c-tunnel";
  805. #address-cells = <1>;
  806. #size-cells = <0>;
  807. google,remote-bus = <0>;
  808. charger: bq24735@9 {
  809. compatible = "ti,bq24735";
  810. reg = <0x9>;
  811. interrupt-parent = <&gpio>;
  812. interrupts = <TEGRA_GPIO(J, 0)
  813. IRQ_TYPE_EDGE_BOTH>;
  814. ti,ac-detect-gpios = <&gpio
  815. TEGRA_GPIO(J, 0)
  816. GPIO_ACTIVE_HIGH>;
  817. };
  818. battery: sbs-battery@b {
  819. compatible = "sbs,sbs-battery";
  820. reg = <0xb>;
  821. sbs,i2c-retry-count = <2>;
  822. sbs,poll-retry-count = <1>;
  823. };
  824. };
  825. };
  826. };
  827. spi@7000da00 {
  828. status = "okay";
  829. spi-max-frequency = <25000000>;
  830. flash@0 {
  831. compatible = "winbond,w25q32dw", "jedec,spi-nor";
  832. reg = <0>;
  833. spi-max-frequency = <20000000>;
  834. };
  835. };
  836. pmc@7000e400 {
  837. nvidia,invert-interrupt;
  838. nvidia,suspend-mode = <1>;
  839. nvidia,cpu-pwr-good-time = <500>;
  840. nvidia,cpu-pwr-off-time = <300>;
  841. nvidia,core-pwr-good-time = <641 3845>;
  842. nvidia,core-pwr-off-time = <61036>;
  843. nvidia,core-power-req-active-high;
  844. nvidia,sys-clock-req-active-high;
  845. };
  846. hda@70030000 {
  847. status = "okay";
  848. };
  849. usb@70090000 {
  850. phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
  851. <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
  852. <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
  853. <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
  854. <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
  855. phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
  856. avddio-pex-supply = <&vdd_1v05_run>;
  857. dvddio-pex-supply = <&vdd_1v05_run>;
  858. avdd-usb-supply = <&vdd_3v3_lp0>;
  859. avdd-pll-utmip-supply = <&vddio_1v8>;
  860. avdd-pll-erefe-supply = <&avdd_1v05_run>;
  861. avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
  862. hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
  863. hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
  864. status = "okay";
  865. };
  866. padctl@7009f000 {
  867. avdd-pll-utmip-supply = <&vddio_1v8>;
  868. avdd-pll-erefe-supply = <&avdd_1v05_run>;
  869. avdd-pex-pll-supply = <&vdd_1v05_run>;
  870. hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
  871. pads {
  872. usb2 {
  873. status = "okay";
  874. lanes {
  875. usb2-0 {
  876. nvidia,function = "xusb";
  877. status = "okay";
  878. };
  879. usb2-1 {
  880. nvidia,function = "xusb";
  881. status = "okay";
  882. };
  883. usb2-2 {
  884. nvidia,function = "xusb";
  885. status = "okay";
  886. };
  887. };
  888. };
  889. pcie {
  890. status = "okay";
  891. lanes {
  892. pcie-0 {
  893. nvidia,function = "usb3-ss";
  894. status = "okay";
  895. };
  896. pcie-1 {
  897. nvidia,function = "usb3-ss";
  898. status = "okay";
  899. };
  900. };
  901. };
  902. };
  903. ports {
  904. usb2-0 {
  905. status = "okay";
  906. mode = "otg";
  907. usb-role-switch;
  908. vbus-supply = <&vdd_usb1_vbus>;
  909. };
  910. usb2-1 {
  911. status = "okay";
  912. mode = "host";
  913. vbus-supply = <&vdd_run_cam>;
  914. };
  915. usb2-2 {
  916. status = "okay";
  917. mode = "host";
  918. vbus-supply = <&vdd_usb3_vbus>;
  919. };
  920. usb3-0 {
  921. nvidia,usb2-companion = <0>;
  922. status = "okay";
  923. };
  924. usb3-1 {
  925. nvidia,usb2-companion = <2>;
  926. status = "okay";
  927. };
  928. };
  929. };
  930. mmc@700b0400 {
  931. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
  932. power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
  933. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
  934. status = "okay";
  935. bus-width = <4>;
  936. vqmmc-supply = <&vddio_sdmmc3>;
  937. };
  938. mmc@700b0600 {
  939. status = "okay";
  940. bus-width = <8>;
  941. non-removable;
  942. };
  943. ahub@70300000 {
  944. i2s@70301100 {
  945. status = "okay";
  946. };
  947. };
  948. usb@7d000000 {
  949. status = "okay";
  950. };
  951. usb-phy@7d000000 {
  952. status = "okay";
  953. vbus-supply = <&vdd_usb1_vbus>;
  954. };
  955. usb@7d004000 {
  956. status = "okay";
  957. };
  958. usb-phy@7d004000 {
  959. status = "okay";
  960. vbus-supply = <&vdd_run_cam>;
  961. };
  962. usb@7d008000 {
  963. status = "okay";
  964. };
  965. usb-phy@7d008000 {
  966. status = "okay";
  967. vbus-supply = <&vdd_usb3_vbus>;
  968. };
  969. backlight: backlight {
  970. compatible = "pwm-backlight";
  971. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  972. power-supply = <&vdd_led>;
  973. pwms = <&pwm 1 1000000>;
  974. brightness-levels = <0 4 8 16 32 64 128 255>;
  975. default-brightness-level = <6>;
  976. };
  977. clk32k_in: clock-32k {
  978. compatible = "fixed-clock";
  979. clock-frequency = <32768>;
  980. #clock-cells = <0>;
  981. };
  982. gpio-keys {
  983. compatible = "gpio-keys";
  984. key-power {
  985. label = "Power";
  986. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  987. linux,code = <KEY_POWER>;
  988. debounce-interval = <10>;
  989. wakeup-source;
  990. };
  991. };
  992. vdd_mux: regulator-mux {
  993. compatible = "regulator-fixed";
  994. regulator-name = "+VDD_MUX";
  995. regulator-min-microvolt = <12000000>;
  996. regulator-max-microvolt = <12000000>;
  997. regulator-always-on;
  998. regulator-boot-on;
  999. };
  1000. vdd_5v0_sys: regulator-5v0sys {
  1001. compatible = "regulator-fixed";
  1002. regulator-name = "+5V_SYS";
  1003. regulator-min-microvolt = <5000000>;
  1004. regulator-max-microvolt = <5000000>;
  1005. regulator-always-on;
  1006. regulator-boot-on;
  1007. vin-supply = <&vdd_mux>;
  1008. };
  1009. vdd_3v3_sys: regulator-3v3sys {
  1010. compatible = "regulator-fixed";
  1011. regulator-name = "+3.3V_SYS";
  1012. regulator-min-microvolt = <3300000>;
  1013. regulator-max-microvolt = <3300000>;
  1014. regulator-always-on;
  1015. regulator-boot-on;
  1016. vin-supply = <&vdd_mux>;
  1017. };
  1018. vdd_3v3_run: regulator-3v3run {
  1019. compatible = "regulator-fixed";
  1020. regulator-name = "+3.3V_RUN";
  1021. regulator-min-microvolt = <3300000>;
  1022. regulator-max-microvolt = <3300000>;
  1023. regulator-always-on;
  1024. regulator-boot-on;
  1025. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  1026. enable-active-high;
  1027. vin-supply = <&vdd_3v3_sys>;
  1028. };
  1029. vdd_3v3_hdmi: regulator-hdmi {
  1030. compatible = "regulator-fixed";
  1031. regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
  1032. regulator-min-microvolt = <3300000>;
  1033. regulator-max-microvolt = <3300000>;
  1034. vin-supply = <&vdd_3v3_run>;
  1035. };
  1036. vdd_led: regulator-led {
  1037. compatible = "regulator-fixed";
  1038. regulator-name = "+VDD_LED";
  1039. regulator-min-microvolt = <3300000>;
  1040. regulator-max-microvolt = <3300000>;
  1041. gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  1042. enable-active-high;
  1043. vin-supply = <&vdd_mux>;
  1044. };
  1045. vdd_5v0_ts: regulator-ts {
  1046. compatible = "regulator-fixed";
  1047. regulator-name = "+5V_VDD_TS_SW";
  1048. regulator-min-microvolt = <5000000>;
  1049. regulator-max-microvolt = <5000000>;
  1050. regulator-boot-on;
  1051. gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
  1052. enable-active-high;
  1053. vin-supply = <&vdd_5v0_sys>;
  1054. };
  1055. vdd_usb1_vbus: regulator-usb1 {
  1056. compatible = "regulator-fixed";
  1057. regulator-name = "+5V_USB_HS";
  1058. regulator-min-microvolt = <5000000>;
  1059. regulator-max-microvolt = <5000000>;
  1060. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  1061. enable-active-high;
  1062. gpio-open-drain;
  1063. vin-supply = <&vdd_5v0_sys>;
  1064. };
  1065. vdd_usb3_vbus: regulator-usb3 {
  1066. compatible = "regulator-fixed";
  1067. regulator-name = "+5V_USB_SS";
  1068. regulator-min-microvolt = <5000000>;
  1069. regulator-max-microvolt = <5000000>;
  1070. gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
  1071. enable-active-high;
  1072. gpio-open-drain;
  1073. vin-supply = <&vdd_5v0_sys>;
  1074. };
  1075. vdd_3v3_panel: regulator-panel {
  1076. compatible = "regulator-fixed";
  1077. regulator-name = "+3.3V_PANEL";
  1078. regulator-min-microvolt = <3300000>;
  1079. regulator-max-microvolt = <3300000>;
  1080. gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
  1081. enable-active-high;
  1082. vin-supply = <&vdd_3v3_run>;
  1083. };
  1084. vdd_3v3_lp0: regulator-lp0 {
  1085. compatible = "regulator-fixed";
  1086. regulator-name = "+3.3V_LP0";
  1087. regulator-min-microvolt = <3300000>;
  1088. regulator-max-microvolt = <3300000>;
  1089. /*
  1090. * TODO: find a way to wire this up with the USB EHCI
  1091. * controllers so that it can be enabled on demand.
  1092. */
  1093. regulator-always-on;
  1094. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  1095. enable-active-high;
  1096. vin-supply = <&vdd_3v3_sys>;
  1097. };
  1098. vdd_hdmi_pll: regulator-hdmipll {
  1099. compatible = "regulator-fixed";
  1100. regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
  1101. regulator-min-microvolt = <1050000>;
  1102. regulator-max-microvolt = <1050000>;
  1103. gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
  1104. vin-supply = <&vdd_1v05_run>;
  1105. };
  1106. vdd_5v0_hdmi: regulator-hdmicon {
  1107. compatible = "regulator-fixed";
  1108. regulator-name = "+5V_HDMI_CON";
  1109. regulator-min-microvolt = <5000000>;
  1110. regulator-max-microvolt = <5000000>;
  1111. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  1112. enable-active-high;
  1113. vin-supply = <&vdd_5v0_sys>;
  1114. };
  1115. sound {
  1116. compatible = "nvidia,tegra-audio-max98090-venice2",
  1117. "nvidia,tegra-audio-max98090";
  1118. nvidia,model = "NVIDIA Tegra Venice2";
  1119. nvidia,audio-routing =
  1120. "Headphones", "HPR",
  1121. "Headphones", "HPL",
  1122. "Speakers", "SPKR",
  1123. "Speakers", "SPKL",
  1124. "Mic Jack", "MICBIAS",
  1125. "IN34", "Mic Jack";
  1126. nvidia,i2s-controller = <&tegra_i2s1>;
  1127. nvidia,audio-codec = <&acodec>;
  1128. clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
  1129. <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1130. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1131. clock-names = "pll_a", "pll_a_out0", "mclk";
  1132. assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
  1133. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1134. assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1135. <&tegra_car TEGRA124_CLK_EXTERN1>;
  1136. };
  1137. };
  1138. #include "cros-ec-keyboard.dtsi"