tegra124-apalis.dtsi 57 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR X11
  2. /*
  3. * Copyright 2016-2019 Toradex AG
  4. */
  5. #include "tegra124.dtsi"
  6. #include "tegra124-apalis-emc.dtsi"
  7. /*
  8. * Toradex Apalis TK1 Module Device Tree
  9. * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
  10. */
  11. / {
  12. memory@80000000 {
  13. reg = <0x0 0x80000000 0x0 0x80000000>;
  14. };
  15. pcie@1003000 {
  16. status = "okay";
  17. avddio-pex-supply = <&reg_1v05_vdd>;
  18. avdd-pex-pll-supply = <&reg_1v05_vdd>;
  19. avdd-pll-erefe-supply = <&reg_1v05_avdd>;
  20. dvddio-pex-supply = <&reg_1v05_vdd>;
  21. hvdd-pex-pll-e-supply = <&reg_module_3v3>;
  22. hvdd-pex-supply = <&reg_module_3v3>;
  23. vddio-pex-ctl-supply = <&reg_module_3v3>;
  24. /* Apalis PCIe (additional lane Apalis type specific) */
  25. pci@1,0 {
  26. /* PCIE1_RX/TX and TS_DIFF1/2 */
  27. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
  28. <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
  29. phy-names = "pcie-0", "pcie-1";
  30. };
  31. /* I210 Gigabit Ethernet Controller (On-module) */
  32. pci@2,0 {
  33. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
  34. phy-names = "pcie-0";
  35. status = "okay";
  36. ethernet@0,0 {
  37. reg = <0 0 0 0 0>;
  38. local-mac-address = [00 00 00 00 00 00];
  39. };
  40. };
  41. };
  42. host1x@50000000 {
  43. hdmi@54280000 {
  44. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  45. nvidia,hpd-gpio =
  46. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  47. pll-supply = <&reg_1v05_avdd_hdmi_pll>;
  48. vdd-supply = <&reg_3v3_avdd_hdmi>;
  49. };
  50. };
  51. gpu@57000000 {
  52. /*
  53. * Node left disabled on purpose - the bootloader will enable
  54. * it after having set the VPR up
  55. */
  56. vdd-supply = <&reg_vdd_gpu>;
  57. };
  58. pinmux@70000868 {
  59. pinctrl-names = "default";
  60. pinctrl-0 = <&state_default>;
  61. state_default: pinmux {
  62. /* Analogue Audio (On-module) */
  63. dap3-fs-pp0 {
  64. nvidia,pins = "dap3_fs_pp0";
  65. nvidia,function = "i2s2";
  66. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  67. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  68. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  69. };
  70. dap3-din-pp1 {
  71. nvidia,pins = "dap3_din_pp1";
  72. nvidia,function = "i2s2";
  73. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  74. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  75. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  76. };
  77. dap3-dout-pp2 {
  78. nvidia,pins = "dap3_dout_pp2";
  79. nvidia,function = "i2s2";
  80. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  81. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  82. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  83. };
  84. dap3-sclk-pp3 {
  85. nvidia,pins = "dap3_sclk_pp3";
  86. nvidia,function = "i2s2";
  87. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  88. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  89. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  90. };
  91. dap-mclk1-pw4 {
  92. nvidia,pins = "dap_mclk1_pw4";
  93. nvidia,function = "extperiph1";
  94. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  95. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  96. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  97. };
  98. /* Apalis BKL1_ON */
  99. pbb5 {
  100. nvidia,pins = "pbb5";
  101. nvidia,function = "vgp5";
  102. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  103. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  104. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  105. };
  106. /* Apalis BKL1_PWM */
  107. pu6 {
  108. nvidia,pins = "pu6";
  109. nvidia,function = "pwm3";
  110. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  111. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  112. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  113. };
  114. /* Apalis CAM1_MCLK */
  115. cam-mclk-pcc0 {
  116. nvidia,pins = "cam_mclk_pcc0";
  117. nvidia,function = "vi_alt3";
  118. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  119. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  120. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  121. };
  122. /* Apalis Digital Audio */
  123. dap2-fs-pa2 {
  124. nvidia,pins = "dap2_fs_pa2";
  125. nvidia,function = "hda";
  126. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  127. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  128. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  129. };
  130. dap2-sclk-pa3 {
  131. nvidia,pins = "dap2_sclk_pa3";
  132. nvidia,function = "hda";
  133. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  134. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  135. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  136. };
  137. dap2-din-pa4 {
  138. nvidia,pins = "dap2_din_pa4";
  139. nvidia,function = "hda";
  140. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  141. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  142. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  143. };
  144. dap2-dout-pa5 {
  145. nvidia,pins = "dap2_dout_pa5";
  146. nvidia,function = "hda";
  147. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  148. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  149. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  150. };
  151. pbb3 { /* DAP1_RESET */
  152. nvidia,pins = "pbb3";
  153. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  154. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  155. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  156. };
  157. clk3-out-pee0 {
  158. nvidia,pins = "clk3_out_pee0";
  159. nvidia,function = "extperiph3";
  160. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  161. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  162. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  163. };
  164. /* Apalis GPIO */
  165. ddc-scl-pv4 {
  166. nvidia,pins = "ddc_scl_pv4";
  167. nvidia,function = "rsvd2";
  168. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  169. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  170. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  171. };
  172. ddc-sda-pv5 {
  173. nvidia,pins = "ddc_sda_pv5";
  174. nvidia,function = "rsvd2";
  175. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  176. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  177. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  178. };
  179. pex-l0-rst-n-pdd1 {
  180. nvidia,pins = "pex_l0_rst_n_pdd1";
  181. nvidia,function = "rsvd2";
  182. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  183. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  184. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  185. };
  186. pex-l0-clkreq-n-pdd2 {
  187. nvidia,pins = "pex_l0_clkreq_n_pdd2";
  188. nvidia,function = "rsvd2";
  189. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  190. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  191. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  192. };
  193. pex-l1-rst-n-pdd5 {
  194. nvidia,pins = "pex_l1_rst_n_pdd5";
  195. nvidia,function = "rsvd2";
  196. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  197. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  198. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  199. };
  200. pex-l1-clkreq-n-pdd6 {
  201. nvidia,pins = "pex_l1_clkreq_n_pdd6";
  202. nvidia,function = "rsvd2";
  203. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  204. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  205. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  206. };
  207. dp-hpd-pff0 {
  208. nvidia,pins = "dp_hpd_pff0";
  209. nvidia,function = "dp";
  210. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  211. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  212. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  213. };
  214. pff2 {
  215. nvidia,pins = "pff2";
  216. nvidia,function = "rsvd2";
  217. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  218. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  219. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  220. };
  221. owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
  222. nvidia,pins = "owr";
  223. nvidia,function = "rsvd2";
  224. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  225. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  226. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  227. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  228. };
  229. /* Apalis HDMI1_CEC */
  230. hdmi-cec-pee3 {
  231. nvidia,pins = "hdmi_cec_pee3";
  232. nvidia,function = "cec";
  233. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  234. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  235. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  236. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  237. };
  238. /* Apalis HDMI1_HPD */
  239. hdmi-int-pn7 {
  240. nvidia,pins = "hdmi_int_pn7";
  241. nvidia,function = "rsvd1";
  242. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  243. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  244. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  245. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  246. };
  247. /* Apalis I2C1 */
  248. gen1-i2c-scl-pc4 {
  249. nvidia,pins = "gen1_i2c_scl_pc4";
  250. nvidia,function = "i2c1";
  251. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  252. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  253. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  254. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  255. };
  256. gen1-i2c-sda-pc5 {
  257. nvidia,pins = "gen1_i2c_sda_pc5";
  258. nvidia,function = "i2c1";
  259. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  260. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  261. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  262. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  263. };
  264. /* Apalis I2C2 (DDC) */
  265. gen2-i2c-scl-pt5 {
  266. nvidia,pins = "gen2_i2c_scl_pt5";
  267. nvidia,function = "i2c2";
  268. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  269. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  270. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  271. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  272. };
  273. gen2-i2c-sda-pt6 {
  274. nvidia,pins = "gen2_i2c_sda_pt6";
  275. nvidia,function = "i2c2";
  276. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  277. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  278. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  279. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  280. };
  281. /* Apalis I2C3 (CAM) */
  282. cam-i2c-scl-pbb1 {
  283. nvidia,pins = "cam_i2c_scl_pbb1";
  284. nvidia,function = "i2c3";
  285. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  286. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  287. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  288. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  289. };
  290. cam-i2c-sda-pbb2 {
  291. nvidia,pins = "cam_i2c_sda_pbb2";
  292. nvidia,function = "i2c3";
  293. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  294. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  295. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  296. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  297. };
  298. /* Apalis MMC1 */
  299. sdmmc1-cd-n-pv3 { /* CD# GPIO */
  300. nvidia,pins = "sdmmc1_wp_n_pv3";
  301. nvidia,function = "sdmmc1";
  302. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  303. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  304. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  305. };
  306. clk2-out-pw5 { /* D5 GPIO */
  307. nvidia,pins = "clk2_out_pw5";
  308. nvidia,function = "rsvd2";
  309. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  310. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  311. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  312. };
  313. sdmmc1-dat3-py4 {
  314. nvidia,pins = "sdmmc1_dat3_py4";
  315. nvidia,function = "sdmmc1";
  316. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  317. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  318. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  319. };
  320. sdmmc1-dat2-py5 {
  321. nvidia,pins = "sdmmc1_dat2_py5";
  322. nvidia,function = "sdmmc1";
  323. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  324. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  325. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  326. };
  327. sdmmc1-dat1-py6 {
  328. nvidia,pins = "sdmmc1_dat1_py6";
  329. nvidia,function = "sdmmc1";
  330. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  331. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  332. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  333. };
  334. sdmmc1-dat0-py7 {
  335. nvidia,pins = "sdmmc1_dat0_py7";
  336. nvidia,function = "sdmmc1";
  337. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  338. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  339. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  340. };
  341. sdmmc1-clk-pz0 {
  342. nvidia,pins = "sdmmc1_clk_pz0";
  343. nvidia,function = "sdmmc1";
  344. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  345. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  346. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  347. };
  348. sdmmc1-cmd-pz1 {
  349. nvidia,pins = "sdmmc1_cmd_pz1";
  350. nvidia,function = "sdmmc1";
  351. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  352. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  353. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  354. };
  355. clk2-req-pcc5 { /* D4 GPIO */
  356. nvidia,pins = "clk2_req_pcc5";
  357. nvidia,function = "rsvd2";
  358. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  359. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  360. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  361. };
  362. sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
  363. nvidia,pins = "sdmmc3_clk_lb_in_pee5";
  364. nvidia,function = "rsvd2";
  365. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  366. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  367. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  368. };
  369. usb-vbus-en2-pff1 { /* D7 GPIO */
  370. nvidia,pins = "usb_vbus_en2_pff1";
  371. nvidia,function = "rsvd2";
  372. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  373. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  374. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  375. };
  376. /* Apalis PWM */
  377. ph0 {
  378. nvidia,pins = "ph0";
  379. nvidia,function = "pwm0";
  380. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  381. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  382. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  383. };
  384. ph1 {
  385. nvidia,pins = "ph1";
  386. nvidia,function = "pwm1";
  387. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  388. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  389. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  390. };
  391. ph2 {
  392. nvidia,pins = "ph2";
  393. nvidia,function = "pwm2";
  394. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  395. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  396. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  397. };
  398. /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
  399. ph3 {
  400. nvidia,pins = "ph3";
  401. nvidia,function = "pwm3";
  402. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  403. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  404. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  405. };
  406. /* Apalis SATA1_ACT# */
  407. dap1-dout-pn2 {
  408. nvidia,pins = "dap1_dout_pn2";
  409. nvidia,function = "gmi";
  410. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  411. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  412. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  413. };
  414. /* Apalis SD1 */
  415. sdmmc3-clk-pa6 {
  416. nvidia,pins = "sdmmc3_clk_pa6";
  417. nvidia,function = "sdmmc3";
  418. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  419. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  420. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  421. };
  422. sdmmc3-cmd-pa7 {
  423. nvidia,pins = "sdmmc3_cmd_pa7";
  424. nvidia,function = "sdmmc3";
  425. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  426. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  427. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  428. };
  429. sdmmc3-dat3-pb4 {
  430. nvidia,pins = "sdmmc3_dat3_pb4";
  431. nvidia,function = "sdmmc3";
  432. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  433. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  434. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  435. };
  436. sdmmc3-dat2-pb5 {
  437. nvidia,pins = "sdmmc3_dat2_pb5";
  438. nvidia,function = "sdmmc3";
  439. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  440. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  441. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  442. };
  443. sdmmc3-dat1-pb6 {
  444. nvidia,pins = "sdmmc3_dat1_pb6";
  445. nvidia,function = "sdmmc3";
  446. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  447. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  448. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  449. };
  450. sdmmc3-dat0-pb7 {
  451. nvidia,pins = "sdmmc3_dat0_pb7";
  452. nvidia,function = "sdmmc3";
  453. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  454. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  455. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  456. };
  457. sdmmc3-cd-n-pv2 { /* CD# GPIO */
  458. nvidia,pins = "sdmmc3_cd_n_pv2";
  459. nvidia,function = "rsvd3";
  460. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  461. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  462. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  463. };
  464. /* Apalis SPDIF */
  465. spdif-out-pk5 {
  466. nvidia,pins = "spdif_out_pk5";
  467. nvidia,function = "spdif";
  468. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  469. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  470. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  471. };
  472. spdif-in-pk6 {
  473. nvidia,pins = "spdif_in_pk6";
  474. nvidia,function = "spdif";
  475. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  476. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  477. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  478. };
  479. /* Apalis SPI1 */
  480. ulpi-clk-py0 {
  481. nvidia,pins = "ulpi_clk_py0";
  482. nvidia,function = "spi1";
  483. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  484. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  485. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  486. };
  487. ulpi-dir-py1 {
  488. nvidia,pins = "ulpi_dir_py1";
  489. nvidia,function = "spi1";
  490. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  491. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  492. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  493. };
  494. ulpi-nxt-py2 {
  495. nvidia,pins = "ulpi_nxt_py2";
  496. nvidia,function = "spi1";
  497. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  498. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  499. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  500. };
  501. ulpi-stp-py3 {
  502. nvidia,pins = "ulpi_stp_py3";
  503. nvidia,function = "spi1";
  504. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  505. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  506. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  507. };
  508. /* Apalis SPI2 */
  509. pg5 {
  510. nvidia,pins = "pg5";
  511. nvidia,function = "spi4";
  512. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  513. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  514. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  515. };
  516. pg6 {
  517. nvidia,pins = "pg6";
  518. nvidia,function = "spi4";
  519. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  520. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  521. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  522. };
  523. pg7 {
  524. nvidia,pins = "pg7";
  525. nvidia,function = "spi4";
  526. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  527. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  528. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  529. };
  530. pi3 {
  531. nvidia,pins = "pi3";
  532. nvidia,function = "spi4";
  533. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  534. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  535. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  536. };
  537. /* Apalis UART1 */
  538. pb1 { /* DCD GPIO */
  539. nvidia,pins = "pb1";
  540. nvidia,function = "rsvd2";
  541. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  542. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  543. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  544. };
  545. pk7 { /* RI GPIO */
  546. nvidia,pins = "pk7";
  547. nvidia,function = "rsvd2";
  548. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  549. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  550. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  551. };
  552. uart1-txd-pu0 {
  553. nvidia,pins = "pu0";
  554. nvidia,function = "uarta";
  555. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  556. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  557. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  558. };
  559. uart1-rxd-pu1 {
  560. nvidia,pins = "pu1";
  561. nvidia,function = "uarta";
  562. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  563. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  564. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  565. };
  566. uart1-cts-n-pu2 {
  567. nvidia,pins = "pu2";
  568. nvidia,function = "uarta";
  569. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  570. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  571. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  572. };
  573. uart1-rts-n-pu3 {
  574. nvidia,pins = "pu3";
  575. nvidia,function = "uarta";
  576. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  577. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  578. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  579. };
  580. uart3-cts-n-pa1 { /* DSR GPIO */
  581. nvidia,pins = "uart3_cts_n_pa1";
  582. nvidia,function = "gmi";
  583. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  584. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  585. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  586. };
  587. uart3-rts-n-pc0 { /* DTR GPIO */
  588. nvidia,pins = "uart3_rts_n_pc0";
  589. nvidia,function = "gmi";
  590. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  591. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  592. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  593. };
  594. /* Apalis UART2 */
  595. uart2-txd-pc2 {
  596. nvidia,pins = "uart2_txd_pc2";
  597. nvidia,function = "irda";
  598. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  599. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  600. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  601. };
  602. uart2-rxd-pc3 {
  603. nvidia,pins = "uart2_rxd_pc3";
  604. nvidia,function = "irda";
  605. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  606. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  607. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  608. };
  609. uart2-cts-n-pj5 {
  610. nvidia,pins = "uart2_cts_n_pj5";
  611. nvidia,function = "uartb";
  612. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  613. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  614. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  615. };
  616. uart2-rts-n-pj6 {
  617. nvidia,pins = "uart2_rts_n_pj6";
  618. nvidia,function = "uartb";
  619. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  620. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  621. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  622. };
  623. /* Apalis UART3 */
  624. uart3-txd-pw6 {
  625. nvidia,pins = "uart3_txd_pw6";
  626. nvidia,function = "uartc";
  627. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  628. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  629. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  630. };
  631. uart3-rxd-pw7 {
  632. nvidia,pins = "uart3_rxd_pw7";
  633. nvidia,function = "uartc";
  634. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  635. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  636. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  637. };
  638. /* Apalis UART4 */
  639. uart4-rxd-pb0 {
  640. nvidia,pins = "pb0";
  641. nvidia,function = "uartd";
  642. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  643. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  644. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  645. };
  646. uart4-txd-pj7 {
  647. nvidia,pins = "pj7";
  648. nvidia,function = "uartd";
  649. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  650. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  651. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  652. };
  653. /* Apalis USBH_EN */
  654. usb-vbus-en1-pn5 {
  655. nvidia,pins = "usb_vbus_en1_pn5";
  656. nvidia,function = "rsvd2";
  657. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  658. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  659. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  660. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  661. };
  662. /* Apalis USBH_OC# */
  663. pbb0 {
  664. nvidia,pins = "pbb0";
  665. nvidia,function = "vgp6";
  666. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  667. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  668. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  669. };
  670. /* Apalis USBO1_EN */
  671. usb-vbus-en0-pn4 {
  672. nvidia,pins = "usb_vbus_en0_pn4";
  673. nvidia,function = "rsvd2";
  674. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  675. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  676. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  677. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  678. };
  679. /* Apalis USBO1_OC# */
  680. pbb4 {
  681. nvidia,pins = "pbb4";
  682. nvidia,function = "vgp4";
  683. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  684. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  685. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  686. };
  687. /* Apalis WAKE1_MICO */
  688. pex-wake-n-pdd3 {
  689. nvidia,pins = "pex_wake_n_pdd3";
  690. nvidia,function = "rsvd2";
  691. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  692. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  693. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  694. };
  695. /* CORE_PWR_REQ */
  696. core-pwr-req {
  697. nvidia,pins = "core_pwr_req";
  698. nvidia,function = "pwron";
  699. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  700. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  701. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  702. };
  703. /* CPU_PWR_REQ */
  704. cpu-pwr-req {
  705. nvidia,pins = "cpu_pwr_req";
  706. nvidia,function = "cpu";
  707. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  708. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  709. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  710. };
  711. /* DVFS */
  712. dvfs-pwm-px0 {
  713. nvidia,pins = "dvfs_pwm_px0";
  714. nvidia,function = "cldvfs";
  715. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  716. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  717. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  718. };
  719. dvfs-clk-px2 {
  720. nvidia,pins = "dvfs_clk_px2";
  721. nvidia,function = "cldvfs";
  722. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  723. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  724. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  725. };
  726. /* eMMC */
  727. sdmmc4-dat0-paa0 {
  728. nvidia,pins = "sdmmc4_dat0_paa0";
  729. nvidia,function = "sdmmc4";
  730. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  731. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  732. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  733. };
  734. sdmmc4-dat1-paa1 {
  735. nvidia,pins = "sdmmc4_dat1_paa1";
  736. nvidia,function = "sdmmc4";
  737. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  738. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  739. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  740. };
  741. sdmmc4-dat2-paa2 {
  742. nvidia,pins = "sdmmc4_dat2_paa2";
  743. nvidia,function = "sdmmc4";
  744. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  745. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  746. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  747. };
  748. sdmmc4-dat3-paa3 {
  749. nvidia,pins = "sdmmc4_dat3_paa3";
  750. nvidia,function = "sdmmc4";
  751. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  752. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  753. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  754. };
  755. sdmmc4-dat4-paa4 {
  756. nvidia,pins = "sdmmc4_dat4_paa4";
  757. nvidia,function = "sdmmc4";
  758. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  759. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  760. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  761. };
  762. sdmmc4-dat5-paa5 {
  763. nvidia,pins = "sdmmc4_dat5_paa5";
  764. nvidia,function = "sdmmc4";
  765. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  766. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  767. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  768. };
  769. sdmmc4-dat6-paa6 {
  770. nvidia,pins = "sdmmc4_dat6_paa6";
  771. nvidia,function = "sdmmc4";
  772. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  773. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  774. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  775. };
  776. sdmmc4-dat7-paa7 {
  777. nvidia,pins = "sdmmc4_dat7_paa7";
  778. nvidia,function = "sdmmc4";
  779. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  780. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  781. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  782. };
  783. sdmmc4-clk-pcc4 {
  784. nvidia,pins = "sdmmc4_clk_pcc4";
  785. nvidia,function = "sdmmc4";
  786. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  787. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  788. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  789. };
  790. sdmmc4-cmd-pt7 {
  791. nvidia,pins = "sdmmc4_cmd_pt7";
  792. nvidia,function = "sdmmc4";
  793. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  794. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  795. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  796. };
  797. /* JTAG_RTCK */
  798. jtag-rtck {
  799. nvidia,pins = "jtag_rtck";
  800. nvidia,function = "rtck";
  801. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  802. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  803. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  804. };
  805. /* LAN_DEV_OFF# */
  806. ulpi-data5-po6 {
  807. nvidia,pins = "ulpi_data5_po6";
  808. nvidia,function = "ulpi";
  809. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  810. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  811. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  812. };
  813. /* LAN_RESET# */
  814. kb-row10-ps2 {
  815. nvidia,pins = "kb_row10_ps2";
  816. nvidia,function = "rsvd2";
  817. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  818. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  819. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  820. };
  821. /* LAN_WAKE# */
  822. ulpi-data4-po5 {
  823. nvidia,pins = "ulpi_data4_po5";
  824. nvidia,function = "ulpi";
  825. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  826. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  827. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  828. };
  829. /* MCU_INT1# */
  830. pk2 {
  831. nvidia,pins = "pk2";
  832. nvidia,function = "rsvd1";
  833. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  834. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  835. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  836. };
  837. /* MCU_INT2# */
  838. pj2 {
  839. nvidia,pins = "pj2";
  840. nvidia,function = "rsvd1";
  841. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  842. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  843. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  844. };
  845. /* MCU_INT3# */
  846. pi5 {
  847. nvidia,pins = "pi5";
  848. nvidia,function = "rsvd2";
  849. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  850. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  851. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  852. };
  853. /* MCU_INT4# */
  854. pj0 {
  855. nvidia,pins = "pj0";
  856. nvidia,function = "rsvd1";
  857. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  858. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  859. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  860. };
  861. /* MCU_RESET */
  862. pbb6 {
  863. nvidia,pins = "pbb6";
  864. nvidia,function = "rsvd2";
  865. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  866. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  867. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  868. };
  869. /* MCU SPI */
  870. gpio-x4-aud-px4 {
  871. nvidia,pins = "gpio_x4_aud_px4";
  872. nvidia,function = "spi2";
  873. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  874. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  875. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  876. };
  877. gpio-x5-aud-px5 {
  878. nvidia,pins = "gpio_x5_aud_px5";
  879. nvidia,function = "spi2";
  880. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  881. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  882. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  883. };
  884. gpio-x6-aud-px6 { /* MCU_CS */
  885. nvidia,pins = "gpio_x6_aud_px6";
  886. nvidia,function = "spi2";
  887. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  888. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  889. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  890. };
  891. gpio-x7-aud-px7 {
  892. nvidia,pins = "gpio_x7_aud_px7";
  893. nvidia,function = "spi2";
  894. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  895. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  896. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  897. };
  898. gpio-w2-aud-pw2 { /* MCU_CSEZP */
  899. nvidia,pins = "gpio_w2_aud_pw2";
  900. nvidia,function = "spi2";
  901. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  902. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  903. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  904. };
  905. /* PMIC_CLK_32K */
  906. clk-32k-in {
  907. nvidia,pins = "clk_32k_in";
  908. nvidia,function = "clk";
  909. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  910. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  911. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  912. };
  913. /* PMIC_CPU_OC_INT */
  914. clk-32k-out-pa0 {
  915. nvidia,pins = "clk_32k_out_pa0";
  916. nvidia,function = "soc";
  917. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  918. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  919. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  920. };
  921. /* PWR_I2C */
  922. pwr-i2c-scl-pz6 {
  923. nvidia,pins = "pwr_i2c_scl_pz6";
  924. nvidia,function = "i2cpwr";
  925. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  926. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  927. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  928. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  929. };
  930. pwr-i2c-sda-pz7 {
  931. nvidia,pins = "pwr_i2c_sda_pz7";
  932. nvidia,function = "i2cpwr";
  933. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  934. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  935. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  936. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  937. };
  938. /* PWR_INT_N */
  939. pwr-int-n {
  940. nvidia,pins = "pwr_int_n";
  941. nvidia,function = "pmi";
  942. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  943. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  944. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  945. };
  946. /* RESET_MOCI_CTRL */
  947. pu4 {
  948. nvidia,pins = "pu4";
  949. nvidia,function = "gmi";
  950. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  951. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  952. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  953. };
  954. /* RESET_OUT_N */
  955. reset-out-n {
  956. nvidia,pins = "reset_out_n";
  957. nvidia,function = "reset_out_n";
  958. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  959. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  960. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  961. };
  962. /* SHIFT_CTRL_DIR_IN */
  963. kb-row0-pr0 {
  964. nvidia,pins = "kb_row0_pr0";
  965. nvidia,function = "rsvd2";
  966. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  967. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  968. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  969. };
  970. kb-row1-pr1 {
  971. nvidia,pins = "kb_row1_pr1";
  972. nvidia,function = "rsvd2";
  973. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  974. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  975. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  976. };
  977. /* Configure level-shifter as output for HDA */
  978. kb-row11-ps3 {
  979. nvidia,pins = "kb_row11_ps3";
  980. nvidia,function = "rsvd2";
  981. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  982. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  983. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  984. };
  985. /* SHIFT_CTRL_DIR_OUT */
  986. kb-col5-pq5 {
  987. nvidia,pins = "kb_col5_pq5";
  988. nvidia,function = "rsvd2";
  989. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  990. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  991. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  992. };
  993. kb-col6-pq6 {
  994. nvidia,pins = "kb_col6_pq6";
  995. nvidia,function = "rsvd2";
  996. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  997. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  998. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  999. };
  1000. kb-col7-pq7 {
  1001. nvidia,pins = "kb_col7_pq7";
  1002. nvidia,function = "rsvd2";
  1003. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1004. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1005. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1006. };
  1007. /* SHIFT_CTRL_OE */
  1008. kb-col0-pq0 {
  1009. nvidia,pins = "kb_col0_pq0";
  1010. nvidia,function = "rsvd2";
  1011. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1012. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1013. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1014. };
  1015. kb-col1-pq1 {
  1016. nvidia,pins = "kb_col1_pq1";
  1017. nvidia,function = "rsvd2";
  1018. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1019. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1020. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1021. };
  1022. kb-col2-pq2 {
  1023. nvidia,pins = "kb_col2_pq2";
  1024. nvidia,function = "rsvd2";
  1025. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1026. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1027. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1028. };
  1029. kb-col4-pq4 {
  1030. nvidia,pins = "kb_col4_pq4";
  1031. nvidia,function = "kbc";
  1032. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1033. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1034. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1035. };
  1036. kb-row2-pr2 {
  1037. nvidia,pins = "kb_row2_pr2";
  1038. nvidia,function = "rsvd2";
  1039. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1040. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1041. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1042. };
  1043. /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
  1044. pi6 {
  1045. nvidia,pins = "pi6";
  1046. nvidia,function = "rsvd1";
  1047. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1048. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1049. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1050. };
  1051. /* TOUCH_INT */
  1052. gpio-w3-aud-pw3 {
  1053. nvidia,pins = "gpio_w3_aud_pw3";
  1054. nvidia,function = "spi6";
  1055. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1056. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1057. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1058. };
  1059. pc7 { /* NC */
  1060. nvidia,pins = "pc7";
  1061. nvidia,function = "rsvd1";
  1062. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1063. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1064. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1065. };
  1066. pg0 { /* NC */
  1067. nvidia,pins = "pg0";
  1068. nvidia,function = "rsvd1";
  1069. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1070. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1071. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1072. };
  1073. pg1 { /* NC */
  1074. nvidia,pins = "pg1";
  1075. nvidia,function = "rsvd1";
  1076. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1077. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1078. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1079. };
  1080. pg2 { /* NC */
  1081. nvidia,pins = "pg2";
  1082. nvidia,function = "rsvd1";
  1083. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1084. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1085. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1086. };
  1087. pg3 { /* NC */
  1088. nvidia,pins = "pg3";
  1089. nvidia,function = "rsvd1";
  1090. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1091. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1092. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1093. };
  1094. pg4 { /* NC */
  1095. nvidia,pins = "pg4";
  1096. nvidia,function = "rsvd1";
  1097. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1098. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1099. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1100. };
  1101. ph4 { /* NC */
  1102. nvidia,pins = "ph4";
  1103. nvidia,function = "rsvd2";
  1104. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1105. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1106. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1107. };
  1108. ph5 { /* NC */
  1109. nvidia,pins = "ph5";
  1110. nvidia,function = "rsvd2";
  1111. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1112. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1113. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1114. };
  1115. ph6 { /* NC */
  1116. nvidia,pins = "ph6";
  1117. nvidia,function = "gmi";
  1118. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1119. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1120. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1121. };
  1122. ph7 { /* NC */
  1123. nvidia,pins = "ph7";
  1124. nvidia,function = "gmi";
  1125. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1126. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1127. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1128. };
  1129. pi0 { /* NC */
  1130. nvidia,pins = "pi0";
  1131. nvidia,function = "rsvd1";
  1132. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1133. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1134. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1135. };
  1136. pi1 { /* NC */
  1137. nvidia,pins = "pi1";
  1138. nvidia,function = "rsvd1";
  1139. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1140. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1141. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1142. };
  1143. pi2 { /* NC */
  1144. nvidia,pins = "pi2";
  1145. nvidia,function = "rsvd4";
  1146. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1147. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1148. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1149. };
  1150. pi4 { /* NC */
  1151. nvidia,pins = "pi4";
  1152. nvidia,function = "gmi";
  1153. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1154. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1155. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1156. };
  1157. pi7 { /* NC */
  1158. nvidia,pins = "pi7";
  1159. nvidia,function = "rsvd1";
  1160. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1161. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1162. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1163. };
  1164. pk0 { /* NC */
  1165. nvidia,pins = "pk0";
  1166. nvidia,function = "rsvd1";
  1167. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1168. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1169. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1170. };
  1171. pk1 { /* NC */
  1172. nvidia,pins = "pk1";
  1173. nvidia,function = "rsvd4";
  1174. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1175. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1176. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1177. };
  1178. pk3 { /* NC */
  1179. nvidia,pins = "pk3";
  1180. nvidia,function = "gmi";
  1181. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1182. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1183. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1184. };
  1185. pk4 { /* NC */
  1186. nvidia,pins = "pk4";
  1187. nvidia,function = "rsvd2";
  1188. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1189. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1190. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1191. };
  1192. dap1-fs-pn0 { /* NC */
  1193. nvidia,pins = "dap1_fs_pn0";
  1194. nvidia,function = "rsvd4";
  1195. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1196. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1197. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1198. };
  1199. dap1-din-pn1 { /* NC */
  1200. nvidia,pins = "dap1_din_pn1";
  1201. nvidia,function = "rsvd4";
  1202. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1203. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1204. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1205. };
  1206. dap1-sclk-pn3 { /* NC */
  1207. nvidia,pins = "dap1_sclk_pn3";
  1208. nvidia,function = "rsvd4";
  1209. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1210. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1211. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1212. };
  1213. ulpi-data7-po0 { /* NC */
  1214. nvidia,pins = "ulpi_data7_po0";
  1215. nvidia,function = "ulpi";
  1216. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1217. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1218. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1219. };
  1220. ulpi-data0-po1 { /* NC */
  1221. nvidia,pins = "ulpi_data0_po1";
  1222. nvidia,function = "ulpi";
  1223. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1224. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1225. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1226. };
  1227. ulpi-data1-po2 { /* NC */
  1228. nvidia,pins = "ulpi_data1_po2";
  1229. nvidia,function = "ulpi";
  1230. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1231. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1232. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1233. };
  1234. ulpi-data2-po3 { /* NC */
  1235. nvidia,pins = "ulpi_data2_po3";
  1236. nvidia,function = "ulpi";
  1237. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1238. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1239. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1240. };
  1241. ulpi-data3-po4 { /* NC */
  1242. nvidia,pins = "ulpi_data3_po4";
  1243. nvidia,function = "ulpi";
  1244. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1245. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1246. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1247. };
  1248. ulpi-data6-po7 { /* NC */
  1249. nvidia,pins = "ulpi_data6_po7";
  1250. nvidia,function = "ulpi";
  1251. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1252. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1253. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1254. };
  1255. dap4-fs-pp4 { /* NC */
  1256. nvidia,pins = "dap4_fs_pp4";
  1257. nvidia,function = "rsvd4";
  1258. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1259. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1260. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1261. };
  1262. dap4-din-pp5 { /* NC */
  1263. nvidia,pins = "dap4_din_pp5";
  1264. nvidia,function = "rsvd3";
  1265. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1266. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1267. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1268. };
  1269. dap4-dout-pp6 { /* NC */
  1270. nvidia,pins = "dap4_dout_pp6";
  1271. nvidia,function = "rsvd4";
  1272. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1273. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1274. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1275. };
  1276. dap4-sclk-pp7 { /* NC */
  1277. nvidia,pins = "dap4_sclk_pp7";
  1278. nvidia,function = "rsvd3";
  1279. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1280. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1281. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1282. };
  1283. kb-col3-pq3 { /* NC */
  1284. nvidia,pins = "kb_col3_pq3";
  1285. nvidia,function = "kbc";
  1286. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1287. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1288. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1289. };
  1290. kb-row3-pr3 { /* NC */
  1291. nvidia,pins = "kb_row3_pr3";
  1292. nvidia,function = "kbc";
  1293. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1294. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1295. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1296. };
  1297. kb-row4-pr4 { /* NC */
  1298. nvidia,pins = "kb_row4_pr4";
  1299. nvidia,function = "rsvd3";
  1300. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1301. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1302. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1303. };
  1304. kb-row5-pr5 { /* NC */
  1305. nvidia,pins = "kb_row5_pr5";
  1306. nvidia,function = "rsvd3";
  1307. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1308. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1309. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1310. };
  1311. kb-row6-pr6 { /* NC */
  1312. nvidia,pins = "kb_row6_pr6";
  1313. nvidia,function = "kbc";
  1314. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1315. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1316. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1317. };
  1318. kb-row7-pr7 { /* NC */
  1319. nvidia,pins = "kb_row7_pr7";
  1320. nvidia,function = "rsvd2";
  1321. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1322. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1323. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1324. };
  1325. kb-row8-ps0 { /* NC */
  1326. nvidia,pins = "kb_row8_ps0";
  1327. nvidia,function = "rsvd2";
  1328. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1329. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1330. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1331. };
  1332. kb-row9-ps1 { /* NC */
  1333. nvidia,pins = "kb_row9_ps1";
  1334. nvidia,function = "rsvd2";
  1335. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1336. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1337. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1338. };
  1339. kb-row12-ps4 { /* NC */
  1340. nvidia,pins = "kb_row12_ps4";
  1341. nvidia,function = "rsvd2";
  1342. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1343. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1344. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1345. };
  1346. kb-row13-ps5 { /* NC */
  1347. nvidia,pins = "kb_row13_ps5";
  1348. nvidia,function = "rsvd2";
  1349. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1350. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1351. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1352. };
  1353. kb-row14-ps6 { /* NC */
  1354. nvidia,pins = "kb_row14_ps6";
  1355. nvidia,function = "rsvd2";
  1356. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1357. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1358. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1359. };
  1360. kb-row15-ps7 { /* NC */
  1361. nvidia,pins = "kb_row15_ps7";
  1362. nvidia,function = "rsvd3";
  1363. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1364. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1365. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1366. };
  1367. kb-row16-pt0 { /* NC */
  1368. nvidia,pins = "kb_row16_pt0";
  1369. nvidia,function = "rsvd2";
  1370. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1371. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1372. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1373. };
  1374. kb-row17-pt1 { /* NC */
  1375. nvidia,pins = "kb_row17_pt1";
  1376. nvidia,function = "rsvd2";
  1377. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1378. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1379. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1380. };
  1381. pu5 { /* NC */
  1382. nvidia,pins = "pu5";
  1383. nvidia,function = "gmi";
  1384. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1385. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1386. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1387. };
  1388. pv0 { /* NC */
  1389. nvidia,pins = "pv0";
  1390. nvidia,function = "rsvd1";
  1391. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1392. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1393. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1394. };
  1395. pv1 { /* NC */
  1396. nvidia,pins = "pv1";
  1397. nvidia,function = "rsvd1";
  1398. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1399. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1400. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1401. };
  1402. gpio-x1-aud-px1 { /* NC */
  1403. nvidia,pins = "gpio_x1_aud_px1";
  1404. nvidia,function = "rsvd2";
  1405. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1406. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1407. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1408. };
  1409. gpio-x3-aud-px3 { /* NC */
  1410. nvidia,pins = "gpio_x3_aud_px3";
  1411. nvidia,function = "rsvd4";
  1412. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1413. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1414. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1415. };
  1416. pbb7 { /* NC */
  1417. nvidia,pins = "pbb7";
  1418. nvidia,function = "rsvd2";
  1419. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1420. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1421. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1422. };
  1423. pcc1 { /* NC */
  1424. nvidia,pins = "pcc1";
  1425. nvidia,function = "rsvd2";
  1426. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1427. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1428. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1429. };
  1430. pcc2 { /* NC */
  1431. nvidia,pins = "pcc2";
  1432. nvidia,function = "rsvd2";
  1433. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1434. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1435. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1436. };
  1437. clk3-req-pee1 { /* NC */
  1438. nvidia,pins = "clk3_req_pee1";
  1439. nvidia,function = "rsvd2";
  1440. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1441. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1442. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1443. };
  1444. dap-mclk1-req-pee2 { /* NC */
  1445. nvidia,pins = "dap_mclk1_req_pee2";
  1446. nvidia,function = "rsvd4";
  1447. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1448. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1449. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1450. };
  1451. /*
  1452. * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
  1453. * driver enabled aka not tristated and input driver
  1454. * enabled as well as it features some magic properties
  1455. * even though the external loopback is disabled and the
  1456. * internal loopback used as per
  1457. * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
  1458. * bits being set to 0xfffd according to the TRM!
  1459. */
  1460. sdmmc3-clk-lb-out-pee4 { /* NC */
  1461. nvidia,pins = "sdmmc3_clk_lb_out_pee4";
  1462. nvidia,function = "sdmmc3";
  1463. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1464. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1465. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1466. };
  1467. };
  1468. };
  1469. serial@70006040 {
  1470. compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
  1471. /delete-property/ reg-shift;
  1472. };
  1473. serial@70006200 {
  1474. compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
  1475. /delete-property/ reg-shift;
  1476. };
  1477. serial@70006300 {
  1478. compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
  1479. /delete-property/ reg-shift;
  1480. };
  1481. hdmi_ddc: i2c@7000c400 {
  1482. clock-frequency = <10000>;
  1483. };
  1484. /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
  1485. i2c@7000d000 {
  1486. status = "okay";
  1487. clock-frequency = <400000>;
  1488. /* SGTL5000 audio codec */
  1489. sgtl5000: codec@a {
  1490. compatible = "fsl,sgtl5000";
  1491. reg = <0x0a>;
  1492. #sound-dai-cells = <0>;
  1493. VDDA-supply = <&reg_module_3v3_audio>;
  1494. VDDD-supply = <&reg_1v8_vddio>;
  1495. VDDIO-supply = <&reg_1v8_vddio>;
  1496. clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
  1497. };
  1498. pmic: pmic@40 {
  1499. compatible = "ams,as3722";
  1500. reg = <0x40>;
  1501. interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
  1502. ams,system-power-controller;
  1503. #interrupt-cells = <2>;
  1504. interrupt-controller;
  1505. gpio-controller;
  1506. #gpio-cells = <2>;
  1507. pinctrl-names = "default";
  1508. pinctrl-0 = <&as3722_default>;
  1509. as3722_default: pinmux {
  1510. gpio2-7 {
  1511. pins = "gpio2", /* PWR_EN_+V3.3 */
  1512. "gpio7"; /* +V1.6_LPO */
  1513. function = "gpio";
  1514. bias-pull-up;
  1515. };
  1516. gpio0-1-3-4-5-6 {
  1517. pins = "gpio0", "gpio1", "gpio3",
  1518. "gpio4", "gpio5", "gpio6";
  1519. bias-high-impedance;
  1520. };
  1521. };
  1522. regulators {
  1523. vsup-sd2-supply = <&reg_module_3v3>;
  1524. vsup-sd3-supply = <&reg_module_3v3>;
  1525. vsup-sd4-supply = <&reg_module_3v3>;
  1526. vsup-sd5-supply = <&reg_module_3v3>;
  1527. vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
  1528. vin-ldo1-6-supply = <&reg_module_3v3>;
  1529. vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
  1530. vin-ldo3-4-supply = <&reg_module_3v3>;
  1531. vin-ldo9-10-supply = <&reg_module_3v3>;
  1532. vin-ldo11-supply = <&reg_module_3v3>;
  1533. reg_vdd_cpu: sd0 {
  1534. regulator-name = "+VDD_CPU_AP";
  1535. regulator-min-microvolt = <700000>;
  1536. regulator-max-microvolt = <1400000>;
  1537. regulator-min-microamp = <3500000>;
  1538. regulator-max-microamp = <3500000>;
  1539. regulator-always-on;
  1540. regulator-boot-on;
  1541. ams,ext-control = <2>;
  1542. };
  1543. sd1 {
  1544. regulator-name = "+VDD_CORE";
  1545. regulator-min-microvolt = <700000>;
  1546. regulator-max-microvolt = <1350000>;
  1547. regulator-min-microamp = <2500000>;
  1548. regulator-max-microamp = <4000000>;
  1549. regulator-always-on;
  1550. regulator-boot-on;
  1551. ams,ext-control = <1>;
  1552. };
  1553. reg_1v35_vddio_ddr: sd2 {
  1554. regulator-name =
  1555. "+V1.35_VDDIO_DDR(sd2)";
  1556. regulator-min-microvolt = <1350000>;
  1557. regulator-max-microvolt = <1350000>;
  1558. regulator-always-on;
  1559. regulator-boot-on;
  1560. };
  1561. sd3 {
  1562. regulator-name =
  1563. "+V1.35_VDDIO_DDR(sd3)";
  1564. regulator-min-microvolt = <1350000>;
  1565. regulator-max-microvolt = <1350000>;
  1566. regulator-always-on;
  1567. regulator-boot-on;
  1568. };
  1569. reg_1v05_vdd: sd4 {
  1570. regulator-name = "+V1.05";
  1571. regulator-min-microvolt = <1050000>;
  1572. regulator-max-microvolt = <1050000>;
  1573. };
  1574. reg_1v8_vddio: sd5 {
  1575. regulator-name = "+V1.8";
  1576. regulator-min-microvolt = <1800000>;
  1577. regulator-max-microvolt = <1800000>;
  1578. regulator-boot-on;
  1579. regulator-always-on;
  1580. };
  1581. reg_vdd_gpu: sd6 {
  1582. regulator-name = "+VDD_GPU_AP";
  1583. regulator-min-microvolt = <650000>;
  1584. regulator-max-microvolt = <1200000>;
  1585. regulator-min-microamp = <3500000>;
  1586. regulator-max-microamp = <3500000>;
  1587. regulator-boot-on;
  1588. regulator-always-on;
  1589. };
  1590. reg_1v05_avdd: ldo0 {
  1591. regulator-name = "+V1.05_AVDD";
  1592. regulator-min-microvolt = <1050000>;
  1593. regulator-max-microvolt = <1050000>;
  1594. regulator-boot-on;
  1595. regulator-always-on;
  1596. ams,ext-control = <1>;
  1597. };
  1598. vddio_sdmmc1: ldo1 {
  1599. regulator-name = "VDDIO_SDMMC1";
  1600. regulator-min-microvolt = <1800000>;
  1601. regulator-max-microvolt = <3300000>;
  1602. };
  1603. ldo2 {
  1604. regulator-name = "+V1.2";
  1605. regulator-min-microvolt = <1200000>;
  1606. regulator-max-microvolt = <1200000>;
  1607. regulator-boot-on;
  1608. regulator-always-on;
  1609. };
  1610. ldo3 {
  1611. regulator-name = "+V1.05_RTC";
  1612. regulator-min-microvolt = <1000000>;
  1613. regulator-max-microvolt = <1000000>;
  1614. regulator-boot-on;
  1615. regulator-always-on;
  1616. ams,enable-tracking;
  1617. };
  1618. /* 1.8V for LVDS, 3.3V for eDP */
  1619. ldo4 {
  1620. regulator-name = "AVDD_LVDS0_PLL";
  1621. regulator-min-microvolt = <1800000>;
  1622. regulator-max-microvolt = <1800000>;
  1623. };
  1624. /* LDO5 not used */
  1625. vddio_sdmmc3: ldo6 {
  1626. regulator-name = "VDDIO_SDMMC3";
  1627. regulator-min-microvolt = <1800000>;
  1628. regulator-max-microvolt = <3300000>;
  1629. };
  1630. /* LDO7 not used */
  1631. ldo9 {
  1632. regulator-name = "+V3.3_ETH(ldo9)";
  1633. regulator-min-microvolt = <3300000>;
  1634. regulator-max-microvolt = <3300000>;
  1635. regulator-always-on;
  1636. };
  1637. ldo10 {
  1638. regulator-name = "+V3.3_ETH(ldo10)";
  1639. regulator-min-microvolt = <3300000>;
  1640. regulator-max-microvolt = <3300000>;
  1641. regulator-always-on;
  1642. };
  1643. ldo11 {
  1644. regulator-name = "+V1.8_VPP_FUSE";
  1645. regulator-min-microvolt = <1800000>;
  1646. regulator-max-microvolt = <1800000>;
  1647. };
  1648. };
  1649. };
  1650. /*
  1651. * TMP451 temperature sensor
  1652. * Note: THERM_N directly connected to AS3722 PMIC THERM
  1653. */
  1654. temp-sensor@4c {
  1655. compatible = "ti,tmp451";
  1656. reg = <0x4c>;
  1657. interrupt-parent = <&gpio>;
  1658. interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_EDGE_FALLING>;
  1659. #thermal-sensor-cells = <1>;
  1660. vcc-supply = <&reg_module_3v3>;
  1661. };
  1662. };
  1663. /* SPI2: MCU SPI */
  1664. spi@7000d600 {
  1665. status = "okay";
  1666. spi-max-frequency = <25000000>;
  1667. };
  1668. pmc@7000e400 {
  1669. nvidia,invert-interrupt;
  1670. nvidia,suspend-mode = <1>;
  1671. nvidia,cpu-pwr-good-time = <500>;
  1672. nvidia,cpu-pwr-off-time = <300>;
  1673. nvidia,core-pwr-good-time = <641 3845>;
  1674. nvidia,core-pwr-off-time = <61036>;
  1675. nvidia,core-power-req-active-high;
  1676. nvidia,sys-clock-req-active-high;
  1677. /* Set power_off bit in ResetControl register of AS3722 PMIC */
  1678. i2c-thermtrip {
  1679. nvidia,i2c-controller-id = <4>;
  1680. nvidia,bus-addr = <0x40>;
  1681. nvidia,reg-addr = <0x36>;
  1682. nvidia,reg-data = <0x2>;
  1683. };
  1684. };
  1685. sata@70020000 {
  1686. phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
  1687. phy-names = "sata-0";
  1688. avdd-supply = <&reg_1v05_vdd>;
  1689. hvdd-supply = <&reg_module_3v3>;
  1690. vddio-supply = <&reg_1v05_vdd>;
  1691. };
  1692. usb@70090000 {
  1693. /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
  1694. phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
  1695. <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
  1696. <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
  1697. <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
  1698. <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
  1699. phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
  1700. avddio-pex-supply = <&reg_1v05_vdd>;
  1701. avdd-pll-erefe-supply = <&reg_1v05_avdd>;
  1702. avdd-pll-utmip-supply = <&reg_1v8_vddio>;
  1703. avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
  1704. avdd-usb-supply = <&reg_module_3v3>;
  1705. dvddio-pex-supply = <&reg_1v05_vdd>;
  1706. hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
  1707. hvdd-usb-ss-supply = <&reg_module_3v3>;
  1708. };
  1709. padctl@7009f000 {
  1710. avdd-pll-utmip-supply = <&reg_1v8_vddio>;
  1711. avdd-pll-erefe-supply = <&reg_1v05_avdd>;
  1712. avdd-pex-pll-supply = <&reg_1v05_vdd>;
  1713. hvdd-pex-pll-e-supply = <&reg_module_3v3>;
  1714. pads {
  1715. usb2 {
  1716. status = "okay";
  1717. lanes {
  1718. usb2-0 {
  1719. status = "okay";
  1720. nvidia,function = "xusb";
  1721. };
  1722. usb2-1 {
  1723. status = "okay";
  1724. nvidia,function = "xusb";
  1725. };
  1726. usb2-2 {
  1727. status = "okay";
  1728. nvidia,function = "xusb";
  1729. };
  1730. };
  1731. };
  1732. pcie {
  1733. status = "okay";
  1734. lanes {
  1735. pcie-0 {
  1736. status = "okay";
  1737. nvidia,function = "usb3-ss";
  1738. };
  1739. pcie-1 {
  1740. status = "okay";
  1741. nvidia,function = "usb3-ss";
  1742. };
  1743. pcie-2 {
  1744. status = "okay";
  1745. nvidia,function = "pcie";
  1746. };
  1747. pcie-3 {
  1748. status = "okay";
  1749. nvidia,function = "pcie";
  1750. };
  1751. pcie-4 {
  1752. status = "okay";
  1753. nvidia,function = "pcie";
  1754. };
  1755. };
  1756. };
  1757. sata {
  1758. status = "okay";
  1759. lanes {
  1760. sata-0 {
  1761. status = "okay";
  1762. nvidia,function = "sata";
  1763. };
  1764. };
  1765. };
  1766. };
  1767. ports {
  1768. /* USBO1 */
  1769. usb2-0 {
  1770. status = "okay";
  1771. mode = "otg";
  1772. usb-role-switch;
  1773. vbus-supply = <&reg_usbo1_vbus>;
  1774. };
  1775. /* USBH2 */
  1776. usb2-1 {
  1777. status = "okay";
  1778. mode = "host";
  1779. vbus-supply = <&reg_usbh_vbus>;
  1780. };
  1781. /* USBH4 */
  1782. usb2-2 {
  1783. status = "okay";
  1784. mode = "host";
  1785. vbus-supply = <&reg_usbh_vbus>;
  1786. };
  1787. usb3-0 {
  1788. status = "okay";
  1789. nvidia,usb2-companion = <2>;
  1790. vbus-supply = <&reg_usbh_vbus>;
  1791. };
  1792. usb3-1 {
  1793. status = "okay";
  1794. nvidia,usb2-companion = <0>;
  1795. vbus-supply = <&reg_usbo1_vbus>;
  1796. };
  1797. };
  1798. };
  1799. /* eMMC */
  1800. mmc@700b0600 {
  1801. status = "okay";
  1802. bus-width = <8>;
  1803. non-removable;
  1804. vmmc-supply = <&reg_module_3v3>; /* VCC */
  1805. vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
  1806. mmc-ddr-1_8v;
  1807. };
  1808. /* CPU DFLL clock */
  1809. clock@70110000 {
  1810. status = "okay";
  1811. nvidia,i2c-fs-rate = <400000>;
  1812. vdd-cpu-supply = <&reg_vdd_cpu>;
  1813. };
  1814. ahub@70300000 {
  1815. i2s@70301200 {
  1816. status = "okay";
  1817. };
  1818. };
  1819. clk32k_in: osc3 {
  1820. compatible = "fixed-clock";
  1821. #clock-cells = <0>;
  1822. clock-frequency = <32768>;
  1823. };
  1824. cpus {
  1825. cpu@0 {
  1826. vdd-cpu-supply = <&reg_vdd_cpu>;
  1827. };
  1828. };
  1829. reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
  1830. compatible = "regulator-fixed";
  1831. regulator-name = "+V1.05_AVDD_HDMI_PLL";
  1832. regulator-min-microvolt = <1050000>;
  1833. regulator-max-microvolt = <1050000>;
  1834. gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
  1835. vin-supply = <&reg_1v05_vdd>;
  1836. };
  1837. reg_3v3_mxm: regulator-3v3-mxm {
  1838. compatible = "regulator-fixed";
  1839. regulator-name = "+V3.3_MXM";
  1840. regulator-min-microvolt = <3300000>;
  1841. regulator-max-microvolt = <3300000>;
  1842. regulator-always-on;
  1843. regulator-boot-on;
  1844. };
  1845. reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
  1846. compatible = "regulator-fixed";
  1847. regulator-name = "+V3.3_AVDD_HDMI";
  1848. regulator-min-microvolt = <3300000>;
  1849. regulator-max-microvolt = <3300000>;
  1850. vin-supply = <&reg_1v05_vdd>;
  1851. };
  1852. reg_module_3v3: regulator-module-3v3 {
  1853. compatible = "regulator-fixed";
  1854. regulator-name = "+V3.3";
  1855. regulator-min-microvolt = <3300000>;
  1856. regulator-max-microvolt = <3300000>;
  1857. regulator-always-on;
  1858. regulator-boot-on;
  1859. /* PWR_EN_+V3.3 */
  1860. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  1861. enable-active-high;
  1862. vin-supply = <&reg_3v3_mxm>;
  1863. };
  1864. reg_module_3v3_audio: regulator-module-3v3-audio {
  1865. compatible = "regulator-fixed";
  1866. regulator-name = "+V3.3_AUDIO_AVDD_S";
  1867. regulator-min-microvolt = <3300000>;
  1868. regulator-max-microvolt = <3300000>;
  1869. regulator-always-on;
  1870. };
  1871. sound {
  1872. compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
  1873. "nvidia,tegra-audio-sgtl5000";
  1874. nvidia,model = "Toradex Apalis TK1";
  1875. nvidia,audio-routing =
  1876. "Headphone Jack", "HP_OUT",
  1877. "LINE_IN", "Line In Jack",
  1878. "MIC_IN", "Mic Jack";
  1879. nvidia,i2s-controller = <&tegra_i2s2>;
  1880. nvidia,audio-codec = <&sgtl5000>;
  1881. clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
  1882. <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1883. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1884. clock-names = "pll_a", "pll_a_out0", "mclk";
  1885. assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
  1886. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1887. assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1888. <&tegra_car TEGRA124_CLK_EXTERN1>;
  1889. };
  1890. thermal-zones {
  1891. cpu-thermal {
  1892. trips {
  1893. cpu-shutdown-trip {
  1894. temperature = <101000>;
  1895. hysteresis = <0>;
  1896. type = "critical";
  1897. };
  1898. };
  1899. };
  1900. mem-thermal {
  1901. trips {
  1902. mem-shutdown-trip {
  1903. temperature = <101000>;
  1904. hysteresis = <0>;
  1905. type = "critical";
  1906. };
  1907. };
  1908. };
  1909. gpu-thermal {
  1910. trips {
  1911. gpu-shutdown-trip {
  1912. temperature = <101000>;
  1913. hysteresis = <0>;
  1914. type = "critical";
  1915. };
  1916. };
  1917. };
  1918. };
  1919. };
  1920. &gpio {
  1921. /* I210 Gigabit Ethernet Controller Reset */
  1922. lan-reset-n-hog {
  1923. gpio-hog;
  1924. gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
  1925. output-high;
  1926. line-name = "LAN_RESET_N";
  1927. };
  1928. /* Control MXM3 pin 26 Reset Module Output Carrier Input */
  1929. reset-moci-ctrl-hog {
  1930. gpio-hog;
  1931. gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
  1932. output-high;
  1933. line-name = "RESET_MOCI_CTRL";
  1934. };
  1935. };